Add new parameter to vec_perm_const hook for specifying operand mode.

The rationale of the patch is to support vec_perm_expr of the form:
lhs = vec_perm_expr<rhs, mask>
where lhs and rhs are vector types with different lengths but have
same element type. For example, lhs is SVE vector and rhs
is corresponding AdvSIMD vector.

It would also allow to express extract even/odd and interleave operations
with a VEC_PERM_EXPR.  The interleave currently has the issue that we have
to artificially widen the inputs with "dont-care" elements.

gcc/ChangeLog:

	* target.def (vec_perm_const): Define new parameter op_mode and
	update doc.
	* doc/tm.texi: Regenerate.
	* config/aarch64/aarch64.cc (aarch64_vectorize_vec_perm_const): Adjust
	vec_perm_const hook to add new parameter op_mode and return false
	if result and operand modes do not match.
	* config/arm/arm.cc (arm_vectorize_vec_perm_const): Likewise.
	* config/gcn/gcn.cc (gcn_vectorize_vec_perm_const): Likewise.
	* config/ia64/ia64.cc (ia64_vectorize_vec_perm_const): Likewise.
	* config/mips/mips.cc (mips_vectorize_vec_perm_const): Likewise.
	* config/rs6000/rs6000.cc (rs6000_vectorize_vec_perm_const): Likewise
	* config/s390/s390.cc (s390_vectorize_vec_perm_const): Likewise.
	* config/sparc/sparc.cc (sparc_vectorize_vec_perm_const): Likewise.
	* config/i386/i386-expand.cc (ix86_vectorize_vec_perm_const): Likewise.
	* config/i386/i386-expand.h (ix86_vectorize_vec_perm_const): Adjust
	prototype.
	* config/i386/sse.md (ashrv4di3): Adjust call to vec_perm_const hook.
	(ashrv2di3): Likewise.
	* optabs.cc (expand_vec_perm_const): Likewise.
	* optabs-query.h (can_vec_perm_const_p): Adjust prototype.
	* optabs-query.cc (can_vec_perm_const_p): Define new parameter
	op_mode and pass it to vec_perm_const hook.
	(can_mult_highpart_p): Adjust call to can_vec_perm_const_p.
	* match.pd (vec_perm X Y CST): Likewise.
	* tree-ssa-forwprop.cc (simplify_vector_constructor): Likewise.
	* tree-vect-data-refs.cc (vect_grouped_store_supported): Likewise.
	(vect_grouped_load_supported): Likewise.
	(vect_shift_permute_load_chain): Likewise.
	* tree-vect-generic.cc (lower_vec_perm): Likewise.
	* tree-vect-loop-manip.cc (interleave_supported_p): Likewise.
	* tree-vect-loop.cc (have_whole_vector_shift): Likewise.
	* tree-vect-patterns.cc (vect_recog_rotate_pattern): Likewise.
	* tree-vect-slp.cc (can_duplicate_and_interleave_p): Likewise.
	(vect_transform_slp_perm_load): Likewise.
	(vectorizable_slp_permutation): Likewise.
	* tree-vect-stmts.cc (perm_mask_for_reverse): Likewise.
	(vectorizable_bswap): Likewise.
	(scan_store_can_perm_p): Likewise.
	(vect_gen_perm_mask_checked): Likewise.

1 files changed, 11 insertions, 7 deletions

diff --git a/gcc/target.def b/gcc/target.def
index d85adf3..2a7fa68 100644
--- a/gcc/target.def
+++ b/gcc/target.def
@@ -1878,12 +1878,16 @@ access using @var{type} is known to be naturally aligned.",
 DEFHOOK
 (vec_perm_const,
  "This hook is used to test whether the target can permute up to two\n\
-vectors of mode @var{mode} using the permutation vector @code{sel}, and\n\
-also to emit such a permutation.  In the former case @var{in0}, @var{in1}\n\
-and @var{out} are all null.  In the latter case @var{in0} and @var{in1} are\n\
-the source vectors and @var{out} is the destination vector; all three are\n\
-operands of mode @var{mode}.  @var{in1} is the same as @var{in0} if\n\
-@var{sel} describes a permutation on one vector instead of two.\n\
+vectors of mode @var{op_mode} using the permutation vector @code{sel},\n\
+producing a vector of mode @var{mode}.  The hook is also used to emit such\n\
+a permutation.\n\
+\n\
+When the hook is being used to test whether the target supports a permutation,\n\
+@var{in0}, @var{in1}, and @var{out} are all null.  When the hook is being used\n\
+to emit a permutation, @var{in0} and @var{in1} are the source vectors of mode\n\
+@var{op_mode} and @var{out} is the destination vector of mode @var{mode}.\n\
+@var{in1} is the same as @var{in0} if @var{sel} describes a permutation on one\n\
+vector instead of two.\n\
 \n\
 Return true if the operation is possible, emitting instructions for it\n\
 if rtxes are provided.\n\
@@ -1894,7 +1898,7 @@ try the equivalent byte operation.  If that also fails, it will try forcing\n\
 the selector into a register and using the @var{vec_perm@var{mode}}\n\
 instruction pattern.  There is no need for the hook to handle these two\n\
 implementation approaches itself.",
- bool, (machine_mode mode, rtx output, rtx in0, rtx in1,
+ bool, (machine_mode mode, machine_mode op_mode, rtx output, rtx in0, rtx in1,
 	const vec_perm_indices &sel),
  NULL)