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2021-05-04Remove CC0Segher Boessenkool4-309/+39
2021-04-30doc/options.texi: Fix the description of 'Negative'.Geng Qi1-2/+2
2021-04-29Generate offset adjusted operation for op_by_pieces operationsH.J. Lu2-0/+9
2021-04-28doc/install.texi: Document --enable-offload-defaulted config optionTobias Burnus1-0/+8
2021-04-27aix: TLS precompute register parameters (PR 94177)David Edelsohn2-0/+11
2021-04-26testsuite/arm: Add arm_cmse_hw effective targetChristophe Lyon1-0/+3
2021-04-26Add '-Wopenacc-parallelism'Thomas Schwinge1-1/+9
2021-04-24Add dg-final option-based target selectorsRichard Sandiford1-3/+87
2021-04-21x86: Add -mmwait for -mgeneral-regs-onlyH.J. Lu2-1/+12
2021-04-20Fix typo in param description.Martin Liska1-1/+1
2021-04-20Document ranger-logical-depth in invoke.texiMartin Liska1-0/+4
2021-04-19[OpenACC 'kernels'] '-fopenacc-kernels=[...]' -> '--param=openacc-kernels=[...]'Thomas Schwinge1-13/+11
2021-04-17d: Add TARGET_D_TEMPLATES_ALWAYS_COMDATIain Buclaw2-0/+8
2021-04-16doc: Update Power builtin documentation in user's manualBill Schmidt1-1968/+232
2021-04-15docs: remove itemx for a paramMartin Liska1-1/+0
2021-04-14d: Add TARGET_D_REGISTER_OS_TARGET_INFOIain Buclaw2-0/+7
2021-04-14d: Add TARGET_D_REGISTER_CPU_TARGET_INFOIain Buclaw2-0/+11
2021-04-14d: Add TARGET_D_HAS_STDCALL_CONVENTIONIain Buclaw2-0/+10
2021-04-12docs: fix content of smallexampleMartin Liska1-3/+3
2021-04-12docs: update symver attribute descriptionMartin Liska1-9/+19
2021-04-12Add rocketlake to gcc.Cui,Lili2-0/+11
2021-04-12Change march=alderlake ISA list and add m_ALDERLAKE to m_CORE_AVX2Cui,Lili1-4/+5
2021-04-09i386: move non-target attributes out of target sectionMartin Liska1-29/+29
2021-04-09-flto-compression-level: improve documentationMartin Liska1-4/+6
2021-04-08testsuite: Add -mbig-endian stdint.h requirementRichard Sandiford1-0/+4
2021-04-02Minor tweak to description of fdelete-dead-exceptionsEric Botcazou1-1/+1
2021-04-01doc: Fix up symver attribute documentationJakub Jelinek1-3/+3
2021-03-28doc: Update link to "Memory Model" paperGerald Pfeifer1-1/+1
2021-03-26aarch64: Take issue rate into account for vector loop costsRichard Sandiford1-0/+8
2021-03-24run sysconf-requiring test on systems that support itAlexandre Oliva1-0/+3
2021-03-23testsuite/arm: Add arm_dsp_ok effective target and use it in arm/acle/dsp_ari...Christophe Lyon1-0/+11
2021-03-23RISC-V: Support -mlittle-endian and -mbig-endianMarcus Comstedt1-0/+12
2021-03-22[PR99581] Define relaxed memory and use it for aarch64Vladimir N. Makarov1-1/+27
2021-03-12analyzer: document new paramMartin Liska1-0/+4
2021-03-11analyzer: new implementation of shortest feasible path [PR96374]David Malcolm2-11/+53
2021-03-10Add LRA target selector.John David Anglin1-0/+3
2021-03-10docs: add interactive vs batch distinction to UX guidelinesDavid Malcolm1-0/+25
2021-03-04Add input_modes parameter to TARGET_MD_ASM_ADJUST hookIlya Leoshkevich1-4/+6
2021-03-02PR middle-end/99295 - documentation on __attribute__((malloc)) is wrongMartin Sebor1-8/+11
2021-03-01dwarf2unwind : Force the CFA after remember/restore pairs [44107/48097].Iain Sandoe2-0/+6
2021-02-28typos: Fix various typos - mainly misspelled reference* [PR99304]Jakub Jelinek1-1/+1
2021-02-25c++: Rename new -flang-note-module-read option [PR 99166]Nathan Sidwell1-6/+7
2021-02-23rs6000: Add support for compatibility built-insPeter Bergner1-2/+2
2021-02-19c++: Inform of CMI reads [PR 99166]Nathan Sidwell1-3/+19
2021-02-18Add retain attribute to place symbols in SHF_GNU_RETAIN sectionH.J. Lu1-2/+6
2021-02-18c++: header-unit build capability [PR 99023]Nathan Sidwell1-1/+6
2021-02-16[PR98096] inline-asm: Take inout operands into account for access to labels b...Vladimir N. Makarov1-10/+17
2021-02-12tree-optimization/38474 - fix store-merging compile-time regressionRichard Biener1-0/+8
2021-02-07Correct typos in attribute malloc documentation.Martin Sebor1-8/+10
2021-02-04doc: mention -mprefer-vector-width in target attrsMartin Liska1-0/+22
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