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| author | Cui,Lili <lili.cui@intel.com> | 2021-04-12 09:59:25 +0800 |
|---|---|---|
| committer | liuhongt <hongtao.liu@intel.com> | 2021-04-12 15:39:52 +0800 |
| commit | f2be08339b77d3495e210d6b5d9cea927f437720 (patch) | |
| tree | e85ec8e50827a315e712055ce13bef627b1646be /gcc/doc | |
| parent | a0ecde220da1edf7062ec429aa2c7a5b4103e92f (diff) | |
| download | gcc-f2be08339b77d3495e210d6b5d9cea927f437720.zip gcc-f2be08339b77d3495e210d6b5d9cea927f437720.tar.gz gcc-f2be08339b77d3495e210d6b5d9cea927f437720.tar.bz2 | |
Change march=alderlake ISA list and add m_ALDERLAKE to m_CORE_AVX2
Alder Lake Intel Hybrid Technology will not support Intel® AVX-512. ISA
features such as Intel® AVX, AVX-VNNI, Intel® AVX2, and UMONITOR/UMWAIT/TPAUSE
are supported.
gcc/ChangeLog
* config/i386/i386.h (PTA_ALDERLAKE): Change alderlake ISA list.
* config/i386/i386-options.c (m_CORE_AVX2): Add m_ALDERLAKE.
* common/config/i386/cpuinfo.h (get_intel_cpu): Add AlderLake model.
* doc/invoke.texi: Change alderlake ISA list.
Diffstat (limited to 'gcc/doc')
| -rw-r--r-- | gcc/doc/invoke.texi | 9 |
1 files changed, 5 insertions, 4 deletions
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index 46876ea..6b585ce 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -30188,10 +30188,11 @@ instruction set support. @item alderlake Intel Alderlake CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3, SSSE3, -SSE4.1, SSE4.2, POPCNT, AVX, AVX2, AES, PCLMUL, FSGSBASE, RDRND, FMA, BMI, -BMI2, F16C, RDSEED, ADCX, PREFETCHW, CLFLUSHOPT, XSAVEC, XSAVES, CLDEMOTE, -PTWRITE, WAITPKG, SERIALIZE, KEYLOCKER, HRESET and AVX-VNNI instruction set -support. +SSE4.1, SSE4.2, POPCNT, AES, PREFETCHW, PCLMUL, RDRND, XSAVE, XSAVEC, XSAVES, +XSAVEOPT, FSGSBASE, PTWRITE, RDPID, SGX, UMIP, GFNI-SSE, CLWB, MOVDIRI, +MOVDIR64B, CLDEMOTE, WAITPKG, ADCX, AVX, AVX2, BMI, BMI2, F16C, FMA, LZCNT, +PCONFIG, PKU, VAES, VPCLMULQDQ, SERIALIZE, HRESET, KL, WIDEKL and AVX-VNNI +instruction set support. @item k6 AMD K6 CPU with MMX instruction set support. |