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2023-10-07[APX EGPR] middle-end: Add index_reg_class with insn argument.Hongyu Wang1-0/+8
2023-10-07[APX EGPR] middle-end: Add insn argument to base_reg_classKong Lingling1-0/+18
2023-09-21rust: Reintroduce TARGET_RUST_OS_INFO hookIain Buclaw1-0/+5
2023-09-21rust: Reintroduce TARGET_RUST_CPU_INFO hookIain Buclaw1-0/+13
2023-09-21rust: Add skeleton support and documentation for targetrustm hooks.Iain Buclaw1-0/+8
2023-09-06Middle-end _BitInt support [PR102989]Jakub Jelinek1-0/+15
2023-08-31Darwin: homogenize spelling of macOSFrancois-Xavier Coudert1-1/+1
2023-08-23rtl: use rtx_code for gen_ccmp_first and gen_ccmp_nextRichard Earnshaw1-2/+2
2023-08-09targhooks: Extend legitimate_address_p with code_helper [PR110248]Kewen Lin1-5/+13
2023-05-30stor-layout, aarch64: Express SRA intrinsics with RTL codesKyrylo Tkachov1-1/+13
2023-04-28Add targetm.libm_function_max_errorJakub Jelinek1-0/+15
2023-04-01aarch64, builtins: Include PR registers in FUNCTION_ARG_REGNO_P etc. [PR109254]Jakub Jelinek1-2/+4
2023-03-23Remove TARGET_GEN_MEMSET_SCRATCH_RTX since it's not used anymore.liuhongt1-7/+0
2023-03-12middle-end: Implement preferred_div_as_shifts_over_mult [PR108583]Tamar Christina1-0/+6
2023-03-12middle-end: Revert can_special_div_by_const changes [PR108583]Tamar Christina1-14/+0
2023-03-03c++, v3: Emit fundamental tinfos for _Float16/decltype(0.0bf16) types on ia32...Jakub Jelinek1-0/+9
2023-02-23**/*.texi: Reorder index entriesArsen Arsenović1-2/+2
2023-01-16Update copyright years.Jakub Jelinek1-1/+1
2023-01-03Revert "Compute a table of DWARF register sizes at compile"Florian Weimer1-4/+3
2023-01-02Compute a table of DWARF register sizes at compileFlorian Weimer1-3/+4
2022-11-25OpenMP: Generate SIMD clones for functions with "declare target"Sandra Loosemore1-1/+1
2022-11-14middle-end: Support not decomposing specific divisions during vectorization.Tamar Christina1-0/+16
2022-11-14Revert "sphinx: remove texinfo files"Martin Liska1-0/+12436
2022-11-09sphinx: remove texinfo filesMartin Liska1-12436/+0
2022-10-29d: Make TARGET_D_MINFO_SECTION hooks in elfos.h the language default.Iain Buclaw1-6/+10
2022-10-28c: tree: target: C2x (...) function prototypes and va_start relaxationJoseph Myers1-1/+3
2022-10-07Introduce DWARF_VERSION_DEFAULT and redefine for VxWorksOlivier Hainque1-0/+6
2022-09-30Document -fexcess-precision=16 in tm.texiPalmer Dabbelt1-1/+1
2022-09-09Fix "address will never be NULL" warningJan-Benedict Glaw1-1/+2
2022-09-05docs: rename DEBUGGER_REGISTER_NUMBER in texiMartin Liska1-4/+4
2022-09-05rename DBX_REGISTER_NUMBER to DEBUGGER_REGNOMartin Liska1-10/+9
2022-09-02Add TARGET_COMPUTE_MULTILIB hook to override multi-lib result.Kito Cheng1-0/+17
2022-09-02STABS: remove -gstabs and -gxcoff functionalityMartin Liska1-215/+5
2022-08-30omp-simd-clone: Allow fixed-lane vectorsAndrew Stubbs1-0/+3
2022-07-26docs: fix previsou commitMartin Liska1-1/+1
2022-07-26docs: fix crossing declaration of @defmac and @hook.Martin Liska1-7/+7
2022-05-25Add new parameter to vec_perm_const hook for specifying operand mode.Prathamesh Kulkarni1-7/+11
2022-04-01Add an assertion: the zeroed_hardregs set is a subset of all call used regs.Qing Zhao1-0/+7
2022-03-13texi + c-target.def: Fix typosTobias Burnus1-2/+2
2022-02-21aarch64: Add compiler support for Shadow Call StackDan Li1-0/+5
2022-01-17Change references of .c files to .cc filesMartin Liska1-23/+23
2022-01-04ipa-inline: Add target info into fn summary [PR102059]Kewen Lin1-0/+31
2022-01-03Update copyright years.Jakub Jelinek1-1/+1
2021-12-03Add TARGET_IFUNC_REF_LOCAL_OKH.J. Lu1-0/+5
2021-11-15IPA: Provide a mechanism to register static DTORs via cxa_atexit.Iain Sandoe1-0/+8
2021-11-04vect: Convert cost hooks to classesRichard Sandiford1-24/+1
2021-10-20calls.c: Remove some dead code and target hooksAlex Coplan1-37/+0
2021-09-17openacc: Shared memory layout optimisationJulian Brown1-1/+8
2021-09-08Support -fexcess-precision=16 which will enable FLT_EVAL_METHOD_PROMOTE_TO_FL...liuhongt1-4/+10
2021-08-16gcov: Add TARGET_GCOV_TYPE_SIZE target hookSebastian Huber1-0/+11
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