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AgeCommit message (Expand)AuthorFilesLines
2017-11-16Enable VBMI2 support [1/7]Julia Koval6-2/+16
2017-11-16GFNI enabling [4/4]Julia Koval5-0/+100
2017-11-15i386.c (x86_print_call_or_nop): Emit 5 byte nop explicitly as a stream of bytes.Uros Bizjak1-1/+2
2017-11-15altivec.h (vec_xst_be): New #define.Bill Schmidt6-233/+328
2017-11-15i386: Add X86_TUNE_EMIT_VZEROUPPERH.J. Lu3-2/+9
2017-11-15rs6000.c (rs6000_gimple_fold_builtin): Add support for folding of vector comp...Will Schmidt2-21/+114
2017-11-15arm-cpus.in (armv8_3, [...]): NewTamar Christina2-6/+27
2017-11-15arm.h (TARGET_DOTPROD): Add arm_arch8_2.Tamar Christina1-2/+3
2017-11-15Fix PR82941 and PR82942 by adding proper vzeroupper generation on SKX. Sebastian Peryt2-26/+30
2017-11-15[AArch64] Improve scheduling model for X-GeneDominik Infuehr1-44/+80
2017-11-15Use proper probability (PR target/82927)Martin Liska1-2/+6
2017-11-14rs6000.md (bswapdi2): On 32-bit ISA 3.0, don't generate the XXBRD instruction.Michael Meissner1-6/+0
2017-11-14rs6000-c.c (is_float128_p): New helper function.Michael Meissner4-131/+140
2017-11-14Adapt Solaris 12 referencesRainer Orth1-2/+2
2017-11-14rs6000.c (swap_endian_selector_for_mode): Remove le_ and be_ prefixes to swap...Carl Love1-57/+24
2017-11-14[Patch AArch64] Stop generating BSL for simple integer codeJames Greenhalgh1-14/+108
2017-11-13altivec.md (altivec_vsumsws_be): Add define_expand.Carl Love1-0/+1
2017-11-13rs6000-c.c (altivec_overloaded_builtins): Add support for builtins...Carl Love4-5/+248
2017-11-13[AArch64] More aarch64_endian_lane_rtxRichard Sandiford1-10/+8
2017-11-12[riscv] Wrap ASM_OUTPUT_LABELREF in do {} while (0)Tom de Vries1-6/+9
2017-11-12Remove semicolon after ASM_OUTPUT_ASCIITom de Vries1-1/+1
2017-11-12[cr16, powerpcspe, rs6000] Remove semicolon after ASM_OUTPUT_LABELREF macro bodyTom de Vries3-3/+3
2017-11-10rs6000.md (bswaphi2_reg): On ISA 3.0 systems, enable generating XXBRH if the ...Michael Meissner1-14/+35
2017-11-10re PR c/81117 (Improve buffer overflow checking in strncpy)Martin Sebor1-11/+11
2017-11-10GFNI enabling [3/4]Julia Koval3-0/+134
2017-11-10re PR target/82641 (Unable to enable crc32 for a certain function with target...Tamar Christina2-132/+151
2017-11-10power9.md (power9-qpdiv): Correct DFU pipe usage.Pat Haugen2-12/+18
2017-11-09[ARM] Fix cmse_nonsecure_entry return insn sizeThomas Preud'homme2-3/+13
2017-11-09rs6000: Separate shrink-wrapping for the TOC registerSegher Boessenkool1-1/+32
2017-11-09Add option to force indirect calls for x86Andi Kleen2-1/+6
2017-11-08RISC-V: Fix build errorKito Cheng3-4/+6
2017-11-08re PR target/82855 (AVX512: replace OP+movemask with OP_mask+ktest)Jakub Jelinek1-4/+4
2017-11-08[AArch64] Add STP pattern to store a vec_concat of two 64-bit registersKyrylo Tkachov3-0/+28
2017-11-08vec_merge + vec_duplicate + vec_concat simplificationKyrylo Tkachov2-0/+21
2017-11-08Simplify vec_merge of vec_duplicate with const_vectorKyrylo Tkachov2-5/+8
2017-11-08[AArch64] Simplify aarch64_can_eliminateWilco Dijkstra1-17/+5
2017-11-08[AArch64] Remove aarch64_frame_pointer_requiredWilco Dijkstra1-29/+8
2017-11-08[mips] Wrap ASM_OUTPUT_LABELREF in do {} while (0)Tom de Vries1-6/+9
2017-11-08[mips] Remove semicolon after do {} while (0) in ASM_OUTPUT_CASE_ENDTom de Vries1-1/+1
2017-11-07re PR target/82855 (AVX512: replace OP+movemask with OP_mask+ktest)Jakub Jelinek1-0/+20
2017-11-07re PR target/82855 (AVX512: replace OP+movemask with OP_mask+ktest)Jakub Jelinek2-44/+44
2017-11-07rs6000: Use isel for the cstore patternsSegher Boessenkool1-14/+119
2017-11-07Fix SSE bits dependencies.Julia Koval4-22/+22
2017-11-07re PR target/80425 (Extra inter-unit register move with zero-extension)Uros Bizjak1-11/+2
2017-11-07RISC-V: Implement movmemsiAndrew Waterman4-4/+190
2017-11-07RISC-V: Define MUSL_DYNAMIC_LINKERMichael Clark1-0/+11
2017-11-07[AArch64] Use aarch64_reg_or_imm instead of nonmemory_operandRichard Sandiford1-3/+3
2017-11-07[powerpcspe] Remove semicolon after do {} while (0) in SUBTARGET_OVERRIDE_OPT...Tom de Vries6-6/+6
2017-11-07[rs6000] Remove semicolon after do {} while (0) in SUBTARGET_OVERRIDE_OPTIONSTom de Vries6-6/+6
2017-11-07[arm] Remove semicolon after while {} do (0) in HANDLE_NARROW_SHIFT_ARITHTom de Vries1-4/+4
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