diff options
author | Jakub Jelinek <jakub@redhat.com> | 2017-11-07 21:48:35 +0100 |
---|---|---|
committer | Jakub Jelinek <jakub@gcc.gnu.org> | 2017-11-07 21:48:35 +0100 |
commit | 682d3a407696ddde5f4404e7e165b0e165bd4187 (patch) | |
tree | eefa05d9b188144c74649e4a174f0460eab7b4e3 /gcc/config | |
parent | b15ef5d3f8a611af67254cdfaf126412872ca95c (diff) | |
download | gcc-682d3a407696ddde5f4404e7e165b0e165bd4187.zip gcc-682d3a407696ddde5f4404e7e165b0e165bd4187.tar.gz gcc-682d3a407696ddde5f4404e7e165b0e165bd4187.tar.bz2 |
re PR target/82855 (AVX512: replace OP+movemask with OP_mask+ktest)
PR target/82855
* config/i386/i386.c (ix86_swap_binary_operands_p): Treat
RTX_COMM_COMPARE as commutative as well.
(ix86_binary_operator_ok): Formatting fix.
* config/i386/sse.md (*mul<mode>3<mask_name><round_name>,
*<code><mode>3<mask_name><round_saeonly_name>,
*<code><mode>3<mask_name>, *<code>tf3, *mul<mode>3<mask_name>,
*<s>mul<mode>3_highpart<mask_name>,
*vec_widen_umult_even_v16si<mask_name>,
*vec_widen_umult_even_v8si<mask_name>,
*vec_widen_umult_even_v4si<mask_name>,
*vec_widen_smult_even_v16si<mask_name>,
*vec_widen_smult_even_v8si<mask_name>, *sse4_1_mulv2siv2di3<mask_name>,
*avx2_pmaddwd, *sse2_pmaddwd, *<sse4_1_avx2>_mul<mode>3<mask_name>,
*avx2_<code><mode>3, *avx512f_<code><mode>3<mask_name>,
*sse4_1_<code><mode>3<mask_name>, *<code>v8hi3,
*sse4_1_<code><mode>3<mask_name>, *<code>v16qi3, *avx2_eq<mode>3,
<avx512>_eq<mode>3<mask_scalar_merge_name>_1, *sse4_1_eqv2di3,
*sse2_eq<mode>3, <mask_codefor><code><mode>3<mask_name>,
*<code><mode>3, *<sse2_avx2>_uavg<mode>3<mask_name>,
*<ssse3_avx2>_pmulhrsw<mode>3<mask_name>, *ssse3_pmulhrswv4hi3): Use
!(MEM_P (operands[1]) && MEM_P (operands[2])) condition instead of
ix86_binary_operator_ok. Formatting fixes.
(*<plusminus_insn><mode>3<mask_name><round_name>,
*<plusminus_insn><mode>3, *<plusminus_insn><mode>3_m): Formatting
fixes.
From-SVN: r254509
Diffstat (limited to 'gcc/config')
-rw-r--r-- | gcc/config/i386/i386.c | 5 | ||||
-rw-r--r-- | gcc/config/i386/sse.md | 83 |
2 files changed, 44 insertions, 44 deletions
diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c index c085a4e..769f189 100644 --- a/gcc/config/i386/i386.c +++ b/gcc/config/i386/i386.c @@ -19778,7 +19778,8 @@ ix86_swap_binary_operands_p (enum rtx_code code, machine_mode mode, rtx src2 = operands[2]; /* If the operation is not commutative, we can't do anything. */ - if (GET_RTX_CLASS (code) != RTX_COMM_ARITH) + if (GET_RTX_CLASS (code) != RTX_COMM_ARITH + && GET_RTX_CLASS (code) != RTX_COMM_COMPARE) return false; /* Highest priority is that src1 should match dst. */ @@ -20009,7 +20010,7 @@ ix86_binary_operator_ok (enum rtx_code code, machine_mode mode, /* If the destination is memory, we must have a matching source operand. */ if (MEM_P (dst) && !rtx_equal_p (dst, src1)) - return false; + return false; /* Source 1 cannot be a constant. */ if (CONSTANT_P (src1)) diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index 4dfb2f8..200aad6 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -1602,7 +1602,8 @@ (plusminus:VF (match_operand:VF 1 "<round_nimm_predicate>" "<comm>0,v") (match_operand:VF 2 "<round_nimm_predicate>" "xBm,<round_constraint>")))] - "TARGET_SSE && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands) && <mask_mode512bit_condition> && <round_mode512bit_condition>" + "TARGET_SSE && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands) + && <mask_mode512bit_condition> && <round_mode512bit_condition>" "@ <plusminus_mnemonic><ssemodesuffix>\t{%2, %0|%0, %2} v<plusminus_mnemonic><ssemodesuffix>\t{<round_mask_op3>%2, %1, %0<mask_operand3>|%0<mask_operand3>, %1, %2<round_mask_op3>}" @@ -1641,7 +1642,9 @@ (mult:VF (match_operand:VF 1 "<round_nimm_predicate>" "%0,v") (match_operand:VF 2 "<round_nimm_predicate>" "xBm,<round_constraint>")))] - "TARGET_SSE && ix86_binary_operator_ok (MULT, <MODE>mode, operands) && <mask_mode512bit_condition> && <round_mode512bit_condition>" + "TARGET_SSE + && !(MEM_P (operands[1]) && MEM_P (operands[2])) + && <mask_mode512bit_condition> && <round_mode512bit_condition>" "@ mul<ssemodesuffix>\t{%2, %0|%0, %2} vmul<ssemodesuffix>\t{<round_mask_op3>%2, %1, %0<mask_operand3>|%0<mask_operand3>, %1, %2<round_mask_op3>}" @@ -1953,7 +1956,8 @@ (smaxmin:VF (match_operand:VF 1 "<round_saeonly_nimm_predicate>" "%0,v") (match_operand:VF 2 "<round_saeonly_nimm_predicate>" "xBm,<round_saeonly_constraint>")))] - "TARGET_SSE && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands) + "TARGET_SSE + && !(MEM_P (operands[1]) && MEM_P (operands[2])) && <mask_mode512bit_condition> && <round_saeonly_mode512bit_condition>" "@ <maxmin_float><ssemodesuffix>\t{%2, %0|%0, %2} @@ -3197,7 +3201,7 @@ (match_operand:VF_128_256 1 "vector_operand" "%0,x,v,v") (match_operand:VF_128_256 2 "vector_operand" "xBm,xm,vm,vm")))] "TARGET_SSE && <mask_avx512vl_condition> - && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)" + && !(MEM_P (operands[1]) && MEM_P (operands[2]))" { static char buf[128]; const char *ops; @@ -3261,7 +3265,7 @@ (any_logic:VF_512 (match_operand:VF_512 1 "nonimmediate_operand" "%v") (match_operand:VF_512 2 "nonimmediate_operand" "vm")))] - "TARGET_AVX512F && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)" + "TARGET_AVX512F && !(MEM_P (operands[1]) && MEM_P (operands[2]))" { static char buf[128]; const char *ops; @@ -3515,8 +3519,7 @@ (any_logic:TF (match_operand:TF 1 "vector_operand" "%0,x,v,v") (match_operand:TF 2 "vector_operand" "xBm,xm,vm,v")))] - "TARGET_SSE - && ix86_binary_operator_ok (<CODE>, TFmode, operands)" + "TARGET_SSE && !(MEM_P (operands[1]) && MEM_P (operands[2]))" { static char buf[128]; const char *ops; @@ -9988,8 +9991,7 @@ (plusminus:VI_AVX2 (match_operand:VI_AVX2 1 "vector_operand" "<comm>0,v") (match_operand:VI_AVX2 2 "vector_operand" "xBm,vm")))] - "TARGET_SSE2 - && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)" + "TARGET_SSE2 && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)" "@ p<plusminus_mnemonic><ssemodesuffix>\t{%2, %0|%0, %2} vp<plusminus_mnemonic><ssemodesuffix>\t{%2, %1, %0<mask_operand3>|%0<mask_operand3>, %1, %2}" @@ -10007,8 +10009,7 @@ (match_operand:VI48_AVX512VL 2 "nonimmediate_operand" "vm")) (match_operand:VI48_AVX512VL 3 "vector_move_operand" "0C") (match_operand:<avx512fmaskmode> 4 "register_operand" "Yk")))] - "TARGET_AVX512F - && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)" + "TARGET_AVX512F && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)" "vp<plusminus_mnemonic><ssemodesuffix>\t{%2, %1, %0%{%4%}%N3|%0%{%4%}%N3, %1, %2}" [(set_attr "type" "sseiadd") (set_attr "prefix" "evex") @@ -10073,8 +10074,7 @@ [(set (match_operand:VI2_AVX2 0 "register_operand" "=x,v") (mult:VI2_AVX2 (match_operand:VI2_AVX2 1 "vector_operand" "%0,v") (match_operand:VI2_AVX2 2 "vector_operand" "xBm,vm")))] - "TARGET_SSE2 - && ix86_binary_operator_ok (MULT, <MODE>mode, operands) + "TARGET_SSE2 && !(MEM_P (operands[1]) && MEM_P (operands[2])) && <mask_mode512bit_condition> && <mask_avx512bw_condition>" "@ pmullw\t{%2, %0|%0, %2} @@ -10109,8 +10109,7 @@ (any_extend:<ssedoublemode> (match_operand:VI2_AVX2 2 "vector_operand" "xBm,vm"))) (const_int 16))))] - "TARGET_SSE2 - && ix86_binary_operator_ok (MULT, <MODE>mode, operands) + "TARGET_SSE2 && !(MEM_P (operands[1]) && MEM_P (operands[2])) && <mask_mode512bit_condition> && <mask_avx512bw_condition>" "@ pmulh<u>w\t{%2, %0|%0, %2} @@ -10158,7 +10157,7 @@ (const_int 4) (const_int 6) (const_int 8) (const_int 10) (const_int 12) (const_int 14)])))))] - "TARGET_AVX512F && ix86_binary_operator_ok (MULT, V16SImode, operands)" + "TARGET_AVX512F && !(MEM_P (operands[1]) && MEM_P (operands[2]))" "vpmuludq\t{%2, %1, %0<mask_operand3>|%0<mask_operand3>, %1, %2}" [(set_attr "type" "sseimul") (set_attr "prefix_extra" "1") @@ -10195,7 +10194,7 @@ (parallel [(const_int 0) (const_int 2) (const_int 4) (const_int 6)])))))] "TARGET_AVX2 && <mask_avx512vl_condition> - && ix86_binary_operator_ok (MULT, V8SImode, operands)" + && !(MEM_P (operands[1]) && MEM_P (operands[2]))" "vpmuludq\t{%2, %1, %0<mask_operand3>|%0<mask_operand3>, %1, %2}" [(set_attr "type" "sseimul") (set_attr "prefix" "maybe_evex") @@ -10227,7 +10226,7 @@ (match_operand:V4SI 2 "vector_operand" "xBm,vm") (parallel [(const_int 0) (const_int 2)])))))] "TARGET_SSE2 && <mask_avx512vl_condition> - && ix86_binary_operator_ok (MULT, V4SImode, operands)" + && !(MEM_P (operands[1]) && MEM_P (operands[2]))" "@ pmuludq\t{%2, %0|%0, %2} vpmuludq\t{%2, %1, %0<mask_operand3>|%0<mask_operand3>, %1, %2}" @@ -10274,7 +10273,7 @@ (const_int 4) (const_int 6) (const_int 8) (const_int 10) (const_int 12) (const_int 14)])))))] - "TARGET_AVX512F && ix86_binary_operator_ok (MULT, V16SImode, operands)" + "TARGET_AVX512F && !(MEM_P (operands[1]) && MEM_P (operands[2]))" "vpmuldq\t{%2, %1, %0<mask_operand3>|%0<mask_operand3>, %1, %2}" [(set_attr "type" "sseimul") (set_attr "prefix_extra" "1") @@ -10310,8 +10309,7 @@ (match_operand:V8SI 2 "nonimmediate_operand" "vm") (parallel [(const_int 0) (const_int 2) (const_int 4) (const_int 6)])))))] - "TARGET_AVX2 - && ix86_binary_operator_ok (MULT, V8SImode, operands)" + "TARGET_AVX2 && !(MEM_P (operands[1]) && MEM_P (operands[2]))" "vpmuldq\t{%2, %1, %0<mask_operand3>|%0<mask_operand3>, %1, %2}" [(set_attr "type" "sseimul") (set_attr "prefix_extra" "1") @@ -10344,7 +10342,7 @@ (match_operand:V4SI 2 "vector_operand" "YrBm,*xBm,vm") (parallel [(const_int 0) (const_int 2)])))))] "TARGET_SSE4_1 && <mask_avx512vl_condition> - && ix86_binary_operator_ok (MULT, V4SImode, operands)" + && !(MEM_P (operands[1]) && MEM_P (operands[2]))" "@ pmuldq\t{%2, %0|%0, %2} pmuldq\t{%2, %0|%0, %2} @@ -10433,7 +10431,7 @@ (const_int 5) (const_int 7) (const_int 9) (const_int 11) (const_int 13) (const_int 15)]))))))] - "TARGET_AVX2 && ix86_binary_operator_ok (MULT, V16HImode, operands)" + "TARGET_AVX2 && !(MEM_P (operands[1]) && MEM_P (operands[2]))" "vpmaddwd\t{%2, %1, %0|%0, %1, %2}" [(set_attr "type" "sseiadd") (set_attr "isa" "*,avx512bw") @@ -10489,7 +10487,7 @@ (vec_select:V4HI (match_dup 2) (parallel [(const_int 1) (const_int 3) (const_int 5) (const_int 7)]))))))] - "TARGET_SSE2 && ix86_binary_operator_ok (MULT, V8HImode, operands)" + "TARGET_SSE2 && !(MEM_P (operands[1]) && MEM_P (operands[2]))" "@ pmaddwd\t{%2, %0|%0, %2} vpmaddwd\t{%2, %1, %0|%0, %1, %2} @@ -10539,7 +10537,8 @@ (mult:VI4_AVX512F (match_operand:VI4_AVX512F 1 "vector_operand" "%0,0,v") (match_operand:VI4_AVX512F 2 "vector_operand" "YrBm,*xBm,vm")))] - "TARGET_SSE4_1 && ix86_binary_operator_ok (MULT, <MODE>mode, operands) && <mask_mode512bit_condition>" + "TARGET_SSE4_1 && !(MEM_P (operands[1]) && MEM_P (operands[2])) + && <mask_mode512bit_condition>" "@ pmulld\t{%2, %0|%0, %2} pmulld\t{%2, %0|%0, %2} @@ -10857,7 +10856,7 @@ (maxmin:VI124_256 (match_operand:VI124_256 1 "nonimmediate_operand" "%v") (match_operand:VI124_256 2 "nonimmediate_operand" "vm")))] - "TARGET_AVX2 && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)" + "TARGET_AVX2 && !(MEM_P (operands[1]) && MEM_P (operands[2]))" "vp<maxmin_int><ssemodesuffix>\t{%2, %1, %0|%0, %1, %2}" [(set_attr "type" "sseiadd") (set_attr "prefix_extra" "1") @@ -10880,7 +10879,7 @@ (maxmin:VI48_AVX512VL (match_operand:VI48_AVX512VL 1 "nonimmediate_operand" "%v") (match_operand:VI48_AVX512VL 2 "nonimmediate_operand" "vm")))] - "TARGET_AVX512F && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)" + "TARGET_AVX512F && !(MEM_P (operands[1]) && MEM_P (operands[2]))" "vp<maxmin_int><ssemodesuffix>\t{%2, %1, %0<mask_operand3>|%0<mask_operand3>, %1, %2}" [(set_attr "type" "sseiadd") (set_attr "prefix_extra" "1") @@ -10986,7 +10985,7 @@ (match_operand:VI14_128 2 "vector_operand" "YrBm,*xBm,vm")))] "TARGET_SSE4_1 && <mask_mode512bit_condition> - && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)" + && !(MEM_P (operands[1]) && MEM_P (operands[2]))" "@ p<maxmin_int><ssemodesuffix>\t{%2, %0|%0, %2} p<maxmin_int><ssemodesuffix>\t{%2, %0|%0, %2} @@ -11002,7 +11001,7 @@ (smaxmin:V8HI (match_operand:V8HI 1 "vector_operand" "%0,x,v") (match_operand:V8HI 2 "vector_operand" "xBm,xm,vm")))] - "TARGET_SSE2 && ix86_binary_operator_ok (<CODE>, V8HImode, operands)" + "TARGET_SSE2 && !(MEM_P (operands[1]) && MEM_P (operands[2]))" "@ p<maxmin_int>w\t{%2, %0|%0, %2} vp<maxmin_int>w\t{%2, %1, %0|%0, %1, %2} @@ -11071,7 +11070,7 @@ (match_operand:VI24_128 2 "vector_operand" "YrBm,*xBm,vm")))] "TARGET_SSE4_1 && <mask_mode512bit_condition> - && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)" + && !(MEM_P (operands[1]) && MEM_P (operands[2]))" "@ p<maxmin_int><ssemodesuffix>\t{%2, %0|%0, %2} p<maxmin_int><ssemodesuffix>\t{%2, %0|%0, %2} @@ -11087,7 +11086,7 @@ (umaxmin:V16QI (match_operand:V16QI 1 "vector_operand" "%0,x,v") (match_operand:V16QI 2 "vector_operand" "xBm,xm,vm")))] - "TARGET_SSE2 && ix86_binary_operator_ok (<CODE>, V16QImode, operands)" + "TARGET_SSE2 && !(MEM_P (operands[1]) && MEM_P (operands[2]))" "@ p<maxmin_int>b\t{%2, %0|%0, %2} vp<maxmin_int>b\t{%2, %1, %0|%0, %1, %2} @@ -11118,7 +11117,7 @@ (eq:VI_256 (match_operand:VI_256 1 "nonimmediate_operand" "%x") (match_operand:VI_256 2 "nonimmediate_operand" "xm")))] - "TARGET_AVX2 && ix86_binary_operator_ok (EQ, <MODE>mode, operands)" + "TARGET_AVX2 && !(MEM_P (operands[1]) && MEM_P (operands[2]))" "vpcmpeq<ssemodesuffix>\t{%2, %1, %0|%0, %1, %2}" [(set_attr "type" "ssecmp") (set_attr "prefix_extra" "1") @@ -11149,7 +11148,7 @@ [(match_operand:VI12_AVX512VL 1 "register_operand" "%v") (match_operand:VI12_AVX512VL 2 "nonimmediate_operand" "vm")] UNSPEC_MASKED_EQ))] - "TARGET_AVX512F && ix86_binary_operator_ok (EQ, <MODE>mode, operands)" + "TARGET_AVX512F && !(MEM_P (operands[1]) && MEM_P (operands[2]))" "vpcmpeq<ssemodesuffix>\t{%2, %1, %0<mask_scalar_merge_operand3>|%0<mask_scalar_merge_operand3>, %1, %2}" [(set_attr "type" "ssecmp") (set_attr "prefix_extra" "1") @@ -11162,7 +11161,7 @@ [(match_operand:VI48_AVX512VL 1 "register_operand" "%v") (match_operand:VI48_AVX512VL 2 "nonimmediate_operand" "vm")] UNSPEC_MASKED_EQ))] - "TARGET_AVX512F && ix86_binary_operator_ok (EQ, <MODE>mode, operands)" + "TARGET_AVX512F && !(MEM_P (operands[1]) && MEM_P (operands[2]))" "vpcmpeq<ssemodesuffix>\t{%2, %1, %0<mask_scalar_merge_operand3>|%0<mask_scalar_merge_operand3>, %1, %2}" [(set_attr "type" "ssecmp") (set_attr "prefix_extra" "1") @@ -11174,7 +11173,7 @@ (eq:V2DI (match_operand:V2DI 1 "vector_operand" "%0,0,x") (match_operand:V2DI 2 "vector_operand" "YrBm,*xBm,xm")))] - "TARGET_SSE4_1 && ix86_binary_operator_ok (EQ, V2DImode, operands)" + "TARGET_SSE4_1 && !(MEM_P (operands[1]) && MEM_P (operands[2]))" "@ pcmpeqq\t{%2, %0|%0, %2} pcmpeqq\t{%2, %0|%0, %2} @@ -11191,7 +11190,7 @@ (match_operand:VI124_128 1 "vector_operand" "%0,x") (match_operand:VI124_128 2 "vector_operand" "xBm,xm")))] "TARGET_SSE2 && !TARGET_XOP - && ix86_binary_operator_ok (EQ, <MODE>mode, operands)" + && !(MEM_P (operands[1]) && MEM_P (operands[2]))" "@ pcmpeq<ssemodesuffix>\t{%2, %0|%0, %2} vpcmpeq<ssemodesuffix>\t{%2, %1, %0|%0, %1, %2}" @@ -11656,7 +11655,7 @@ (match_operand:VI48_AVX_AVX512F 1 "vector_operand" "%0,x,v") (match_operand:VI48_AVX_AVX512F 2 "vector_operand" "xBm,xm,vm")))] "TARGET_SSE && <mask_mode512bit_condition> - && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)" + && !(MEM_P (operands[1]) && MEM_P (operands[2]))" { static char buf[64]; const char *ops; @@ -11753,10 +11752,10 @@ (define_insn "*<code><mode>3" [(set (match_operand:VI12_AVX_AVX512F 0 "register_operand" "=x,x,v") - (any_logic: VI12_AVX_AVX512F + (any_logic:VI12_AVX_AVX512F (match_operand:VI12_AVX_AVX512F 1 "vector_operand" "%0,x,v") (match_operand:VI12_AVX_AVX512F 2 "vector_operand" "xBm,xm,vm")))] - "TARGET_SSE && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)" + "TARGET_SSE && !(MEM_P (operands[1]) && MEM_P (operands[2]))" { static char buf[64]; const char *ops; @@ -14067,7 +14066,7 @@ (match_operand:VI12_AVX2 <mask_expand_op3> "const1_operand")) (const_int 1))))] "TARGET_SSE2 && <mask_mode512bit_condition> && <mask_avx512bw_condition> - && ix86_binary_operator_ok (PLUS, <MODE>mode, operands)" + && !(MEM_P (operands[1]) && MEM_P (operands[2]))" "@ pavg<ssemodesuffix>\t{%2, %0|%0, %2} vpavg<ssemodesuffix>\t{%2, %1, %0<mask_operand3>|%0<mask_operand3>, %1, %2}" @@ -14741,7 +14740,7 @@ (match_operand:VI2_AVX2 3 "const1_operand")) (const_int 1))))] "TARGET_SSSE3 && <mask_mode512bit_condition> && <mask_avx512bw_condition> - && ix86_binary_operator_ok (MULT, <MODE>mode, operands)" + && !(MEM_P (operands[1]) && MEM_P (operands[2]))" "@ pmulhrsw\t{%2, %0|%0, %2} vpmulhrsw\t{%2, %1, %0<mask_operand4>|%0<mask_operand4>, %1, %2} @@ -14767,7 +14766,7 @@ (const_int 14)) (match_operand:V4HI 3 "const1_operand")) (const_int 1))))] - "TARGET_SSSE3 && ix86_binary_operator_ok (MULT, V4HImode, operands)" + "TARGET_SSSE3 && !(MEM_P (operands[1]) && MEM_P (operands[2]))" "pmulhrsw\t{%2, %0|%0, %2}" [(set_attr "type" "sseimul") (set_attr "prefix_extra" "1") |