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2017-11-09[ARM] Fix cmse_nonsecure_entry return insn sizeThomas Preud'homme2-3/+13
2017-11-09rs6000: Separate shrink-wrapping for the TOC registerSegher Boessenkool1-1/+32
2017-11-09Add option to force indirect calls for x86Andi Kleen2-1/+6
2017-11-08RISC-V: Fix build errorKito Cheng3-4/+6
2017-11-08re PR target/82855 (AVX512: replace OP+movemask with OP_mask+ktest)Jakub Jelinek1-4/+4
2017-11-08[AArch64] Add STP pattern to store a vec_concat of two 64-bit registersKyrylo Tkachov3-0/+28
2017-11-08vec_merge + vec_duplicate + vec_concat simplificationKyrylo Tkachov2-0/+21
2017-11-08Simplify vec_merge of vec_duplicate with const_vectorKyrylo Tkachov2-5/+8
2017-11-08[AArch64] Simplify aarch64_can_eliminateWilco Dijkstra1-17/+5
2017-11-08[AArch64] Remove aarch64_frame_pointer_requiredWilco Dijkstra1-29/+8
2017-11-08[mips] Wrap ASM_OUTPUT_LABELREF in do {} while (0)Tom de Vries1-6/+9
2017-11-08[mips] Remove semicolon after do {} while (0) in ASM_OUTPUT_CASE_ENDTom de Vries1-1/+1
2017-11-07re PR target/82855 (AVX512: replace OP+movemask with OP_mask+ktest)Jakub Jelinek1-0/+20
2017-11-07re PR target/82855 (AVX512: replace OP+movemask with OP_mask+ktest)Jakub Jelinek2-44/+44
2017-11-07rs6000: Use isel for the cstore patternsSegher Boessenkool1-14/+119
2017-11-07Fix SSE bits dependencies.Julia Koval4-22/+22
2017-11-07re PR target/80425 (Extra inter-unit register move with zero-extension)Uros Bizjak1-11/+2
2017-11-07RISC-V: Implement movmemsiAndrew Waterman4-4/+190
2017-11-07RISC-V: Define MUSL_DYNAMIC_LINKERMichael Clark1-0/+11
2017-11-07[AArch64] Use aarch64_reg_or_imm instead of nonmemory_operandRichard Sandiford1-3/+3
2017-11-07[powerpcspe] Remove semicolon after do {} while (0) in SUBTARGET_OVERRIDE_OPT...Tom de Vries6-6/+6
2017-11-07[rs6000] Remove semicolon after do {} while (0) in SUBTARGET_OVERRIDE_OPTIONSTom de Vries6-6/+6
2017-11-07[arm] Remove semicolon after while {} do (0) in HANDLE_NARROW_SHIFT_ARITHTom de Vries1-4/+4
2017-11-07rs6000: Don't clear TARGET_ISEL implicitlySegher Boessenkool1-11/+1
2017-11-06i386: Use reference of struct ix86_frame to avoid copyH.J. Lu1-6/+3
2017-11-06[AArch64] Pass number of units to aarch64_expand_vec_perm(_const)Richard Sandiford3-11/+15
2017-11-06[AArch64] Pass number of units to aarch64_simd_vect_par_cnst_halfRichard Sandiford3-39/+40
2017-11-06[AArch64] Pass number of units to aarch64_reverse_maskRichard Sandiford3-11/+13
2017-11-06[AArch64] Add an endian_lane_rtx helper routineRichard Sandiford6-66/+80
2017-11-06rs6000-c.c (P8V_BUILTIN_VEC_REVB): Add power 8 definitions.Carl Love6-25/+146
2017-11-06[Arm] Cleanup IT attributesWilco Dijkstra6-260/+96
2017-11-06re PR target/82748 (ICE with __builtin_fabsq and __float128 in copy_to_mode_r...Michael Meissner3-108/+100
2017-11-06re PR target/82788 (wrong code with -fstack-clash-protection --param=stack-cl...Jeff Law1-23/+34
2017-11-06[gcc]Bill Schmidt1-1/+44
2017-11-06[ARM] PR 67591 ARM v8 Thumb IT blocks are deprecated part 2Christophe Lyon1-0/+3
2017-11-06rs6000: Implement insn_cost for mfcr, mfcrfSegher Boessenkool1-0/+2
2017-11-05Remove semicolon after ASM_OUTPUT_BEFORE_CASE_LABEL macro bodyTom de Vries5-7/+7
2017-11-05RISC-V: Emit "i" suffix for instructions with immediate operandsMichael Clark2-19/+25
2017-11-05RISC-V: If -m[no-]strict-align is not passed, assume its value from -mtuneAndrew Waterman1-1/+5
2017-11-05RISC-V: Set SLOW_BYTE_ACCESS=1Andrew Waterman1-1/+6
2017-11-04PR target/82002 Part 2: Correct non-immediate offset/invalid INSNDaniel Santos1-13/+49
2017-11-03i386.c (ix86_emit_restore_reg_using_pop): Prototype.Jeff Law1-2/+10
2017-11-03Improve aarch64_legitimate_constant_pWilco Dijkstra1-30/+28
2017-11-03i386.c (ix86_expand_prologue): Tighten assert for int_registers_saved.Jeff Law1-2/+6
2017-11-03re PR c++/82768 (ICE in synthesize_implicit_template_parm, at cp/parser.c:39338)Wilco Dijkstra1-9/+1
2017-11-03rs6000: Remove rs6000_emit_sISELSegher Boessenkool3-12/+3
2017-11-03Set default sched pressure algorithmWilco Dijkstra1-0/+5
2017-11-03RISC-V: Handle non-legitimate address in riscv_legitimize_moveKito Cheng1-0/+16
2017-11-03rs6000: Improve *lt0 patternsSegher Boessenkool1-4/+12
2017-11-03rs6000: move_from_CR_ov_bit is TARGET_PAIRED_FLOAT, not TARGET_ISELSegher Boessenkool1-1/+1
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