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Age
Commit message (
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Author
Files
Lines
2017-11-09
Add option to force indirect calls for x86
Andi Kleen
2
-1
/
+6
2017-11-08
RISC-V: Fix build error
Kito Cheng
3
-4
/
+6
2017-11-08
re PR target/82855 (AVX512: replace OP+movemask with OP_mask+ktest)
Jakub Jelinek
1
-4
/
+4
2017-11-08
[AArch64] Add STP pattern to store a vec_concat of two 64-bit registers
Kyrylo Tkachov
3
-0
/
+28
2017-11-08
vec_merge + vec_duplicate + vec_concat simplification
Kyrylo Tkachov
2
-0
/
+21
2017-11-08
Simplify vec_merge of vec_duplicate with const_vector
Kyrylo Tkachov
2
-5
/
+8
2017-11-08
[AArch64] Simplify aarch64_can_eliminate
Wilco Dijkstra
1
-17
/
+5
2017-11-08
[AArch64] Remove aarch64_frame_pointer_required
Wilco Dijkstra
1
-29
/
+8
2017-11-08
[mips] Wrap ASM_OUTPUT_LABELREF in do {} while (0)
Tom de Vries
1
-6
/
+9
2017-11-08
[mips] Remove semicolon after do {} while (0) in ASM_OUTPUT_CASE_END
Tom de Vries
1
-1
/
+1
2017-11-07
re PR target/82855 (AVX512: replace OP+movemask with OP_mask+ktest)
Jakub Jelinek
1
-0
/
+20
2017-11-07
re PR target/82855 (AVX512: replace OP+movemask with OP_mask+ktest)
Jakub Jelinek
2
-44
/
+44
2017-11-07
rs6000: Use isel for the cstore patterns
Segher Boessenkool
1
-14
/
+119
2017-11-07
Fix SSE bits dependencies.
Julia Koval
4
-22
/
+22
2017-11-07
re PR target/80425 (Extra inter-unit register move with zero-extension)
Uros Bizjak
1
-11
/
+2
2017-11-07
RISC-V: Implement movmemsi
Andrew Waterman
4
-4
/
+190
2017-11-07
RISC-V: Define MUSL_DYNAMIC_LINKER
Michael Clark
1
-0
/
+11
2017-11-07
[AArch64] Use aarch64_reg_or_imm instead of nonmemory_operand
Richard Sandiford
1
-3
/
+3
2017-11-07
[powerpcspe] Remove semicolon after do {} while (0) in SUBTARGET_OVERRIDE_OPT...
Tom de Vries
6
-6
/
+6
2017-11-07
[rs6000] Remove semicolon after do {} while (0) in SUBTARGET_OVERRIDE_OPTIONS
Tom de Vries
6
-6
/
+6
2017-11-07
[arm] Remove semicolon after while {} do (0) in HANDLE_NARROW_SHIFT_ARITH
Tom de Vries
1
-4
/
+4
2017-11-07
rs6000: Don't clear TARGET_ISEL implicitly
Segher Boessenkool
1
-11
/
+1
2017-11-06
i386: Use reference of struct ix86_frame to avoid copy
H.J. Lu
1
-6
/
+3
2017-11-06
[AArch64] Pass number of units to aarch64_expand_vec_perm(_const)
Richard Sandiford
3
-11
/
+15
2017-11-06
[AArch64] Pass number of units to aarch64_simd_vect_par_cnst_half
Richard Sandiford
3
-39
/
+40
2017-11-06
[AArch64] Pass number of units to aarch64_reverse_mask
Richard Sandiford
3
-11
/
+13
2017-11-06
[AArch64] Add an endian_lane_rtx helper routine
Richard Sandiford
6
-66
/
+80
2017-11-06
rs6000-c.c (P8V_BUILTIN_VEC_REVB): Add power 8 definitions.
Carl Love
6
-25
/
+146
2017-11-06
[Arm] Cleanup IT attributes
Wilco Dijkstra
6
-260
/
+96
2017-11-06
re PR target/82748 (ICE with __builtin_fabsq and __float128 in copy_to_mode_r...
Michael Meissner
3
-108
/
+100
2017-11-06
re PR target/82788 (wrong code with -fstack-clash-protection --param=stack-cl...
Jeff Law
1
-23
/
+34
2017-11-06
[gcc]
Bill Schmidt
1
-1
/
+44
2017-11-06
[ARM] PR 67591 ARM v8 Thumb IT blocks are deprecated part 2
Christophe Lyon
1
-0
/
+3
2017-11-06
rs6000: Implement insn_cost for mfcr, mfcrf
Segher Boessenkool
1
-0
/
+2
2017-11-05
Remove semicolon after ASM_OUTPUT_BEFORE_CASE_LABEL macro body
Tom de Vries
5
-7
/
+7
2017-11-05
RISC-V: Emit "i" suffix for instructions with immediate operands
Michael Clark
2
-19
/
+25
2017-11-05
RISC-V: If -m[no-]strict-align is not passed, assume its value from -mtune
Andrew Waterman
1
-1
/
+5
2017-11-05
RISC-V: Set SLOW_BYTE_ACCESS=1
Andrew Waterman
1
-1
/
+6
2017-11-04
PR target/82002 Part 2: Correct non-immediate offset/invalid INSN
Daniel Santos
1
-13
/
+49
2017-11-03
i386.c (ix86_emit_restore_reg_using_pop): Prototype.
Jeff Law
1
-2
/
+10
2017-11-03
Improve aarch64_legitimate_constant_p
Wilco Dijkstra
1
-30
/
+28
2017-11-03
i386.c (ix86_expand_prologue): Tighten assert for int_registers_saved.
Jeff Law
1
-2
/
+6
2017-11-03
re PR c++/82768 (ICE in synthesize_implicit_template_parm, at cp/parser.c:39338)
Wilco Dijkstra
1
-9
/
+1
2017-11-03
rs6000: Remove rs6000_emit_sISEL
Segher Boessenkool
3
-12
/
+3
2017-11-03
Set default sched pressure algorithm
Wilco Dijkstra
1
-0
/
+5
2017-11-03
RISC-V: Handle non-legitimate address in riscv_legitimize_move
Kito Cheng
1
-0
/
+16
2017-11-03
rs6000: Improve *lt0 patterns
Segher Boessenkool
1
-4
/
+12
2017-11-03
rs6000: move_from_CR_ov_bit is TARGET_PAIRED_FLOAT, not TARGET_ISEL
Segher Boessenkool
1
-1
/
+1
2017-11-03
[aarch64] Add Qualcomm saphira CPU support.
Siddhesh Poyarekar
3
-1
/
+34
2017-11-03
[ARC] Fix to unwinding.
Cupertino Miranda
2
-6
/
+38
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