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Age
Commit message (
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Author
Files
Lines
2022-10-27
RISC-V: Target support for z*inx extension.
Jiawei
4
-44
/
+46
2022-10-27
RISC-V: Minimal support of z*inx extension.
Jiawei
3
-0
/
+18
2022-10-26
bpf: add preserve_field_info builtin
David Faust
3
-75
/
+334
2022-10-26
xtensa: Fix out-of-bounds array access in the movdi pattern
Takayuki 'January June' Suwa
1
-3
/
+4
2022-10-26
RISC-V: Fix epilogue generation for barrier.
Ju-Zhe Zhong
1
-2
/
+2
2022-10-26
RISC-V: ADJUST_NUNITS according to -march.
Ju-Zhe Zhong
5
-53
/
+50
2022-10-26
RISC-V: Support load/store in mov<mode> pattern for RVV modes.
Ju-Zhe Zhong
11
-27
/
+645
2022-10-26
RISC-V: Recognized Svinval and Svnapot extensions
Monk Chiang
2
-0
/
+9
2022-10-26
RISC-V: Adjust table indentation in commnet for riscv-modes.def
Ju-Zhe Zhong
1
-23
/
+23
2022-10-26
rs6000: cannot_force_const_mem for HIGH code rtx[PR106460]
Jiufu Guo
1
-2
/
+5
2022-10-25
rs6000: Add CCANY; replace <un>signed by <mode:CCANY>
Segher Boessenkool
3
-20
/
+19
2022-10-25
Remove znver4 instruction reservations
Tejas Joshi
1
-813
/
+36
2022-10-25
MIPS: add builtime option for -mcompact-branches
YunQiang Su
1
-1
/
+2
2022-10-25
MIPS: Not trigger error for pre-R6 and -mcompact-branches=always
YunQiang Su
2
-15
/
+15
2022-10-25
MIPS: fix building on multiarch platform
YunQiang Su
2
-1
/
+22
2022-10-24
[AArch64] Improve immediate expansion [PR106583]
Wilco Dijkstra
1
-225
/
+260
2022-10-24
RISC-V: Support --target-help for -mcpu/-mtune
Kito Cheng
2
-10
/
+34
2022-10-24
RISC-V: Support (set (mem) (const_poly_int))
Ju-Zhe Zhong
1
-0
/
+12
2022-10-24
RISC-V: Replace CONSTEXPR with constexpr
Ju-Zhe Zhong
4
-11
/
+11
2022-10-24
RISC-V: Remove unused TI/TF vector modes.
Ju-Zhe Zhong
1
-4
/
+0
2022-10-24
RISC-V: Fix REG_CLASS_CONTENTS.
Ju-Zhe Zhong
1
-1
/
+1
2022-10-22
Fix uninitialized variable warnings.
Michael Eager
1
-5
/
+14
2022-10-22
xtensa: Make register A0 allocable for the CALL0 ABI
Takayuki 'January June' Suwa
1
-4
/
+10
2022-10-21
i386: Fix up BFmode comparisons in conditional moves [PR107322]
Jakub Jelinek
1
-0
/
+37
2022-10-21
Enable AMD znver4 support and add instruction reservations
Tejas Joshi
9
-41
/
+983
2022-10-21
RISC-V: Add type attribute for atomic instructions.
Monk Chiang
2
-6
/
+11
2022-10-21
RISC-V: Add RVV vsetvl/vsetvlmax intrinsics and tests.
Ju-Zhe Zhong
11
-1
/
+549
2022-10-21
RISC-V: Add RVV intrinsic basic framework.
Ju-Zhe Zhong
5
-81
/
+1063
2022-10-21
i386: Auto vectorize sdot_prod, udot_prod with VNNIINT8 instruction.
Haochen Jiang
1
-11
/
+50
2022-10-21
Support Intel AVX-VNNI-INT8
Kong Lingling
9
-21
/
+217
2022-10-21
Support Intel AVX-IFMA
Hongyu Wang
13
-68
/
+195
2022-10-20
amdgcn: Use FLAT addressing for all functions with pointer arguments [PR105421]
Julian Brown
1
-6
/
+9
2022-10-20
aarch64: Commonise some folding code
Richard Sandiford
3
-7
/
+10
2022-10-20
aarch64: Use using directives to inherit constructors
Richard Sandiford
3
-87
/
+24
2022-10-20
aarch64: Replace CONSTEXPR with constexpr
Richard Sandiford
5
-83
/
+83
2022-10-20
aarch64: Prevent generation of /M BRKAS and BRKBS
Richard Sandiford
1
-14
/
+10
2022-10-20
aarch64: Fix matching of BRKNS
Richard Sandiford
2
-8
/
+64
2022-10-19
gcc: Add 'mcf' thread model support from mcfgthread
LIU Hao
2
-1
/
+13
2022-10-19
IBM zSystems: Fix function_ok_for_sibcall [PR106355]
Stefan Schulze Frielinghaus
1
-23
/
+24
2022-10-19
xtensa: Prepare the transition from Reload to LRA
Takayuki 'January June' Suwa
7
-24
/
+99
2022-10-19
s390: Fix bootstrap error with checking and -m31.
Robin Dapp
1
-3
/
+4
2022-10-19
i386: Fix up __bf16 handling on ia32
Jakub Jelinek
2
-10
/
+9
2022-10-19
Canonicalize vec_perm index to make the first index come from the first vector.
liuhongt
1
-0
/
+17
2022-10-17
Fix bogus RTL on the H8.
Jeff Law
2
-41
/
+69
2022-10-17
More infrastructure to avoid bogus RTL on H8.
Jeff Law
3
-0
/
+35
2022-10-17
Remove accidential commits
Jeff Law
12
-31671
/
+0
2022-10-17
Enable REE for H8
Jeff Law
12
-0
/
+31671
2022-10-17
Add missing splitter for H8
Jeff Law
1
-0
/
+18
2022-10-17
GCN: Restore build with GCC 4.8
Thomas Schwinge
1
-7
/
+7
2022-10-17
RISC-V: Fix format[NFC]
Ju-Zhe Zhong
1
-1
/
+1
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