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| author | Ju-Zhe Zhong <juzhe.zhong@rivai.ai> | 2022-10-24 10:03:12 +0800 |
|---|---|---|
| committer | Kito Cheng <kito.cheng@sifive.com> | 2022-10-24 10:31:06 +0800 |
| commit | 6bfea64164c3f1989d34656ab96d03a7cda2143e (patch) | |
| tree | 60ba85c8451b9fbd21889ba505efa09c0c0c33a4 /gcc/config | |
| parent | f84e4fb44aa26b71fbc64e0532fd24d96e5caa3f (diff) | |
| download | gcc-6bfea64164c3f1989d34656ab96d03a7cda2143e.zip gcc-6bfea64164c3f1989d34656ab96d03a7cda2143e.tar.gz gcc-6bfea64164c3f1989d34656ab96d03a7cda2143e.tar.bz2 | |
RISC-V: Support (set (mem) (const_poly_int))
gcc/ChangeLog:
* config/riscv/riscv.cc (riscv_legitimize_move): Support (set (mem) (const_poly_int)).
Diffstat (limited to 'gcc/config')
| -rw-r--r-- | gcc/config/riscv/riscv.cc | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index 90a3904..53a91a1 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -1958,6 +1958,18 @@ riscv_legitimize_move (machine_mode mode, rtx dest, rtx src) { if (CONST_POLY_INT_P (src)) { + /* + Handle: + (insn 183 182 184 6 (set (mem:QI (plus:DI (reg/f:DI 156) + (const_int 96 [0x60])) [0 S1 A8]) + (const_poly_int:QI [8, 8])) + "../../../../riscv-gcc/libgcc/unwind-dw2.c":1579:3 -1 (nil)) + */ + if (MEM_P (dest)) + { + emit_move_insn (dest, force_reg (mode, src)); + return true; + } poly_int64 value = rtx_to_poly_int64 (src); if (!value.is_constant () && !TARGET_VECTOR) { |