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gcc/ChangeLog:
PR target/106742
* config/i386/i386-expand.cc (ix86_expand_vector_init_duplicate):
Handle V8BF mode.
(expand_vec_perm_broadcast_1): Ditto.
* config/i386/sse.md (avx512fmaskhalfmode): Add BF vector mode.
(vec_set<mode>_0): Add @ to it.
(@vec_set<mode>_0): Ditto.
(vec_interleave_high<mode><mask_name>): Ditto.
(@vec_interleave_high<mode><mask_name>): Ditto.
(vec_interleave_low<mode><mask_name>): Ditto.
(@vec_interleave_low<mode><mask_name>): Ditto.
* config/i386/subst.md (SUBST_V): Add BF vector mode.
gcc/testsuite/ChangeLog:
* gcc.target/i386/pr106742.c: New test.
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Similar to the rs6000 code, nvptx defines ASM_OUTPUT_DEF_FROM_DECLS as well as
ASM_OUTPUT_DEF. Make sure that the define's parameters are used by referencing
them as (void) to silence a warning in output_constant_pool_contents().
2022-09-30 Jan-Benedict Glaw <jbglaw@lug-owl.de>
gcc/
* config/nvptx/nvptx.h (ASM_OUTPUT_DEF): Reference macro arguments.
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This moves all D front-end specific target definitions out of the main
target headers, and into its own header that is included by tm_d.h
instead of pulling in the same headers as tm_p.h.
This fixes the build on target configurations that pull in the default D
language target hooks, and subsequently trigger an error because the
definition of PREFERRED_DEBUGGING_TYPE is behind tm.h, the one header
that is avoided from being included in default-d.cc.
PR d/105659
gcc/ChangeLog:
* config.gcc: Set tm_d_file to ${cpu_type}/${cpu_type}-d.h.
* config/aarch64/aarch64-d.cc: Include tm_d.h.
* config/aarch64/aarch64-protos.h (aarch64_d_target_versions): Move to
config/aarch64/aarch64-d.h.
(aarch64_d_register_target_info): Likewise.
* config/aarch64/aarch64.h (TARGET_D_CPU_VERSIONS): Likewise.
(TARGET_D_REGISTER_CPU_TARGET_INFO): Likewise.
* config/arm/arm-d.cc: Include tm_d.h and arm-protos.h instead of
tm_p.h.
* config/arm/arm-protos.h (arm_d_target_versions): Move to
config/arm/arm-d.h.
(arm_d_register_target_info): Likewise.
* config/arm/arm.h (TARGET_D_CPU_VERSIONS): Likewise.
(TARGET_D_REGISTER_CPU_TARGET_INFO): Likewise.
* config/default-d.cc: Remove memmodel.h include.
* config/freebsd-d.cc: Include tm_d.h instead of tm_p.h.
* config/glibc-d.cc: Likewise.
* config/i386/i386-d.cc: Include tm_d.h.
* config/i386/i386-protos.h (ix86_d_target_versions): Move to
config/i386/i386-d.h.
(ix86_d_register_target_info): Likewise.
(ix86_d_has_stdcall_convention): Likewise.
* config/i386/i386.h (TARGET_D_CPU_VERSIONS): Likewise.
(TARGET_D_REGISTER_CPU_TARGET_INFO): Likewise.
(TARGET_D_HAS_STDCALL_CONVENTION): Likewise.
* config/i386/winnt-d.cc: Include tm_d.h instead of tm_p.h.
* config/mips/mips-d.cc: Include tm_d.h.
* config/mips/mips-protos.h (mips_d_target_versions): Move to
config/mips/mips-d.h.
(mips_d_register_target_info): Likewise.
* config/mips/mips.h (TARGET_D_CPU_VERSIONS): Likewise.
(TARGET_D_REGISTER_CPU_TARGET_INFO): Likewise.
* config/netbsd-d.cc: Include tm_d.h instead of tm.h and memmodel.h.
* config/openbsd-d.cc: Likewise.
* config/pa/pa-d.cc: Include tm_d.h.
* config/pa/pa-protos.h (pa_d_target_versions): Move to
config/pa/pa-d.h.
(pa_d_register_target_info): Likewise.
* config/pa/pa.h (TARGET_D_CPU_VERSIONS): Likewise.
(TARGET_D_REGISTER_CPU_TARGET_INFO): Likewise.
* config/riscv/riscv-d.cc: Include tm_d.h.
* config/riscv/riscv-protos.h (riscv_d_target_versions): Move to
config/riscv/riscv-d.h.
(riscv_d_register_target_info): Likewise.
* config/riscv/riscv.h (TARGET_D_CPU_VERSIONS): Likewise.
(TARGET_D_REGISTER_CPU_TARGET_INFO): Likewise.
* config/rs6000/rs6000-d.cc: Include tm_d.h.
* config/rs6000/rs6000-protos.h (rs6000_d_target_versions): Move to
config/rs6000/rs6000-d.h.
(rs6000_d_register_target_info): Likewise.
* config/rs6000/rs6000.h (TARGET_D_CPU_VERSIONS) Likewise.:
(TARGET_D_REGISTER_CPU_TARGET_INFO) Likewise.:
* config/s390/s390-d.cc: Include tm_d.h.
* config/s390/s390-protos.h (s390_d_target_versions): Move to
config/s390/s390-d.h.
(s390_d_register_target_info): Likewise.
* config/s390/s390.h (TARGET_D_CPU_VERSIONS): Likewise.
(TARGET_D_REGISTER_CPU_TARGET_INFO): Likewise.
* config/sol2-d.cc: Include tm_d.h instead of tm.h and memmodel.h.
* config/sparc/sparc-d.cc: Include tm_d.h.
* config/sparc/sparc-protos.h (sparc_d_target_versions): Move to
config/sparc/sparc-d.h.
(sparc_d_register_target_info): Likewise.
* config/sparc/sparc.h (TARGET_D_CPU_VERSIONS): Likewise.
(TARGET_D_REGISTER_CPU_TARGET_INFO): Likewise.
* configure: Regenerate.
* configure.ac (tm_d_file): Remove defaults.h.
(tm_d_include_list): Remove options.h and insn-constants.h.
* config/aarch64/aarch64-d.h: New file.
* config/arm/arm-d.h: New file.
* config/i386/i386-d.h: New file.
* config/mips/mips-d.h: New file.
* config/pa/pa-d.h: New file.
* config/riscv/riscv-d.h: New file.
* config/rs6000/rs6000-d.h: New file.
* config/s390/s390-d.h: New file.
* config/sparc/sparc-d.h: New file.
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When we cast pointers to our opaque MMA pointers, use NOP_EXPR rather
than VIEW_CONVERT_EXPR.
2022-09-02 Peter Bergner <bergner@linux.ibm.com>
gcc/
* config/rs6000/rs6000-builtin.cc (rs6000_gimple_fold_mma_builtin): Use
NOP_EXPR for MMA pointer casting.
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Use TARGET_COMPUTE_MULTILIB to search the multi-lib reuse for riscv*-*-elf*,
according following rules:
1. Check ABI is same.
2. Check both has atomic extension or both don't have atomic extension.
- Because mix soft and hard atomic operation doesn't make sense and
won't work as expect.
3. Check current arch is superset of the target multi-lib arch.
- It might result slower performance or larger code size, but it
safe to run.
4. Pick most match multi-lib set if more than one multi-lib are pass
the above checking.
Example for how to select multi-lib:
We build code with -march=rv32imaf and -mabi=ilp32, and we have
following 5 multi-lib set:
1. rv32ia/ilp32
2. rv32ima/ilp32
3. rv32imf/ilp32
4. rv32imaf/ilp32f
5. rv32imafd/ilp32
The first and second multi-lib is safe to like, 3rd multi-lib can't
re-use becasue it don't have atomic extension, which is mismatch according
rule 2, and the 4th multi-lib can't re-use too due to the ABI mismatch,
the last multi-lib can't use since current arch is not superset of the
arch of multi-lib.
And emit error if not found suitable multi-lib set, the error message
only emit when link with standard libraries.
Example for when error will be emitted:
$ riscv64-unknown-elf-gcc -print-multi-lib
.;
rv32i/ilp32;@march=rv32i@mabi=ilp32
rv32im/ilp32;@march=rv32im@mabi=ilp32
rv32iac/ilp32;@march=rv32iac@mabi=ilp32
rv32imac/ilp32;@march=rv32imac@mabi=ilp32
rv32imafc/ilp32f;@march=rv32imafc@mabi=ilp32f
rv64imac/lp64;@march=rv64imac@mabi=lp64
// No actual linking, so no error emitted.
$ riscv64-unknown-elf-gcc -print-multi-directory -march=rv32ia -mabi=ilp32
.
// Link to default libc and libgcc, so check the multi-lib, and emit
// error because not found suitable multilib.
$ riscv64-unknown-elf-gcc -march=rv32ia -mabi=ilp32 ~/hello.c
riscv64-unknown-elf-gcc: fatal error: can't found suitable multilib set for '-march=rv32ia'/'-mabi=ilp32'
compilation terminated.
// No error emitted, because not link to stdlib.
$ riscv64-unknown-elf-gcc -march=rv32ia -mabi=ilp32 ~/hello.c -nostdlib
// No error emitted, because compile only.
$ riscv64-unknown-elf-gcc -march=rv32ia -mabi=ilp32 ~/hello.c -c
gcc/ChangeLog:
* common/config/riscv/riscv-common.cc: Include <vector>.
(struct riscv_multi_lib_info_t): New.
(riscv_subset_list::match_score): Ditto.
(find_last_appear_switch): Ditto.
(prefixed_with): Ditto.
(struct multi_lib_info_t): Ditto.
(riscv_current_arch_str): Ditto.
(riscv_current_abi_str): Ditto.
(riscv_multi_lib_info_t::parse): Ditto.
(riscv_check_cond): Ditto.
(riscv_check_conds): Ditto.
(riscv_compute_multilib): Ditto.
(TARGET_COMPUTE_MULTILIB): Defined.
* config/riscv/elf.h (LIB_SPEC): Call riscv_multi_lib_check if
doing link.
(RISCV_USE_CUSTOMISED_MULTI_LIB): New.
* config/riscv/riscv.h (riscv_multi_lib_check): New.
(EXTRA_SPEC_FUNCTIONS): Add riscv_multi_lib_check.
* config/riscv/riscv-subset.h (riscv_subset_list::match_score): New.
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gcc/ChangeLog:
* config/pdp11/pdp11.h (PREFERRED_DEBUGGING_TYPE): Disable
debugging format.
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gcc/ChangeLog:
* Makefile.in: Remove -gstabs option support, DBX-related
macros and DBX debugging info support.
* collect2.cc (scan_prog_file): Likewise.
* common.opt: Likewise.
* config.gcc: Likewise.
* config.in: Likewise.
* config/aarch64/aarch64-elf.h (DBX_DEBUGGING_INFO): Likewise.
* config/alpha/alpha.cc: Likewise.
* config/alpha/elf.h (ASM_SPEC): Likewise.
* config/arc/arc.h (DBX_DEBUGGING_INFO): Likewise.
(DBX_CONTIN_LENGTH): Likewise.
* config/arm/aout.h (DBX_DEBUGGING_INFO): Likewise.
(DBX_CONTIN_LENGTH): Likewise.
* config/arm/netbsd-elf.h (DBX_CONTIN_LENGTH): Likewise.
* config/darwin.h (DSYMUTIL_SPEC): Likewise.
(ASM_DEBUG_SPEC): Likewise.
(DBX_DEBUGGING_INFO): Likewise.
(DBX_USE_BINCL): Likewise.
(DBX_CONTIN_LENGTH): Likewise.
(DBX_OUTPUT_NULL_N_SO_AT_MAIN_SOURCE_FILE_END): Likewise.
* config/epiphany/epiphany.h (DBX_DEBUGGING_INFO): Likewise.
(DBX_CONTIN_LENGTH): Likewise.
* config/i386/bsd.h (DBX_NO_XREFS): Likewise.
(DBX_CONTIN_LENGTH): Likewise.
* config/i386/gas.h (DBX_NO_XREFS): Likewise.
(DBX_CONTIN_LENGTH): Likewise.
* config/ia64/ia64.h: Likewise.
* config/ia64/sysv4.h (DBX_DEBUGGING_INFO): Likewise.
* config/m68k/linux.h (DBX_CONTIN_LENGTH): Likewise.
* config/m68k/openbsd.h (DBX_DEBUGGING_INFO): Likewise.
(DBX_CONTIN_LENGTH): Likewise.
(DBX_CONTIN_CHAR): Likewise.
* config/mips/mips.cc (mips_output_filename): Likewise.
(mips_option_override): Likewise.
* config/mips/mips.h (SUBTARGET_ASM_DEBUGGING_SPEC): Likewise.
(DBX_DEBUGGING_INFO): Likewise.
(DBX_CONTIN_LENGTH): Likewise.
(DBX_REGISTER_NUMBER): Likewise.
(GP_DBX_FIRST): Likewise.
(FP_DBX_FIRST): Likewise.
(MD_DBX_FIRST): Likewise.
* config/nvptx/nvptx.cc: Likewise.
* config/openbsd.h (DBX_NO_XREFS): Likewise.
* config/pa/pa-64.h (DBX_DEBUGGING_INFO): Likewise.
* config/pa/pa.h (ASSEMBLER_DIALECT): Likewise.
(DBX_CONTIN_LENGTH): Likewise.
* config/pa/som.h (PREFERRED_DEBUGGING_TYPE): Likewise.
(DBX_USE_BINCL): Likewise.
(DBX_LINES_FUNCTION_RELATIVE): Likewise.
(DBX_OUTPUT_NULL_N_SO_AT_MAIN_SOURCE_FILE_END): Likewise.
* config/pdp11/pdp11.cc: Likewise.
* config/pdp11/pdp11.h (DBX_DEBUGGING_INFO): Likewise.
(PREFERRED_DEBUGGING_TYPE): Likewise.
(DBX_CONTIN_LENGTH): Likewise.
* config/rs6000/rs6000-builtin.cc: Likewise.
* config/rs6000/rs6000-call.cc: Likewise.
* config/rs6000/rs6000-logue.cc (defined): Likewise.
* config/rs6000/rs6000.cc (rs6000_option_override_internal): Likewise.
(HAVE_XCOFF_DWARF_EXTRAS): Likewise.
(rs6000_xcoff_declare_function_name): Likewise.
* config/rs6000/sysv4.h (DBX_DEBUGGING_INFO): Likewise.
(DBX_FUNCTION_FIRST): Likewise.
* config/rs6000/xcoff.h (XCOFF_DEBUGGING_INFO): Likewise.
* config/rx/rx.h (DBX_DEBUGGING_INFO): Likewise.
* config/sh/elf.h (DBX_LINES_FUNCTION_RELATIVE): Likewise.
(DBX_OUTPUT_NULL_N_SO_AT_MAIN_SOURCE_FILE_END): Likewise.
* config/sol2.h (NO_DBX_BNSYM_ENSYM): Likewise.
* config/sparc/freebsd.h (DBX_CONTIN_CHAR): Likewise.
* config/sparc/netbsd-elf.h (DBX_CONTIN_CHAR): Likewise.
* config/sparc/sparc.h (DBX_CONTIN_LENGTH): Likewise.
* config/vax/vax.cc (vax_file_start): Likewise.
* config/vax/vax.h (DBX_DEBUGGING_INFO): Likewise.
(DBX_CONTIN_LENGTH): Likewise.
(DBX_CONTIN_CHAR): Likewise.
(DBX_NO_XREFS): Likewise.
(DBX_STATIC_STAB_DATA_SECTION): Likewise.
* config/vx-common.h (DBX_DEBUGGING_INFO): Likewise.
(XCOFF_DEBUGGING_INFO): Likewise.
* configure: Regenerate. Likewise.
* configure.ac: Likewise.
* debug.h: Likewise.
* doc/install.texi: Likewise.
* doc/invoke.texi: Likewise.
* doc/passes.texi: Likewise.
* doc/tm.texi: Likewise.
* doc/tm.texi.in: Likewise.
* dwarf2asm.cc (XCOFF_DEBUGGING_INFO): Likewise.
(dw2_asm_output_nstring): Likewise.
(USE_LINKONCE_INDIRECT): Likewise.
* dwarf2out.cc (XCOFF_DEBUGGING_INFO): Likewise.
(HAVE_XCOFF_DWARF_EXTRAS): Likewise.
(output_fde): Likewise.
(output_call_frame_info): Likewise.
(have_macinfo): Likewise.
(add_AT_loc_list): Likewise.
(add_AT_view_list): Likewise.
(output_compilation_unit_header): Likewise.
(output_pubnames): Likewise.
(output_aranges): Likewise.
(output_line_info): Likewise.
(output_macinfo): Likewise.
(dwarf2out_finish): Likewise.
(dwarf2out_early_finish): Likewise.
* final.cc (final_scan_insn_1): Likewise.
(rest_of_handle_final): Likewise.
* flag-types.h (enum debug_info_type): Likewise.
(DBX_DEBUG): Likewise.
(XCOFF_DEBUG): Likewise.
* function.cc (defined): Likewise.
* gcc.cc (defined): Likewise.
(ASM_DEBUG_SPEC): Likewise.
(ASM_DEBUG_OPTION_SPEC): Likewise.
* opts.cc (common_handle_option): Likewise.
(set_debug_level): Likewise.
* system.h (fancy_abort): Likewise.
* target-def.h (TARGET_ASM_CONSTRUCTOR): Likewise.
(TARGET_ASM_DESTRUCTOR): Likewise.
* toplev.cc (defined): Likewise.
* varasm.cc: Likewise.
* config/dbxcoff.h: Removed.
* config/dbxelf.h: Removed.
* dbxout.cc: Removed.
* dbxout.h: Removed.
* gstab.h: Removed.
* stab.def: Removed.
* xcoffout.cc: Removed.
* xcoffout.h: Removed.
gcc/go/ChangeLog:
* go-lang.cc (go_langhook_pushdecl): Remove -gstabs option support, DBX-related
macros and DBX debugging info support.
* gospec.cc (lang_specific_driver): Likewise.
gcc/testsuite/ChangeLog:
* lib/gcc-dg.exp: Remove -gstabs option support, DBX-related
macros and DBX debugging info support.
* lib/gfortran-dg.exp: Likewise.
* lib/target-supports.exp: Likewise.
* g++.dg/cpp0x/alias-decl-debug-0.C: Removed.
* g++.dg/other/PR23205.C: Removed.
* g++.dg/other/pr23205-2.C: Removed.
* gcc.dg/20040813-1.c: Removed.
* gcc.dg/darwin-20040809-2.c: Removed.
* gcc.dg/debug/pr35154.c: Removed.
* gcc.dg/pr69471-2.c: Removed.
* gcc.target/powerpc/stabs-attrib-vect-darwin.c: Removed.
* gcc.target/s390/20041216-1.c: Removed.
* gfortran.dg/debug/pr35154-stabs.f: Removed.
* objc.dg/stabs-1.m: Removed.
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Any multi-versioned function was implicitly declared as noexcept, which
leads to an abort if an exception is thrown inside the function.
The reason for this is that the function declaration is replaced by a
newly created dispatcher declaration, which has TREE_NOTHROW always set
to 1. Instead we need to set TREE_NOTHROW to the value of the original
declaration.
PR ipa/106627
gcc/ChangeLog:
* config/i386/i386-features.cc (ix86_get_function_versions_dispatcher):
Set TREE_NOTHROW correctly for dispatcher declaration.
* config/rs6000/rs6000.cc (rs6000_get_function_versions_dispatcher):
Likewise.
gcc/testsuite/ChangeLog:
* g++.target/i386/pr106627.C: New test.
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[PR106782]
This fixes the bootstrap failure on AArch64 following -Werror=format by
correcting the print format modifiers in the backend.
gcc/ChangeLog:
PR other/106782
* config/aarch64/aarch64.cc
(aarch64_vector_costs::prefer_unrolled_loop): Replace %u with
HOST_WIDE_INT_PRINT_UNSIGNED.
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The conversion of a move pattern where both operands are AX_REG
should be prevented.
2022-09-01 Uroš Bizjak <ubizjak@gmail.com>
gcc/ChangeLog:
PR target/106707
* config/i386/i386.md (moves to/from AX_REG into xchg peephole2):
Do not convert a move pattern where both operands are AX_REG.
gcc/testsuite/ChangeLog:
PR target/106707
* gcc.target/i386/pr106707.c: New test.
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When we expand an MMA disassemble built-in with C++ using a pointer that
is cast to a valid MMA type, the type isn't passed down to the expand
machinery and we end up using the base type of the pointer which leads to
an ICE. This patch enforces we always use the correct MMA type regardless
of the pointer type being used.
2022-08-31 Peter Bergner <bergner@linux.ibm.com>
gcc/
PR target/101322
* config/rs6000/rs6000-builtin.cc (rs6000_gimple_fold_mma_builtin):
Enforce the use of a valid MMA pointer type.
gcc/testsuite/
PR target/101322
* g++.target/powerpc/pr101322.C: New test.
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gcc/ChangeLog:
* config/riscv/riscv.cc (riscv_conditional_register_usage): Add vector
registers.
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gcc/ChangeLog:
* config/riscv/riscv.cc (riscv_const_insns): Add cost of poly_int.
(riscv_output_move): Add csrr vlenb assembly.
* config/riscv/riscv.md (move_type): Add csrr vlenb type.
(ext): New attribute.
(ext_enabled): Ditto.
(enabled): Ditto.
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gcc/ChangeLog:
* config/riscv/constraints.md (TARGET_VECTOR ? V_REGS : NO_REGS): Add
"vr" constraint.
(TARGET_VECTOR ? VD_REGS : NO_REGS): Add "vd" constraint.
(TARGET_VECTOR ? VM_REGS : NO_REGS): Add "vm" constraint.
(vp): Add poly constraint.
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gcc/ChangeLog:
* config/riscv/riscv.h (enum reg_class): Change vype to vtype.
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gcc/ChangeLog:
* config/riscv/riscv.cc (riscv_convert_vector_bits): Change
configuration according to TARGET_MIN_VLEN.
* config/riscv/riscv.h (UNITS_PER_FP_REG): Fix comment.
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ChangeLog:
* configure: Regenerate.
* configure.ac: Delete hpux9 and hpux10.
config/ChangeLog:
* mh-pa-hpux10: Removed.
contrib/ChangeLog:
* config-list.mk: Remove deprecated ports.
contrib/header-tools/ChangeLog:
* README: Remove deprecated ports.
* reduce-headers: Likewise.
gcc/ChangeLog:
* config.build: Remove deprecated ports.
* config.gcc: Likewise.
* config.host: Likewise.
* configure.ac: Likewise.
* configure: Regenerate.
* config/pa/pa-hpux10.h: Removed.
* config/pa/pa-hpux10.opt: Removed.
* config/pa/t-dce-thr: Removed.
gnattools/ChangeLog:
* configure.ac: Remove deprecated ports.
* configure: Regenerate.
libstdc++-v3/ChangeLog:
* configure: Regenerate.
* crossconfig.m4: Remove deprecated ports.
gcc/testsuite/ChangeLog:
* g++.dg/cpp0x/lambda/lambda-conv.C: Remove useless test.
* gcc.c-torture/execute/ieee/hugeval.x: Likewise.
* gcc.dg/torture/pr47917.c: Likewise.
* lib/target-supports.exp: Likewise.
libgcc/ChangeLog:
* config.host: Remove hppa.
libitm/ChangeLog:
* configure: Regenerate.
fixincludes/ChangeLog:
* configure: Regenerate.
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Enable and configure SIMD clones for amdgcn. This affects both the __simd__
function attribute, and the OpenMP "declare simd" directive.
Note that the masked SIMD variants are generated, but the middle end doesn't
actually support calling them yet.
gcc/ChangeLog:
* config/gcn/gcn.cc (gcn_simd_clone_compute_vecsize_and_simdlen): New.
(gcn_simd_clone_adjust): New.
(gcn_simd_clone_usable): New.
(TARGET_SIMD_CLONE_ADJUST): New.
(TARGET_SIMD_CLONE_COMPUTE_VECSIZE_AND_SIMDLEN): New.
(TARGET_SIMD_CLONE_USABLE): New.
gcc/testsuite/ChangeLog:
* gcc.dg/vect/vect-simd-clone-1.c: Add dg-warning.
* gcc.dg/vect/vect-simd-clone-2.c: Add dg-warning.
* gcc.dg/vect/vect-simd-clone-3.c: Add dg-warning.
* gcc.dg/vect/vect-simd-clone-4.c: Add dg-warning.
* gcc.dg/vect/vect-simd-clone-5.c: Add dg-warning.
* gcc.dg/vect/vect-simd-clone-8.c: Add dg-warning.
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contrib/ChangeLog:
* config-list.mk: Remove the port.
gcc/ChangeLog:
* config.gcc: Remove the port.
* config/m32c/rtems.h: Removed.
libgcc/ChangeLog:
* config.host: Remove the port.
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Fixes build on i686:
gcc/config/s390/s390.cc: In function 'bool s390_rtx_costs(rtx, machine_mode, int, int, int*, bool)':
gcc/config/s390/s390.cc:3728:63: error: cannot convert 'long int*' to 'long long int*'
gcc/ChangeLog:
* config/s390/s390.cc (s390_rtx_costs): Use proper type as
argument.
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The old method for computing a member index for a CO-RE relocation
relied on a name comparison, which could SEGV if the member in question
is itself part of an anonymous inner struct or union.
This patch changes the index computation to not rely on a name, while
maintaining the ability to account for other sibling fields which may
not have a representation in BTF.
gcc/ChangeLog:
PR target/106745
* config/bpf/coreout.cc (bpf_core_get_sou_member_index): Fix
computation of index for anonymous members.
gcc/testsuite/ChangeLog:
PR target/106745
* gcc.target/bpf/core-pr106745.c: New test.
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LLVM defines both __bpf__ and __BPF_ as target macros.
GCC was defining only __BPF__.
This patch defines __bpf__ as a target macro for BPF.
Tested in bpf-unknown-none.
gcc/ChangeLog:
* config/bpf/bpf.cc (bpf_target_macros): Define __bpf__ as a
target macro.
|
|
Handle E_V16BFmode in ix86_avx256_split_vector_move_misalign and add
V16BF to V_256H iterator.
gcc/
PR target/106748
* config/i386/i386-expand.cc
(ix86_avx256_split_vector_move_misalign): Handle E_V16BFmode.
* config/i386/sse.md (V_256H): Add V16BF.
gcc/testsuite/
PR target/106748
* gcc.target/i386/pr106748.c: New test.
|
|
The IF_THEN_ELSE detection currently prevents us from properly costing
register-register moves which causes the lower-subreg pass to assume that
a VR-VR move is as expensive as two GPR-GPR moves.
This patch adds handling for SETs containing REGs as well as MEMs and is
inspired by the aarch64 implementation.
gcc/ChangeLog:
* config/s390/s390.cc (s390_address_cost): Declare.
(s390_hard_regno_nregs): Declare.
(s390_rtx_costs): Add handling for REG and MEM in SET.
gcc/testsuite/ChangeLog:
* gcc.target/s390/vector/vec-sum-across-no-lower-subreg-1.c: New test.
|
|
This adds functions to recognize reverse/element swap permute patterns
for vler, vster as well as vpdi and rotate.
gcc/ChangeLog:
* config/s390/s390.cc (expand_perm_with_vpdi): Recognize swap pattern.
(is_reverse_perm_mask): New function.
(expand_perm_with_rot): Recognize reverse pattern.
(expand_perm_with_vstbrq): New function.
(expand_perm_with_vster): Use vler/vster for element reversal on z15.
(vectorize_vec_perm_const_1): Use.
(s390_vectorize_vec_perm_const): Add expand functions.
* config/s390/vx-builtins.md: Prefer vster over vler.
gcc/testsuite/ChangeLog:
* gcc.target/s390/vector/vperm-rev-z14.c: New test.
* gcc.target/s390/vector/vperm-rev-z15.c: New test.
* gcc.target/s390/zvector/vec-reve-store-byte.c: Adjust test
expectation.
|
|
vec_select can handle dynamic/runtime masks nowadays. Therefore we can
get rid of the UNSPEC_VEC_EXTRACT that was preventing further
optimizations like combining instructions with vec_extract patterns.
gcc/ChangeLog:
* config/s390/s390.md: Remove UNSPEC_VEC_EXTRACT.
* config/s390/vector.md: Rewrite patterns to use vec_select.
* config/s390/vx-builtins.md (vec_scatter_element<V_HW_2:mode>_SI):
Likewise.
|
|
Swapping the two elements of a V2DImode or V2DFmode vector can be done
with vpdi instead of using the generic way of loading a permutation mask
from the literal pool and vperm.
Analogous to the V2DI/V2DF case reversing the elements of a four-element
vector can be done by first swapping the elements of the first
doubleword as well the ones of the second one and subsequently rotate
the doublewords by 32 bits.
gcc/ChangeLog:
PR target/100869
* config/s390/vector.md (@vpdi4_2<mode>): New pattern.
(rotl<mode>3_di): New pattern.
* config/s390/vx-builtins.md: Use vpdi and verll for reversing
elements.
gcc/testsuite/ChangeLog:
* gcc.target/s390/zvector/vec-reve-int-long.c: New test.
|
|
Be more explicit by mentioning z15 in s390_issue_rate.
gcc/ChangeLog:
* config/s390/s390.cc (s390_issue_rate): Add z15.
|
|
Inspired by Power we also introduce -munroll-only-small-loops. This
implies activating -funroll-loops and -munroll-only-small-loops at -O2 and
above.
gcc/ChangeLog:
* common/config/s390/s390-common.cc: Enable -funroll-loops and
-munroll-only-small-loops for OPT_LEVELS_2_PLUS_SPEED_ONLY.
* config/s390/s390.cc (s390_loop_unroll_adjust): Do not unroll
loops larger than 12 instructions.
(s390_override_options_after_change): Set unroll options.
(s390_option_override_internal): Likewise.
* config/s390/s390.opt: Document munroll-only-small-loops.
gcc/testsuite/ChangeLog:
* gcc.target/s390/vector/vec-copysign.c: Do not unroll.
* gcc.target/s390/zvector/autovec-double-quiet-uneq.c: Dito.
* gcc.target/s390/zvector/autovec-double-signaling-ltgt.c: Dito.
* gcc.target/s390/zvector/autovec-float-quiet-uneq.c: Dito.
* gcc.target/s390/zvector/autovec-float-signaling-ltgt.c: Dito.
|
|
poly_int64 is non-trivial type, we need to clean up manully instead
of memset to prevent this warning.
../../gcc/gcc/config/riscv/riscv.cc: In function 'void riscv_compute_frame_info()':
../../gcc/gcc/config/riscv/riscv.cc:4113:10: error: 'void* memset(void*, int, size_t)' clearing an object of non-trivial type 'struct riscv_frame_info'; use assignment or value-initialization instead [-Werror=class-memaccess]
4113 | memset (frame, 0, sizeof (*frame));
| ~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~~~~
../../gcc/gcc/config/riscv/riscv.cc:101:17: note: 'struct riscv_frame_info' declared here
101 | struct GTY(()) riscv_frame_info {
| ^~~~~~~~~~~~~~~~
cc1plus: all warnings being treated as errors
gcc/ChangeLog:
* config/riscv/riscv.cc (riscv_frame_info): Introduce `reset(void)`;
(riscv_frame_info::reset(void)): New.
(riscv_compute_frame_info): Use riscv_frame_info::reset instead
of memset when clean frame.
|
|
gcc/ChangeLog:
* config/riscv/riscv.cc (riscv_v_ext_vector_mode_p): New function.
(riscv_classify_address): Disallow PLUS/LO_SUM/CONST_INT address types for RVV.
(riscv_address_insns): Add RVV modes condition.
(riscv_binary_cost): Ditto.
(riscv_rtx_costs): Adjust cost for RVV.
(riscv_secondary_memory_needed): Add RVV modes condition.
(riscv_hard_regno_nregs): Add RVV register allocation.
(riscv_hard_regno_mode_ok): Add RVV register allocation.
(riscv_class_max_nregs): Add RVV register allocation.
* config/riscv/riscv.h (DWARF_FRAME_REGNUM): Add VL/VTYPE and vector registers in Dwarf.
(UNITS_PER_V_REG): New macro.
(FIRST_PSEUDO_REGISTER): Adjust first pseudo num for RVV.
(V_REG_FIRST): New macro.
(V_REG_LAST): Ditto.
(V_REG_NUM): Ditto.
(V_REG_P): Ditto.
(VL_REG_P): Ditto.
(VTYPE_REG_P): Ditto.
(RISCV_DWARF_VL): Ditto.
(RISCV_DWARF_VTYPE): Ditto.
(enum reg_class): Add RVV register types.
(REG_CLASS_CONTENTS): Add RVV register types.
* config/riscv/riscv.md: Add VL/VTYPE register number constants.
|
|
gcc/ChangeLog:
* config/riscv/riscv.md: Add new type for vector instructions.
|
|
GCC incorrectly disables conversions between MMA pointer types, which
are allowed with clang. The original intent was to disable conversions
between MMA types and other other types, but pointer conversions should
have been allowed. The fix is to just remove the MMA pointer conversion
handling code altogether.
gcc/
PR target/106017
* config/rs6000/rs6000.cc (rs6000_invalid_conversion): Remove handling
of MMA pointer conversions.
gcc/testsuite/
PR target/106017
* gcc.target/powerpc/pr106017.c: New test.
|
|
Python 2 has been EOL'ed for two years. egrep has been deprecated
for many years and the next grep release will start to print warning if
it is used.
-E option may be unsupported by some non-POSIX grep implementations, but
gcc-auto-profile won't work on non-Linux systems anyway.
contrib/ChangeLog:
* gen_autofdo_event.py: Port to Python 3, and use grep -E
instead of egrep.
gcc/ChangeLog:
* config/i386/gcc-auto-profile: Regenerate.
|
|
The following patch implements a new builtin, __builtin_issignaling,
which can be used to implement the ISO/IEC TS 18661-1 issignaling
macro.
It is implemented as type-generic function, so there is just one
builtin, not many with various suffixes.
This patch doesn't address PR56831 nor PR58416, but I think compared to
using glibc issignaling macro could make some cases better (as
the builtin is expanded always inline and for SFmode/DFmode just
reinterprets a memory or pseudo register as SImode/DImode, so could
avoid some raising of exception + turning sNaN into qNaN before the
builtin can analyze it).
For floading point modes that do not have NaNs it will return 0,
otherwise I've tried to implement this for all the other supported
real formats.
It handles both the MIPS/PA floats where a sNaN has the mantissa
MSB set and the rest where a sNaN has it cleared, with the exception
of format which are known never to be in the MIPS/PA form.
The MIPS/PA floats are handled using a test like
(x & mask) == mask,
the other usually as
((x ^ bit) & mask) > val
where bit, mask and val are some constants.
IBM double double is done by doing DFmode test on the most significant
half, and Intel/Motorola extended (12 or 16 bytes) and IEEE quad are
handled by extracting 32-bit/16-bit words or 64-bit parts from the
value and testing those.
On x86, XFmode is handled by a special optab so that even pseudo numbers
are considered signaling, like in glibc and like the i386 specific testcase
tests.
2022-08-26 Jakub Jelinek <jakub@redhat.com>
gcc/
* builtins.def (BUILT_IN_ISSIGNALING): New built-in.
* builtins.cc (expand_builtin_issignaling): New function.
(expand_builtin_signbit): Don't overwrite target.
(expand_builtin): Handle BUILT_IN_ISSIGNALING.
(fold_builtin_classify): Likewise.
(fold_builtin_1): Likewise.
* optabs.def (issignaling_optab): New.
* fold-const-call.cc (fold_const_call_ss): Handle
BUILT_IN_ISSIGNALING.
* config/i386/i386.md (issignalingxf2): New expander.
* doc/extend.texi (__builtin_issignaling): Document.
(__builtin_isinf, __builtin_isnan): Clarify behavior with
-ffinite-math-only.
* doc/md.texi (issignaling<mode>2): Likewise.
gcc/c-family/
* c-common.cc (check_builtin_function_arguments): Handle
BUILT_IN_ISSIGNALING.
gcc/c/
* c-typeck.cc (convert_arguments): Handle BUILT_IN_ISSIGNALING.
gcc/fortran/
* f95-lang.cc (gfc_init_builtin_functions): Initialize
BUILT_IN_ISSIGNALING.
gcc/testsuite/
* gcc.dg/torture/builtin-issignaling-1.c: New test.
* gcc.dg/torture/builtin-issignaling-2.c: New test.
* gcc.dg/torture/float16-builtin-issignaling-1.c: New test.
* gcc.dg/torture/float32-builtin-issignaling-1.c: New test.
* gcc.dg/torture/float32x-builtin-issignaling-1.c: New test.
* gcc.dg/torture/float64-builtin-issignaling-1.c: New test.
* gcc.dg/torture/float64x-builtin-issignaling-1.c: New test.
* gcc.dg/torture/float128-builtin-issignaling-1.c: New test.
* gcc.dg/torture/float128x-builtin-issignaling-1.c: New test.
* gcc.target/i386/builtin-issignaling-1.c: New test.
|
|
contrib/ChangeLog:
* config-list.mk: Remove cr16.
gcc/ChangeLog:
* doc/extend.texi: Remove cr16 related stuff.
* doc/install.texi: Likewise.
* doc/invoke.texi: Likewise.
* doc/md.texi: Likewise.
* function-tests.cc (test_expansion_to_rtl): Likewise.
* common/config/cr16/cr16-common.cc: Removed.
* config/cr16/constraints.md: Removed.
* config/cr16/cr16-protos.h: Removed.
* config/cr16/cr16.cc: Removed.
* config/cr16/cr16.h: Removed.
* config/cr16/cr16.md: Removed.
* config/cr16/cr16.opt: Removed.
* config/cr16/predicates.md: Removed.
* config/cr16/t-cr16: Removed.
libgcc/ChangeLog:
* config.host: Remove cr16 related stuff.
* config/cr16/crti.S: Removed.
* config/cr16/crtlibid.S: Removed.
* config/cr16/crtn.S: Removed.
* config/cr16/divmodhi3.c: Removed.
* config/cr16/lib1funcs.S: Removed.
* config/cr16/t-cr16: Removed.
* config/cr16/t-crtlibid: Removed.
* config/cr16/unwind-cr16.c: Removed.
* config/cr16/unwind-dw2.h: Removed.
gcc/testsuite/ChangeLog:
* lib/target-supports.exp: Remove cr16 related stuff.
|
|
Since 256-bit vector integer comparison is under TARGET_AVX2,
and gimple folding for vblendvpd/vblendvps/vpblendvb relies on that.
Restrict gimple fold condition to TARGET_AVX2.
gcc/ChangeLog:
PR target/106704
* config/i386/i386-builtin.def (BDESC): Add
CODE_FOR_avx_blendvpd256/CODE_FOR_avx_blendvps256 to
corresponding builtins.
* config/i386/i386.cc (ix86_gimple_fold_builtin):
Don't fold IX86_BUILTIN_PBLENDVB256, IX86_BUILTIN_BLENDVPS256,
IX86_BUILTIN_BLENDVPD256 w/o TARGET_AVX2.
gcc/testsuite/ChangeLog:
* gcc.target/i386/pr106704.c: New test.
|
|
This avoids generating illegal (strict_low_part (reg ...)) RTXs. This
required two changes:
1. Do not use gen_lowpart to generate the inner expression of a
STRICT_LOW_PART. gen_lowpart might fold the SUBREG either because
there is already a paradoxical subreg or because it can directly be
applied to the register. A new wrapper function makes sure that we
always end up having an actual SUBREG.
2. Change the movstrict patterns to enforce a SUBREG as inner operand
of the STRICT_LOW_PARTs. The new predicate introduced for the
destination operand requires a SUBREG expression with a
register_operand as inner operand. However, since reload strips away
the majority of the SUBREGs we have to accept single registers as well
once we reach reload.
Bootstrapped and regression tested on IBM zSystems 64 bit.
gcc/ChangeLog:
PR target/106101
* config/s390/predicates.md (subreg_register_operand): New
predicate.
* config/s390/s390-protos.h (s390_gen_lowpart_subreg): New
function prototype.
* config/s390/s390.cc (s390_gen_lowpart_subreg): New function.
(s390_expand_insv): Use s390_gen_lowpart_subreg instead of
gen_lowpart.
* config/s390/s390.md ("*get_tp_64", "*zero_extendhisi2_31")
("*zero_extendqisi2_31", "*zero_extendqihi2_31"): Likewise.
("movstrictqi", "movstricthi", "movstrictsi"): Use the
subreg_register_operand predicate instead of register_operand.
gcc/testsuite/ChangeLog:
PR target/106101
* gcc.c-torture/compile/pr106101.c: New test.
|
|
A linker script and/or a section attribute may locate some object
specially, so we need to handle the code model for such objects
differently than the -mcmodel setting. This happens when the Linux
kernel loads a module with per-CPU variables.
Add an attribute to override the code model for a specific variable.
gcc/ChangeLog:
* config/loongarch/loongarch-protos.h (loongarch_symbol_type):
Add SYMBOL_PCREL64 and change the description for SYMBOL_PCREL.
* config/loongarch/loongarch.cc (loongarch_attribute_table):
New attribute table.
(TARGET_ATTRIBUTE_TABLE): Define the target hook.
(loongarch_handle_model_attribute): New static function.
(loongarch_classify_symbol): Take TARGET_CMODEL_EXTREME and the
model attribute of SYMBOL_REF_DECL into account returning
SYMBOL_PCREL or SYMBOL_PCREL64.
(loongarch_use_anchors_for_symbol_p): New static function.
(TARGET_USE_ANCHORS_FOR_SYMBOL_P): Define the target hook.
(loongarch_symbol_extreme_p): New static function.
(loongarch_symbolic_constant_p): Handle SYMBOL_PCREL64.
(loongarch_symbol_insns): Likewise.
(loongarch_split_symbol_type): Likewise.
(loongarch_split_symbol): Check SYMBOL_PCREL64 instead of
TARGET_CMODEL_EXTREME for PC-relative addressing.
(loongarch_print_operand_reloc): Likewise.
* doc/extend.texi (Variable Attributes): Document new
LoongArch specific attribute.
gcc/testsuite/ChangeLog:
* gcc.target/loongarch/attr-model-test.c: New test.
* gcc.target/loongarch/attr-model-1.c: New test.
* gcc.target/loongarch/attr-model-2.c: New test.
* gcc.target/loongarch/attr-model-diag.c: New test.
|
|
SYMBOL_REF_TLS_MODEL invokes SYMBOL_REF_FLAGS, and SYMBOL_REF_FLAGS
invokes RTL_FLAG_CHECK1 and aborts when RTL code is not SYMBOL_REF.
r13-1833 removed "gcc_assert (SYMBOL_REF_P (x))" before invoking
"SYMBOL_REF_TLS_MODEL (x)", indicating that it's now possible that "x"
is not a SYMBOL_REF. So we need to check if "x" is SYMBOL_REF first.
This fixes a test failure happening with r13-2173 with RTL flag
checking enabled:
pr106096.C:26:1: internal compiler error: RTL flag check:
SYMBOL_REF_FLAGS used with unexpected rtx code 'const' in
loongarch_classify_symbol
gcc/ChangeLog:
* config/loongarch/loongarch.cc (loongarch_classify_symbol):
Return early if the rtx is not SYMBOL_REF.
|
|
gcc/ChangeLog:
PR target/106459
* config/loongarch/loongarch.cc (loongarch_build_integer):
Use HOST_WIDE_INT.
* config/loongarch/loongarch.h (IMM_REACH): Likewise.
(HWIT_1U): New Defined.
(LU12I_OPERAND): Use HOST_WIDE_INT.
(LU32I_OPERAND): Likewise.
(LU52I_OPERAND): Likewise.
(HWIT_UC_0xFFF): Likwise.
gcc/testsuite/ChangeLog:
* gcc.target/loongarch/pr106459.c: New test.
|
|
The constraints should be n instead of i. Also there
needs to a check for out of bounds zero_extract for
*bexti.
gcc/ChangeLog:
PR target/106632
PR target/106588
* config/riscv/bitmanip.md (*shNadduw): Use n constraint
instead of i.
(*slliuw): Likewise.
(*bexti): Likewise. Also add a check for operands[2] to be less
than the mode bitsize.
|
|
Like a previous patch, just add constraints for predicates
not_single_bit_mask_operand and single_bit_mask_operand.
OK? Built and tested for riscv32-linux-gnu and riscv64-linux-gnu.
Thanks,
Andrew Pinski
gcc/ChangeLog:
* config/riscv/constraints.md (DbS): New constraint.
(DnS): New constraint.
* config/riscv/bitmanip.md (*bset<mode>_1_mask): Use new constraint.
(*bclr<mode>): Likewise.
(*binvi<mode>): Likewise.
|
|
The problem here is two fold. With RISCV32, 32bit
const_int are always signed extended to 64bit in HWI.
So that means for SINGLE_BIT_MASK_OPERAND, it should
mask off the upper bits to see it is a single bit
for !TARGET_64BIT.
Plus there are a few locations which forget to call
trunc_int_for_mode when generating a SImode constant
so they are not sign extended correctly for HWI.
The predicates single_bit_mask_operand and
not_single_bit_mask_operand need get the same handling
as SINGLE_BIT_MASK_OPERAND so just use SINGLE_BIT_MASK_OPERAND.
OK? Built and tested on riscv32-linux-gnu and riscv64-linux-gnu with
--with-arch=rvNimafdc_zba_zbb_zbc_zbs where N is replaced with 32 or 64.
Thanks,
Andrew Pinski
gcc/ChangeLog:
PR target/106586
* config/riscv/predicates.md (single_bit_mask_operand):
Use SINGLE_BIT_MASK_OPERAND instead of directly calling pow2p_hwi.
(not_single_bit_mask_operand): Likewise.
* config/riscv/riscv.cc (riscv_build_integer_1): Don't special case
1<<31 for 32bits as it is already handled.
Call trunc_int_for_mode on the upper part after the subtraction.
(riscv_move_integer): Call trunc_int_for_mode before generating
the integer just make sure the constant has been sign extended
corectly.
(riscv_emit_int_compare): Call trunc_int_for_mode after doing the
addition for the new rhs.
* config/riscv/riscv.h (SINGLE_BIT_MASK_OPERAND): If !TARGET64BIT,
then mask off the upper 32bits of the HWI as it will be sign extended.
|
|
A constraint here just makes it easier to understand what the
operands are.
OK? Built and tested on riscv32-linux-gnu and riscv64-linux-gnu with
--with-arch=rvNimafdc_zba_zbb_zbc_zbs (where N is 32 and 64).
Thanks,
Andrew Pinski
gcc/ChangeLog:
* config/riscv/constraints.md (DsS): New constraint.
(DsD): New constraint.
* config/riscv/iterators.md (shiftm1c): New iterator.
* config/riscv/bitmanip.md (*bset<mode>_mask):
Use shiftm1c.
(*bset<mode>_1_mask): Likewise.
|
|
for shNadd patterns
This simplifies the code by adding a predicate and a constraint for 1/2/3.
The aarch64 backend has a similar predicate called aarch64_shift_imm_<mode>
which they use there.
OK? Built and tested on riscv32-linux-gnu and riscv64-linux-gnu with no regressions.
Thanks,
Andrew Pinski
gcc/ChangeLog:
* config/riscv/constraints.md (Ds3): New constraint.
* config/riscv/predicates.md (imm123_operand): New predicate.
* config/riscv/bitmanip.md (*shNadd): Use Ds3 and imm123_operand.
(*shNadduw): Likewise.
|
|
To make things easier and more maintainable, we need to
add support printing out w if TARGET_64BIT so this patch
adds %~ to do that, similar how the x86 backend uses %~
to print out i/f for TARGET_AVX2. We could have chosen any
punctuation symbol but ~ looks the closest to w.
OK? Build and tested for riscv64-linux-gnu and riscv32-linux-gnu with no regressions.
Thanks,
Andrew Pinski
gcc/ChangeLog:
* config/riscv/riscv.cc (riscv_print_operand):
Handle '~'.
(riscv_print_operand_punct_valid_p): New function
(TARGET_PRINT_OPERAND_PUNCT_VALID_P): Define.
* config/riscv/bitmanip.md (<bitmanip_optab>si2/clz_ctz_pcnt):
Use %~ instead of conditional the pattern on TARGET_64BIT.
(rotrsi3): Likewise.
(rotlsi3): Likewise.
* config/riscv/riscv.md: Add ~ to the list of modifiers.
(addsi3): Use %~ instead of conditional the pattern on TARGET_64BIT.
(subsi3): Likewise.
(negsi2): Likewise.
(mulsi3): Likewise.
(optab>si3/any_div): Likewise.
(*add<mode>hi3): Likewise.
(<optab>si3/any_shift): Likewise.
|
|
To make it easier to find operands modifiers while in the md
file, add the list of modifiers to the top of the md file.
This is similar to i386 target.
OK? Built and tested for riscv32-linux-gnu and riscv64-linux-gnu.
gcc/ChangeLog:
* config/riscv/riscv.cc (riscv_print_operand): Make a mention to
keep the list in riscv.md in sync with this list.
* config/riscv/riscv.md: Add list of modifiers as comments.
|
|
Like the previous two patches this moves the iterators
that are in sync.md to iterators.md.
OK? build and tested for riscv64-linux-gnu.
gcc/ChangeLog:
* config/riscv/sync.md (any_atomic, atomic_optab): Move to ...
* config/riscv/iterators.md: Here.
|
|
Just like the previous patch this move all of the iterators
of bitmanip.md to iterators.md. All modern backends put the
iterators in iterators.md for easier access.
OK? Built and tested for riscv32-linux-gnu with --with-arch=rv32imafdc_zba_zbb_zbc_zbs.
Thanks,
Andrew Pinski
gcc/ChangeLog:
* config/riscv/bitmanip.md
(bitmanip_bitwise, bitmanip_minmax, clz_ctz_pcna,
tbitmanip_optab, bitmanip_insn, shiftm1): Move to ...
* config/riscv/iterators.md: Here.
|
