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| author | zhongjuzhe <juzhe.zhong@rivai.ai> | 2022-08-30 14:27:52 +0800 |
|---|---|---|
| committer | Kito Cheng <kito.cheng@sifive.com> | 2022-09-01 10:01:54 +0800 |
| commit | e8c83ab9d5142a305bbd75c7ff0e41eae38433df (patch) | |
| tree | 691a0eb211372248a618fe4f27577003c58b80fd /gcc/config | |
| parent | 8fe75147a948ceab6fb9afbe0ee698517ce1dda0 (diff) | |
| download | gcc-e8c83ab9d5142a305bbd75c7ff0e41eae38433df.zip gcc-e8c83ab9d5142a305bbd75c7ff0e41eae38433df.tar.gz gcc-e8c83ab9d5142a305bbd75c7ff0e41eae38433df.tar.bz2 | |
RISC-V: Add vector registers in TARGET_CONDITIONAL_REGISTER_USAGE
gcc/ChangeLog:
* config/riscv/riscv.cc (riscv_conditional_register_usage): Add vector
registers.
Diffstat (limited to 'gcc/config')
| -rw-r--r-- | gcc/config/riscv/riscv.cc | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index 30cbf00..675d92c 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -5438,6 +5438,15 @@ riscv_conditional_register_usage (void) for (int regno = FP_REG_FIRST; regno <= FP_REG_LAST; regno++) call_used_regs[regno] = 1; } + + if (!TARGET_VECTOR) + { + for (int regno = V_REG_FIRST; regno <= V_REG_LAST; regno++) + fixed_regs[regno] = call_used_regs[regno] = 1; + + fixed_regs[VTYPE_REGNUM] = call_used_regs[VTYPE_REGNUM] = 1; + fixed_regs[VL_REGNUM] = call_used_regs[VL_REGNUM] = 1; + } } /* Return a register priority for hard reg REGNO. */ |