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| author | liuhongt <hongtao.liu@intel.com> | 2022-08-22 10:41:16 +0800 |
|---|---|---|
| committer | liuhongt <hongtao.liu@intel.com> | 2022-08-26 09:20:59 +0800 |
| commit | 388f1a8cf0851854cc4d2ee99ed85600f0822afc (patch) | |
| tree | 9f0ae83b78b97a107efaa81f5417e8e28c5f3d24 /gcc/config | |
| parent | 5d4389dc913269cc6a6fd6ee38abc78b1fb7dbe8 (diff) | |
| download | gcc-388f1a8cf0851854cc4d2ee99ed85600f0822afc.zip gcc-388f1a8cf0851854cc4d2ee99ed85600f0822afc.tar.gz gcc-388f1a8cf0851854cc4d2ee99ed85600f0822afc.tar.bz2 | |
Don't gimple fold ymm-version vblendvpd/vblendvps/vpblendvb w/o TARGET_AVX2
Since 256-bit vector integer comparison is under TARGET_AVX2,
and gimple folding for vblendvpd/vblendvps/vpblendvb relies on that.
Restrict gimple fold condition to TARGET_AVX2.
gcc/ChangeLog:
PR target/106704
* config/i386/i386-builtin.def (BDESC): Add
CODE_FOR_avx_blendvpd256/CODE_FOR_avx_blendvps256 to
corresponding builtins.
* config/i386/i386.cc (ix86_gimple_fold_builtin):
Don't fold IX86_BUILTIN_PBLENDVB256, IX86_BUILTIN_BLENDVPS256,
IX86_BUILTIN_BLENDVPD256 w/o TARGET_AVX2.
gcc/testsuite/ChangeLog:
* gcc.target/i386/pr106704.c: New test.
Diffstat (limited to 'gcc/config')
| -rw-r--r-- | gcc/config/i386/i386-builtin.def | 4 | ||||
| -rw-r--r-- | gcc/config/i386/i386.cc | 12 |
2 files changed, 11 insertions, 5 deletions
diff --git a/gcc/config/i386/i386-builtin.def b/gcc/config/i386/i386-builtin.def index acb7e8c..f9c7abd 100644 --- a/gcc/config/i386/i386-builtin.def +++ b/gcc/config/i386/i386-builtin.def @@ -1036,8 +1036,8 @@ BDESC (OPTION_MASK_ISA_AVX, 0, CODE_FOR_avx_vpermilvarv8sf3, "__builtin_ia32_vpe BDESC (OPTION_MASK_ISA_AVX, 0, CODE_FOR_avx_blendpd256, "__builtin_ia32_blendpd256", IX86_BUILTIN_BLENDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT) BDESC (OPTION_MASK_ISA_AVX, 0, CODE_FOR_avx_blendps256, "__builtin_ia32_blendps256", IX86_BUILTIN_BLENDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT) -BDESC (OPTION_MASK_ISA_AVX, 0, CODE_FOR_nothing, "__builtin_ia32_blendvpd256", IX86_BUILTIN_BLENDVPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF) -BDESC (OPTION_MASK_ISA_AVX, 0, CODE_FOR_nothing, "__builtin_ia32_blendvps256", IX86_BUILTIN_BLENDVPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF) +BDESC (OPTION_MASK_ISA_AVX, 0, CODE_FOR_avx_blendvpd256, "__builtin_ia32_blendvpd256", IX86_BUILTIN_BLENDVPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF) +BDESC (OPTION_MASK_ISA_AVX, 0, CODE_FOR_avx_blendvps256, "__builtin_ia32_blendvps256", IX86_BUILTIN_BLENDVPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF) BDESC (OPTION_MASK_ISA_AVX, 0, CODE_FOR_avx_dpps256, "__builtin_ia32_dpps256", IX86_BUILTIN_DPPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT) BDESC (OPTION_MASK_ISA_AVX, 0, CODE_FOR_avx_shufpd256, "__builtin_ia32_shufpd256", IX86_BUILTIN_SHUFPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT) BDESC (OPTION_MASK_ISA_AVX, 0, CODE_FOR_avx_shufps256, "__builtin_ia32_shufps256", IX86_BUILTIN_SHUFPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT) diff --git a/gcc/config/i386/i386.cc b/gcc/config/i386/i386.cc index e27c87f..c4d0e36 100644 --- a/gcc/config/i386/i386.cc +++ b/gcc/config/i386/i386.cc @@ -18452,6 +18452,15 @@ ix86_gimple_fold_builtin (gimple_stmt_iterator *gsi) } break; + case IX86_BUILTIN_PBLENDVB256: + case IX86_BUILTIN_BLENDVPS256: + case IX86_BUILTIN_BLENDVPD256: + /* pcmpeqb/d/q is under avx2, w/o avx2, it's veclower + to scalar operations and not combined back. */ + if (!TARGET_AVX2) + break; + + /* FALLTHRU. */ case IX86_BUILTIN_BLENDVPD: /* blendvpd is under sse4.1 but pcmpgtq is under sse4.2, w/o sse4.2, it's veclowered to scalar operations and @@ -18460,10 +18469,7 @@ ix86_gimple_fold_builtin (gimple_stmt_iterator *gsi) break; /* FALLTHRU. */ case IX86_BUILTIN_PBLENDVB128: - case IX86_BUILTIN_PBLENDVB256: case IX86_BUILTIN_BLENDVPS: - case IX86_BUILTIN_BLENDVPS256: - case IX86_BUILTIN_BLENDVPD256: gcc_assert (n_args == 3); arg0 = gimple_call_arg (stmt, 0); arg1 = gimple_call_arg (stmt, 1); |