riscv-gnu-toolchain/gcc.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2023-08-28	Use vmaskmov{ps,pd} for VI48_128_256 when TARGET_AVX2 is not available.	liuhongt	1	-18/+30
2023-08-28	RISC-V: Refactor Phase 3 (Demand fusion) of VSETVL PASS	Juzhe-Zhong	2	-1022/+620
2023-08-26	RISC-V: Support LEN_FOLD_EXTRACT_LAST auto-vectorization	Juzhe-Zhong	4	-6/+147
2023-08-25	RISC-V: Add Types to Un-Typed Sync Instructions:	Edwin Lu	3	-11/+17
2023-08-25	[PATCH v10] RISC-V: Add support for the Zfa extension	Jin Ma	7	-36/+347
2023-08-25	RISC-V: Enable Hoist to GCSE simple constants	Vineet Gupta	1	-9/+9
2023-08-25	RISC-V: Add early continue for ENTRY and EXIT block	Juzhe-Zhong	1	-0/+2
2023-08-25	Refactor mode iterator V_128 and V_128H, V_256 and V_256H	liuhongt	1	-58/+7
2023-08-25	Fix avx512ne2ps2bf16 wrong code [PR 111127]	Hongyu Wang	1	-2/+2
2023-08-24	i386: Optimize pinsrq of 0 with index 1 into movq [PR94866]	Uros Bizjak	1	-0/+12
2023-08-24	RISC-V: Add COND_LEN_FNMA/COND_LEN_FMS/COND_LEN_FNMS testcases	Juzhe-Zhong	1	-21/+0
2023-08-24	RISC-V: Enable pressure-aware scheduling by default.	Robin Dapp	1	-0/+5
2023-08-24	RISC-V: Allow const 17-31 for vector shift.	Robin Dapp	1	-1/+2
2023-08-24	aarch64: Account for different Advanced SIMD fusing options	Richard Sandiford	1	-6/+18
2023-08-24	RISC-V: Fix one typo in autovec.md pattern comment	Pan Li	1	-3/+3
2023-08-24	RISC-V: Refactor RVV class by frm_op_type template arg	Pan Li	1	-428/+143
2023-08-24	Revert "Initial support for AVX10.1"	Haochen Jiang	8	-76/+9
2023-08-24	Revert "Emit a warning when disabling AVX512 with AVX10 enabled or disabling ...	Haochen Jiang	1	-1/+1
2023-08-24	Revert "Emit a warning when AVX10 options conflict in vector width"	Haochen Jiang	1	-2/+1
2023-08-24	Revert "Support AVX10.1 for AVX512DQ+AVX512VL intrins"	Haochen Jiang	7	-109/+77
2023-08-24	Revert "[Patch 3/6] Support AVX10.1 for AVX512DQ+AVX512VL intrins"	Haochen Jiang	4	-109/+89
2023-08-24	Revert "[Patch 5/6] Support AVX10.1 for AVX512DQ+AVX512VL intrins"	Haochen Jiang	4	-76/+65
2023-08-24	Revert "i386: Add AVX2 pragma wrapper for AVX512DQVL intrins"	Haochen Jiang	1	-11/+0
2023-08-24	Adjust GCC V13 to GCC 13.1 in diagnotic.	liuhongt	1	-1/+1
2023-08-24	Fix target_clone ("arch=graniterapids-d") and target_clone ("arch=arrowlake-s")	liuhongt	4	-33/+55
2023-08-23	rtl: use rtx_code for gen_ccmp_first and gen_ccmp_next	Richard Earnshaw	1	-2/+3
2023-08-23	i386: Fix register spill failure with concat RTX [PR111010]	Uros Bizjak	1	-32/+14
2023-08-23	[PATCH] RISC-V:add a more appropriate type attribute	Zhangjin Liao	1	-1/+1
2023-08-23	RISC-V: Add conditional unary neg/abs/not autovec patterns	Lehua Ding	4	-13/+186
2023-08-23	RISC-V: Fix potential ICE of global vsetvl elimination	Juzhe-Zhong	1	-2/+5
2023-08-23	RISC-V: Fix VTYPE fuse rule bug	Juzhe-Zhong	2	-3/+9
2023-08-23	RISC-V: Add attribute to vtype change only vsetvl	Juzhe-Zhong	1	-1/+5
2023-08-23	RISC-V: Clang format riscv-vsetvl.cc[NFC]	Juzhe-Zhong	1	-36/+29
2023-08-23	RISC-V: Add riscv-vsetvl.def to t-riscv	Juzhe-Zhong	1	-1/+2
2023-08-22	RISC-V: output Autovec params explicitly in --help ...	Vineet Gupta	1	-2/+2
2023-08-22	RISC-V: Add multiarch support on riscv-linux-gnu	Raphael Moreira Zinsly	1	-0/+2
2023-08-22	RISC-V: Support RVV VFWREDUSUM.VS rounding mode intrinsic API	Pan Li	3	-0/+4
2023-08-21	bpf: neg instruction does not accept an immediate	David Faust	1	-2/+2
2023-08-21	[PATCH] RISC-V: Add Types to Missing Bitmanip Instructions	Edwin Lu	1	-8/+18
2023-08-21	[RISCV][committed] Remove spurious newline in ztso sequence	Jeff Law	1	-2/+2
2023-08-21	aarch64: fix format specifier	Francois-Xavier Coudert	1	-1/+1
2023-08-20	i386: Micro-optimize ix86_expand_sse_extend	Uros Bizjak	2	-7/+4
2023-08-19	Loongarch: Fix plugin header missing install.	Guo Jie	1	-0/+4
2023-08-18	i386: Use PUNPCKL?? to implement vector extend and zero_extend for TARGET_SSE2.	Uros Bizjak	4	-8/+85
2023-08-18	bpf: bump maximum frame size limit to 32767 bytes	Jose E. Marchesi	1	-1/+1
2023-08-18	i386: Add AVX2 pragma wrapper for AVX512DQVL intrins	Haochen Jiang	1	-0/+11
2023-08-18	RISC-V: Add the missed half floating-point mode patterns of local_pic_load/st...	Lehua Ding	2	-17/+22
2023-08-18	RISC-V: Revert the convert from vmv.s.x to vmv.v.i	Lehua Ding	2	-12/+35
2023-08-18	RISC-V: Forbidden fuse vlmax vsetvl to DEMAND_NONZERO_AVL vsetvl	Lehua Ding	1	-0/+17
2023-08-17	bpf: support `naked' function attributes in BPF targets	Jose E. Marchesi	1	-0/+25