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| author | Edwin Lu <ewlu@rivosinc.com> | 2023-08-25 16:35:43 -0700 |
|---|---|---|
| committer | Edwin Lu <ewlu@rivosinc.com> | 2023-08-25 16:35:43 -0700 |
| commit | df177510665c4e1045bdaadf10d837f1bdc4ea06 (patch) | |
| tree | d5c73cccf078c862d879a98949b99becb0800f2b /gcc/config | |
| parent | e1f096a3cc96c71907cfbc7b8baf67a3d863cb6d (diff) | |
| download | gcc-df177510665c4e1045bdaadf10d837f1bdc4ea06.zip gcc-df177510665c4e1045bdaadf10d837f1bdc4ea06.tar.gz gcc-df177510665c4e1045bdaadf10d837f1bdc4ea06.tar.bz2 | |
RISC-V: Add Types to Un-Typed Sync Instructions:
Updates the sync instructions to ensure that no insn is left without
a type attribute. Updates a total of 9 insns to have type "atomic"
or type "multi" based on number of assembly instructions generated
Tested for regressions using rv32/64 multilib with newlib/linux.
gcc/Changelog:
* config/riscv/sync-rvwmo.md: updated types to "multi" or
"atomic" based on number of assembly lines generated
* config/riscv/sync-ztso.md: likewise
* config/riscv/sync.md: likewise
Reviewed-by: Jeff Law <jlaw@ventanamicro.com>
Signed-off-by: Edwin Lu <ewlu@rivosinc.com>
Diffstat (limited to 'gcc/config')
| -rw-r--r-- | gcc/config/riscv/sync-rvwmo.md | 7 | ||||
| -rw-r--r-- | gcc/config/riscv/sync-ztso.md | 7 | ||||
| -rw-r--r-- | gcc/config/riscv/sync.md | 14 |
3 files changed, 17 insertions, 11 deletions
diff --git a/gcc/config/riscv/sync-rvwmo.md b/gcc/config/riscv/sync-rvwmo.md index 1fc7cf1..cb641ea 100644 --- a/gcc/config/riscv/sync-rvwmo.md +++ b/gcc/config/riscv/sync-rvwmo.md @@ -41,7 +41,8 @@ else gcc_unreachable (); } - [(set (attr "length") (const_int 4))]) + [(set_attr "type" "atomic") + (set (attr "length") (const_int 4))]) ;; Atomic memory operations. @@ -66,7 +67,7 @@ else return "l<amo>\t%0,%1"; } - [(set_attr "type" "atomic") + [(set_attr "type" "multi") (set (attr "length") (const_int 12))]) ;; Implement atomic stores with conservative fences. @@ -92,5 +93,5 @@ else return "s<amo>\t%z1,%0"; } - [(set_attr "type" "atomic") + [(set_attr "type" "multi") (set (attr "length") (const_int 12))]) diff --git a/gcc/config/riscv/sync-ztso.md b/gcc/config/riscv/sync-ztso.md index ed94471..7bb15b7 100644 --- a/gcc/config/riscv/sync-ztso.md +++ b/gcc/config/riscv/sync-ztso.md @@ -35,7 +35,8 @@ else gcc_unreachable (); } - [(set (attr "length") (const_int 4))]) + [(set_attr "type" "atomic") + (set (attr "length") (const_int 4))]) ;; Atomic memory operations. @@ -56,7 +57,7 @@ else return "l<amo>\t%0,%1"; } - [(set_attr "type" "atomic") + [(set_attr "type" "multi") (set (attr "length") (const_int 12))]) (define_insn "atomic_store_ztso<mode>" @@ -76,5 +77,5 @@ else return "s<amo>\t%z1,%0"; } - [(set_attr "type" "atomic") + [(set_attr "type" "multi") (set (attr "length") (const_int 8))]) diff --git a/gcc/config/riscv/sync.md b/gcc/config/riscv/sync.md index 2f85951..6ff3493 100644 --- a/gcc/config/riscv/sync.md +++ b/gcc/config/riscv/sync.md @@ -136,7 +136,8 @@ "sc.w%J3\t%6, %7, %1\;" "bnez\t%6, 1b"; } - [(set (attr "length") (const_int 28))]) + [(set_attr "type" "multi") + (set (attr "length") (const_int 28))]) (define_expand "atomic_fetch_nand<mode>" [(match_operand:SHORT 0 "register_operand") ;; old value at mem @@ -203,7 +204,8 @@ "sc.w%J3\t%6, %7, %1\;" "bnez\t%6, 1b"; } - [(set (attr "length") (const_int 32))]) + [(set_attr "type" "multi") + (set (attr "length") (const_int 32))]) (define_expand "atomic_fetch_<atomic_optab><mode>" [(match_operand:SHORT 0 "register_operand") ;; old value at mem @@ -310,7 +312,8 @@ "sc.w%J3\t%5, %5, %1\;" "bnez\t%5, 1b"; } - [(set (attr "length") (const_int 20))]) + [(set_attr "type" "multi") + (set (attr "length") (const_int 20))]) (define_insn "atomic_cas_value_strong<mode>" [(set (match_operand:GPR 0 "register_operand" "=&r") @@ -336,7 +339,7 @@ "bnez\t%6,1b\;" "1:"; } - [(set_attr "type" "atomic") + [(set_attr "type" "multi") (set (attr "length") (const_int 16))]) (define_expand "atomic_compare_and_swap<mode>" @@ -497,7 +500,8 @@ "bnez\t%7, 1b\;" "1:"; } - [(set (attr "length") (const_int 28))]) + [(set_attr "type" "multi") + (set (attr "length") (const_int 28))]) (define_expand "atomic_test_and_set" [(match_operand:QI 0 "register_operand" "") ;; bool output |