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2017-10-08* i386.c (has_dispatch): Disable for Ryzen.Jan Hubicka1-1/+2
From-SVN: r253523
2017-10-08arm.c (arm_set_return_address): Use MEM_VOLATILE_P on the target mem instead ↵Olivier Hainque1-12/+13
of RTX_FRAME_RELATED_P on the insn... 2017-10-08 Olivier Hainque <hainque@adacore.com> * config/arm/arm.c (arm_set_return_address): Use MEM_VOLATILE_P on the target mem instead of RTX_FRAME_RELATED_P on the insn to prevent DSE. (thumb_set_return_address): Likewise. From-SVN: r253522
2017-10-08aarch64.md (*aarch64_reg_<optab>_minus<mode>3): New pattern.Michael Collison1-0/+29
2017-10-07 Michael Collison <michael.collison@arm.com> * config/aarch64/aarch64.md (*aarch64_reg_<optab>_minus<mode>3): New pattern. 2017-10-07 Michael Collison <michael.collison@arm.com> * gcc.target/aarch64/var_shift_mask_2.c: New test. From-SVN: r253520
2017-10-06Committed on behalf of Sudi DasSudakshina Das1-4/+6
2017-10-06 Sudakshina Das <sudi.das@arm.com> PR target/82440 * config/aarch64/predicates.md (aarch64_reg_or_orr_imm): Only call aarch64_simd_valid_immediate on CONST_VECTORs. (aarch64_reg_or_bic_imm): Likewise. *** gcc/testsuite/ChangeLog *** 2017-10-06 Sudakshina Das <sudi.das@arm.com> * gcc.target/aarch64/bic_imm_1.c: New test. * gcc.target/aarch64/orr_imm_1.c: Likewise. From-SVN: r253490
2017-10-06PR82322: S/390: Fix vec_ceil and friendsAndreas Krebbel2-0/+7
vec_ceil and friends are expanded by vecintrin.h to __builtin_s390_vfi which is an overloaded builtin being replaced by either __builtin_s390_vfisb or __builtin_s390_vfidb depending on its argument types. The problem in this PR was that the overloaded builtin definition of __builtin_s390_vfi was missing in s390-builtins.def. gcc/ChangeLog: 2017-10-06 Andreas Krebbel <krebbel@linux.vnet.ibm.com> PR target/82322 * config/s390/s390-builtins.def (s390_vfi): Define new overloaded builtin. * config/s390/s390-builtin-types.def: Regenerate. gcc/testsuite/ChangeLog: 2017-10-06 Andreas Krebbel <krebbel@linux.vnet.ibm.com> PR target/82322 * gcc.target/s390/zvector/pr82322.c: New test. From-SVN: r253481
2017-10-06PR82317: S/390: Fix vec_min/vec_max builtins for IBM z13.Andreas Krebbel2-40/+40
With IBM z14 a hardware instruction for floating point min and max has been added while for IBM z13 we emulated min/max for vector double with compare and select. This testcase makes sure that we fall back to the emulated variant when compiling for z13. gcc/ChangeLog: 2017-10-06 Andreas Krebbel <krebbel@linux.vnet.ibm.com> PR target/82317 * config/s390/s390-builtin-types.def: Regenerate. * config/s390/s390-builtins.def (s390_vfmaxdb_4, s390_vfmindb_4): Change flag from B_VXE to B_VX. (s390_vec_min_dbl): Remove B_VXE flag. gcc/testsuite/ChangeLog: 2017-10-06 Andreas Krebbel <krebbel@linux.vnet.ibm.com> PR target/82317 * gcc.target/s390/zvector/pr82317.c: New test. From-SVN: r253480
2017-10-05rs6000: Fix an error message in sysv4.hSegher Boessenkool1-1/+1
While looking at PR82411, I got the error message error: '-msdata=-mcall' and 'eabi-linux' are incompatible which caused some head-scratching. * config/rs6000/sysv4.h (SUBTARGET_OVERRIDE_OPTIONS): Correct error message for incompatible -msdata=* and -mcall-* options. From-SVN: r253467
2017-10-05i386.c (ia32_multipass_dfa_lookahead): Default to issue rate for post-reload ↵Jan Hubicka1-38/+7
scheduling. * i386.c (ia32_multipass_dfa_lookahead): Default to issue rate for post-reload scheduling. From-SVN: r253453
2017-10-05i386.c (znver1_cost): Set branch_cost to 3 (instead of 2) to improve monte ↵Jan Hubicka1-1/+1
carlo in scimark. * i386.c (znver1_cost): Set branch_cost to 3 (instead of 2) to improve monte carlo in scimark. From-SVN: r253449
2017-10-05i386.c (ix86_size_cost, [...]): Set reassociation width to 1.Jan Hubicka3-48/+72
* i386.c (ix86_size_cost, i386_cost, i486_cost, pentium_cost, lakemont_cost, pentiumpro_cost, geode_cost, k6_cost, athlon_cost, k8_cost, amdfam10_cost, btver1_cost, btver2_cost, pentium4_cost, nocona_cost): Set reassociation width to 1. (bdver1_cost, bdver2_cost, bdver3_cost, bdver4_cost): Set reassociation width to 2 for fp operations and 1 otherwise. (znver1_cost): Set scalar reassoc width to 4 and vector to 3 and 6 for int and fp. (atom_cost): Set reassociation width to 2. (slm_cost, generic_cost): Set fp reassociation width to 2 and 1 otherwise. (intel_cost): Set fp reassociation width to 4 and 1 otherwise. (core_cost): Set fp reassociation width to 4 and vector to 2. (ix86_reassociation_width): Rewrite using cost table; special case plus/minus on Zen; honor X86_TUNE_SSE_SPLIT_REGS and TARGET_AVX128_OPTIMAL. * i386.h (processor_costs): Add reassoc_int, reassoc_fp, reassoc_vec_int, reassoc_vec_fp. (TARGET_VECTOR_PARALLEL_EXECUTION, TARGET_REASSOC_INT_TO_PARALLEL, TARGET_REASSOC_FP_TO_PARALLEL): Remove. * x86-tune.def (X86_TUNE_REASSOC_INT_TO_PARALLEL): Remove. (X86_TUNE_REASSOC_FP_TO_PARALLEL): Remove. (X86_TUNE_VECTOR_PARALLEL_EXECUTION): Remove. From-SVN: r253448
2017-10-05arm.c (arm_test_fpu_data): New.Tamar Christina1-0/+33
2017-10-05 Tamar Christina <tamar.christina@arm.com> * config/arm/arm.c (arm_test_fpu_data): New. (arm_run_selftests): Call arm_test_fpu_data. From-SVN: r253443
2017-10-04[PATCH][AArch64] Add BIC-imm and ORR-imm SIMD patternSudakshina Das5-58/+153
This patch adds the support for BIC (vector, immediate) and ORR (vector, immediate) SIMD patterns to the AArch64 backend. Committed on behalf of Sudi Das. Reviewed-by: Richard Earnshaw <Richard.Earnshaw@arm.com> Reviewed-by: James Greenhalgh <james.greenhalgh@arm.com> gcc/ * config/aarch64/aarch64-protos.h (enum simd_immediate_check): New check type for aarch64_simd_valid_immediate. (aarch64_output_simd_mov_immediate): Update prototype. (aarch64_simd_valid_immediate): Update prototype. * config/aarch64/aarch64-simd.md (orr<mode>3): modified pattern to add support for ORR-immediate. (and<mode>3): modified pattern to add support for BIC-immediate. * config/aarch64/aarch64.c (aarch64_simd_valid_immediate): Function now checks for valid immediate for BIC and ORR based on new enum argument. (aarch64_output_simd_mov_immediate): Function now used to output BIC/ORR imm as well based on new enum argument. * config/aarch64/constraints.md (Do): New vector immediate constraint. (Db) : Likewise. * config/aarch64/predicates.md (aarch64_reg_or_orr_imm): New predicate. (aarch64_reg_or_bic_imm): Likewise. gcc/testsuite/ * gcc.target/aarch64/bic_imm_1.c: New test. * gcc.target/aarch64/orr_imm_1.c: Likewise. From-SVN: r253422
2017-10-04S/390: Fix mode in vector merge pattern.Andreas Krebbel1-6/+6
vec_unpacks_hi_v4sf/vec_unpacks_lo_v4sf expand vec_mergeh and vec_mergel patterns also for z13 with V4SF modes so the patterns should better accept this. Fixed by changing the mode iterator to V_128_NOSINGLE which accepts V4SF unconditionally. gcc/ChangeLog: 2017-10-04 Andreas Krebbel <krebbel@linux.vnet.ibm.com> * config/s390/vx-builtins.md ("vec_mergeh<mode>") ("vec_mergel<mode>"): Change mode iterator to V_128_NOSINGLE. From-SVN: r253420
2017-10-03rs6000-builtin.def (BU_FLOAT128_2_HW): Define new helper macro for IEEE ↵Michael Meissner2-9/+138
float128 hardware built-in functions. [gcc] 2017-10-03 Michael Meissner <meissner@linux.vnet.ibm.com> * config/rs6000/rs6000-builtin.def (BU_FLOAT128_2_HW): Define new helper macro for IEEE float128 hardware built-in functions. (SQRTF128_ODD): Add built-in functions with the round-to-odd semantics. (TRUNCF128_ODD): Likewise. (ADDF128_ODD): Likewise. (SUBF128_ODD): Likewise. (MULF128_ODD): Likewise. (DIVF128_ODD): Likewise. (FMAF128_ODD): Likewise. * config/rs6000/rs6000.md (UNSPEC_ROUND_TO_ODD): Rename to UNSPEC_TRUNC_ROUND_TO_ODD. (UNSPEC_TRUNC_ROUND_TO_ODD): Likewise. (UNSPEC_ADD_ROUND_TO_ODD): New unspec codes for the IEEE 128-bit floating point round to odd instructions. (UNSPEC_SUB_ROUND_TO_ODD): Likewise. (UNSPEC_MUL_ROUND_TO_ODD): Likewise. (UNSPEC_DIV_ROUND_TO_ODD): Likewise. (UNSPEC_FMA_ROUND_TO_ODD): Likewise. (UNSPEC_SQRT_ROUND_TO_ODD): Likewise. (trunc<mode>sf2_hw): Change the truncate with round to odd expansion to use UNSPEC_TRUNC_ROUND_TO_ODD. (add<mode>3_odd): Add insns for IEEE 128-bit floating point round to odd hardware instructions. (sub<mode>3_odd): Likewise. (mul<mode>3_odd): Likewise. (div<mode>3_odd): Likewise. (sqrt<mode>2_odd): Likewise. (fma<mode>4_odd): Likewise. (fms<mode>4_odd): Likewise. (nfma<mode>4_odd): Likewise. (nfms<mode>4_odd): Likewise. (trunc<mode>df2_odd): Change the truncate with round to odd expansion to use UNSPEC_TRUNC_ROUND_TO_ODD. Add a generator function. * doc/extend.texi (PowerPC built-in functions): Update documentation for existing IEEE float128-bit built-in functions. Add built-in functions that generate the IEEE 128-bit floating point round to odd instructions. [gcc/testsuite] 2017-10-03 Michael Meissner <meissner@linux.vnet.ibm.com> * gcc.target/powerpc/float128-odd.c: New test. From-SVN: r253389
2017-10-02re PR target/80210 (ICE in in extract_insn, at recog.c:2311 on ppc64 for ↵Peter Bergner2-88/+57
with __builtin_pow) gcc/ PR target/80210 * config/rs6000/rs6000.c (rs6000_option_override_internal): Rewrite function to not use the have_cpu variable. Do not set cpu_index, rs6000_cpu_index or rs6000_tune_index if we end up using TARGET_DEFAULT or the default cpu. (rs6000_valid_attribute_p): Remove duplicate initializations of old_optimize and func_optimize. (rs6000_pragma_target_parse): Call rs6000_activate_target_options (). (rs6000_activate_target_options): Make global. * config/rs6000/rs6000-protos.h (rs6000_activate_target_options): Add prototype. gcc/testsuite/ PR target/80210 * gcc.target/powerpc/pr80210-2.c: New test. From-SVN: r253358
2017-10-02re PR target/41076 ([avr] pessimal code for logical OR of 8-bit fields)Georg-Johann Lay1-3/+3
PR target/41076 * confg/avr/avr.md (*iorhi3.ashift8-ext.zerox): Add "r,r,0" alternative. From-SVN: r253343
2017-10-02[AArch64] PR71307: Define union class of POINTER+FPRichard Sandiford2-0/+4
ALL_REGS doesn't function as a union class of POINTER_REGS and FP_REGS since it includes the CC register as well. REGNO_REG_CLASS (CC_REGNUM) is NO_REGS, but of course NO_REGS rightly doesn't include CC_REGNUM. Adding a union class for POINTER+FP allows the RA to use it as the preferred or alternative class of a pseudo. It also works as a union class of GENERAL+FP for modes that aren't allowed in SP. This is also needed for the SVE port, which adds predicate registers to the mix. 2017-09-15 Richard Sandiford <richard.sandiford@linaro.org> Alan Hayward <alan.hayward@arm.com> David Sherwood <david.sherwood@arm.com> gcc/ PR target/71307 * config/aarch64/aarch64.h (POINTER_AND_FP_REGS): New reg class. (REG_CLASS_NAMES, REG_CLASS_CONTENTS): Update accordingly. * config/aarch64/aarch64.c (aarch64_class_max_nregs): Handle POINTER_AND_FP_REGS. gcc/testsuite/ PR target/71307 * gcc.target/aarch64/vect_copy_lane_1.c: Remove XFAIL. Co-Authored-By: Alan Hayward <alan.hayward@arm.com> Co-Authored-By: David Sherwood <david.sherwood@arm.com> From-SVN: r253337
2017-09-30config.gcc (*-*-netbsd*): New variable nbsd_tm_file containing netbsd.h, ↵Krister Walfridsson1-0/+16
netbsd-stdint.h, and netbsd-elf.h. 2017-09-30 Krister Walfridsson <krister.walfridsson@gmail.com> Maya Rashish <coypu@sdf.org> * config.gcc (*-*-netbsd*): New variable nbsd_tm_file containing netbsd.h, netbsd-stdint.h, and netbsd-elf.h. (alpha*-*-netbsd*) Use nbsd_tm_file. (arm*-*-netbsdelf*) Likewise. (i[34567]86-*-netbsdelf*) Likewise. (x86_64-*-netbsd*) Likewise. (mips*-*-netbsd*) Likewise. (powerpc-*-netbsd*) Likewise. (sh*-*-netbsd*) Likewise. (sparc-*-netbsdelf*) Likewise. (sparc64-*-netbsd*) Likewise. (m68k*-*-netbsdelf*) Use nbsd_tm_file and add CHAR_FAST8/SHORT_FAST16 to tm_defines. (vax-*-netbsdelf*) Likewise. * config/netbsd-stdint.h (INT_FAST8_TYPE): Check CHAR_FAST8. (UINT_FAST8_TYPE) Likewise. (INT_FAST16_TYPE) Check CHAR_FAST16. (UINT_FAST16_TYPE) Likewise. Co-Authored-By: Maya Rashish <coypu@sdf.org> From-SVN: r253323
2017-09-30re PR target/82361 (Useless "mov eax, eax" in generated code)Jakub Jelinek2-4/+431
PR target/82361 * config/i386/i386.md (TARGET_USE_8BIT_IDIV zext divmodsi4 splitter): New define_split. (divmodsi4_zext_1, divmodsi4_zext_2, *divmodsi4_zext_1, *divmodsi4_zext_2): New define_insn_and_split. (*divmodsi4_noext_zext_1, *divmodsi4_noext_zext_2): New define_insn. (TARGET_USE_8BIT_IDIV zext udivmodsi4 splitter): New define_split. (udivmodsi4_zext_1, udivmodsi4_zext_2, *udivmodsi4_zext_1, *udivmodsi4_zext_2, *udivmodsi4_pow2_zext_1, *udivmodsi4_pow2_zext_2): New define_insn_and_split. (*udivmodsi4_noext_zext_1, *udivmodsi4_noext_zext_2): New define_insn. * config/i386/i386.c (ix86_split_idivmod): Handle operands[0] or operands[1] having DImode when mode is SImode. * gcc.target/i386/pr82361-1.c: New test. * gcc.target/i386/pr82361-2.c: New test. From-SVN: r253317
2017-09-30i386.c (ix86_split_idivmod): Use mode instead of always SImode for DIV and ↵Jakub Jelinek1-4/+4
MOD in REG_EQUAL notes. * config/i386/i386.c (ix86_split_idivmod): Use mode instead of always SImode for DIV and MOD in REG_EQUAL notes. From-SVN: r253316
2017-09-29i386.c (ix86_adjust_stack_and_probe_stack_clash): Fix typos and whitespace ↵Jeff Law3-5/+5
errors. * config/i386/i386.c (ix86_adjust_stack_and_probe_stack_clash): Fix typos and whitespace errors. * config/i386/predicates.md (address_no_seg_operand): Likewise. * config/s390/s390.c (s390_emit_prologue): Likewise. From-SVN: r253303
2017-09-29re PR target/82339 (Inefficient movabs instruction)Jakub Jelinek1-0/+22
PR target/82339 * config/i386/i386.md (*movdi_internal peephole2): New -Os peephole for movabsq $(i32 << shift), r64. From-SVN: r253279
2017-09-28i386.c (ix86_print_operand_address_as): Do not check index when encoding ↵Uros Bizjak1-5/+4
%esp as %rsp to avoid 0x67 prefix. * config/i386/i386.c (ix86_print_operand_address_as): Do not check index when encoding %esp as %rsp to avoid 0x67 prefix. From-SVN: r253260
2017-09-28i386.md (*movsf_internal, [...]): Return 256-bit AVX modes for ↵Sergey Shalnov1-2/+4
TARGET_PREFER_AVX256. gcc/ * config/i386/i386.md (*movsf_internal, *movdf_internal): Return 256-bit AVX modes for TARGET_PREFER_AVX256. gcc/testsuite/ * gcc.target/i386/avx512f-constant-float-return.c: New test. From-SVN: r253259
2017-09-28[ARM] Remove ARMv8-M code for D17-D31Thomas Preud'homme1-24/+40
Function cmse_nonsecure_entry_clear_before_return has code to deal with high VFP register (D16-D31) while ARMv8-M Baseline and Mainline both do not support more than 16 double VFP registers (D0-D15). This makes this security-sensitive code harder to read for not much benefit since libcall for cmse_nonsecure_call functions do not deal with those high VFP registers anyway. This commit gets rid of this code for simplicity and fixes 2 issues in the same function: - stop the first loop when reaching maxregno to avoid dealing with VFP registers if targetting Thumb-1 or using -mfloat-abi=soft - include maxregno in that loop 2017-09-28 Thomas Preud'homme <thomas.preudhomme@arm.com> gcc/ * config/arm/arm.c (arm_option_override): Forbid ARMv8-M Security Extensions with more than 16 double VFP registers. (cmse_nonsecure_entry_clear_before_return): Remove second entry of to_clear_mask and all code related to it. Replace the remaining entry by a sbitmap and adapt code accordingly. From-SVN: r253256
2017-09-28Avoid assembler warnings from AArch64 constructor/destructor priorities.Joseph Myers1-2/+2
Many GCC tests fail for AArch64 with current binutils because of assembler warnings of the form "Warning: ignoring incorrect section type for .init_array.00100". The same issue was fixed for ARM in r247015 by using SECTION_NOTYPE when creating those sections; this patch applies the same fix to AArch64. Tested with no regressions with cross to aarch64-linux-gnu. * config/aarch64/aarch64.c (aarch64_elf_asm_constructor) (aarch64_elf_asm_destructor): Pass SECTION_NOTYPE to get_section when creating .init_array and .fini_array sections with priority specified. From-SVN: r253252
2017-09-28[AArch64] PR71727 fix -mstrict-alignChristophe Lyon1-12/+2
2017-09-27 Christophe Lyon <christophe.lyon@linaro.org> PR target/71727 gcc/ * config/aarch64/aarch64.c (aarch64_builtin_support_vector_misalignment): Always return false when misalignment is unknown. gcc/testsuite/ * gcc.target/aarch64/pr71727-2.c: New test From-SVN: r253242
2017-09-27rs6000-p8swap.c (const_load_sequence_p): Revise this function to return ↵Kelvin Nilsen1-3/+267
false if the definition used by the swap... gcc/ChangeLog: 2017-09-27 Kelvin Nilsen <kelvin@gcc.gnu.org> * config/rs6000/rs6000-p8swap.c (const_load_sequence_p): Revise this function to return false if the definition used by the swap instruction is artificial, or if the memory address from which the constant value is loaded is not represented by a base address held in a register or if the base address register is a frame or stack pointer. Additionally, return false if the base address of the loaded constant is a SYMBOL_REF but is not considered to be a constant. (replace_swapped_load_constant): New function. (rs6000_analyze_swaps): Add a new pass to replace a swap of a loaded constant vector with a load of a swapped constant vector. gcc/testsuite/ChangeLog: 2017-09-27 Kelvin Nilsen <kelvin@gcc.gnu.org> * gcc.target/powerpc/swaps-p8-28.c: New test. * gcc.target/powerpc/swaps-p8-29.c: New test. * gcc.target/powerpc/swaps-p8-30.c: New test. * gcc.target/powerpc/swaps-p8-31.c: New test. * gcc.target/powerpc/swaps-p8-32.c: New test. * gcc.target/powerpc/swaps-p8-33.c: New test. * gcc.target/powerpc/swaps-p8-34.c: New test. * gcc.target/powerpc/swaps-p8-35.c: New test. * gcc.target/powerpc/swaps-p8-36.c: New test. * gcc.target/powerpc/swaps-p8-37.c: New test. * gcc.target/powerpc/swaps-p8-38.c: New test. * gcc.target/powerpc/swaps-p8-39.c: New test. * gcc.target/powerpc/swaps-p8-40.c: New test. * gcc.target/powerpc/swaps-p8-41.c: New test. * gcc.target/powerpc/swaps-p8-42.c: New test. * gcc.target/powerpc/swaps-p8-43.c: New test. * gcc.target/powerpc/swaps-p8-44.c: New test. * gcc.target/powerpc/swaps-p8-45.c: New test. From-SVN: r253240
2017-09-27rs6000-builtin.def (BU_FP_1MISC_1): Add define macro.Carl Love2-0/+22
gcc/ChangeLog: 2017-09-27 Carl Love <cel@us.ibm.com> * config/rs6000/rs6000-builtin.def (BU_FP_1MISC_1): Add define macro. (FCTID, FCTIW): Add BU_FP_MISC_1 macro expansion for builtins. * config/rs6000/rs6000.md (lrintsfsi2): Add define_insn for the fctiw instruction. gcc/testsuite/ChangeLog: 2017-09-27 Carl Love <cel@us.ibm.com> * gcc.target/powerpc/builtin-fctid-fctiw-runnable.c: New test file for the __builtin_fctid and __builtin_fctiw. From-SVN: r253238
2017-09-27vsx.md (peephole for optimizing move SF to GPR): Adjust code to eliminate ↵Michael Meissner1-21/+17
needing to do the shift right 32-bits operation after... [gcc] 2017-09-26 Michael Meissner <meissner@linux.vnet.ibm.com> * config/rs6000/vsx.md (peephole for optimizing move SF to GPR): Adjust code to eliminate needing to do the shift right 32-bits operation after XSCVDPSPN. [gcc/testsuite] 2017-09-26 Michael Meissner <meissner@linux.vnet.ibm.com> * gcc.target/powerpc/pr71977-1.c: Update test to know that we don't generate a 32-bit shift after doing XSCVDPSPN. * gcc.target/powerpc/direct-move-float1.c: Likewise. * gcc.target/powerpc/direct-move-float3.c: New test. From-SVN: r253223
2017-09-26rs6000-c.c (P9V_BUILTIN_VEC_XL_LEN_R, [...]): Add support for builtins ↵Carl Love6-4/+107
vector unsigned char vec_xl_len_r (unsigned char *... gcc/ChangeLog: 2017-09-26 Carl Love <cel@us.ibm.com> * config/rs6000/rs6000-c.c (P9V_BUILTIN_VEC_XL_LEN_R, P9V_BUILTIN_VEC_XST_LEN_R): Add support for builtins vector unsigned char vec_xl_len_r (unsigned char *, size_t); void vec_xst_len_r (vector unsigned char, unsigned char *, size_t); * config/rs6000/altivec.h (vec_xl_len_r, vec_xst_len_r): Add defines. * config/rs6000/rs6000-builtin.def (XL_LEN_R, XST_LEN_R): Add definitions and overloading. * config/rs6000/rs6000.c (altivec_expand_builtin): Add case statement for P9V_BUILTIN_XST_LEN_R. (altivec_init_builtins): Add def_builtin for P9V_BUILTIN_STXVLL. * config/rs6000/vsx.md (lxvll, stxvll, xl_len_r, xst_len_r): Add define_expand and define_insn for the instructions and builtins. * doc/extend.texi: Update the built-in documentation file for the new built-in functions. * config/rs6000/altivec.md (altivec_lvsl_reg, altivec_lvsr_reg): Add define_insn for the instructions gcc/testsuite/ChangeLog: 2017-09-26 Carl Love <cel@us.ibm.com> * gcc.target/powerpc/builtins-5-p9-runnable.c: Add new runable test file for the new built-ins and the existing built-ins. From-SVN: r253217
2017-09-26re PR target/39570 (cabs and cabsf are named differently on NetBSD 5)Krister Walfridsson4-0/+101
2017-09-26 Krister Walfridsson <krister.walfridsson@gmail.com> PR target/39570 * gcc/config/netbsd-protos.h: New file. * gcc/config/netbsd.c: New file. * gcc/config/netbsd.h (SUBTARGET_INIT_BUILTINS): Define. * gcc/config/t-netbsd: New file. * gcc/config.gcc (tm_p_file): Add netbsd-protos.h. (tmake_file) Add t-netbsd. (extra_objs) Add netbsd.o. From-SVN: r253216
2017-09-26vsx.md (vsx_xscvdpspn): Eliminate useless alternative constraint.Michael Meissner1-7/+7
2017-09-26 Michael Meissner <meissner@linux.vnet.ibm.com> * config/rs6000/vsx.md (vsx_xscvdpspn): Eliminate useless alternative constraint. (vsx_xscvspdpn): Likewise. (vsx_xscvspdpn_scalar): Likewise. From-SVN: r253213
2017-09-26vsx.md (vsx_xscvspdp_scalar2): Move insn so that it is adjacent to the other ↵Michael Meissner1-9/+9
XSCVSPDP insns. 2017-09-26 Michael Meissner <meissner@linux.vnet.ibm.com> * config/rs6000/vsx.md (vsx_xscvspdp_scalar2): Move insn so that it is adjacent to the other XSCVSPDP insns. From-SVN: r253212
2017-09-26rs6000.md (movsi_from_df): Optimize converting a DFmode to a SFmode...Michael Meissner1-0/+20
2017-09-26 Michael Meissner <meissner@linux.vnet.ibm.com> * config/rs6000/rs6000.md (movsi_from_df): Optimize converting a DFmode to a SFmode, and then needing to move the SFmode to a GPR to use the XSCVDPSP instruction instead of FRSP and XSCVDPSPN. From-SVN: r253210
2017-09-26rs6000.md (movsi_from_sf): Adjust code to eliminate doing a 32-bit shift ↵Michael Meissner1-68/+38
right or vector extract after... 2017-09-26 Michael Meissner <meissner@linux.vnet.ibm.com> * config/rs6000/rs6000.md (movsi_from_sf): Adjust code to eliminate doing a 32-bit shift right or vector extract after doing XSCVDPSPN. Use zero_extendsidi2 instead of p8_mfvsrd_4_disf to move the value to the GPRs. (movdi_from_sf_zero_ext): Likewise. (reload_gpr_from_vsxsf): Likewise. (p8_mfvsrd_4_disf): Delete, no longer used. From-SVN: r253209
2017-09-26rs6000.md (extendsi<mode>2): Add a splitter to do sign extension from a ↵Michael Meissner1-4/+20
vector register to a GPR by doing a... 2017-09-26 Michael Meissner <meissner@linux.vnet.ibm.com> * config/rs6000/rs6000.md (extendsi<mode>2): Add a splitter to do sign extension from a vector register to a GPR by doing a 32-bit direct move and then an EXTSW. (extendsi<mode>2 splitter): Likewise. From-SVN: r253208
2017-09-26Enable no-exec stacks for more targets using the Linux kernel.Joseph Myers4-10/+18
Building glibc for many different configurations and running the compilation parts of the testsuite runs into failures of the elf/check-execstack test for hppa and microblaze. Those configurations default to executable stacks in the Linux kernel because of VM_DATA_DEFAULT_FLAGS definitions including VM_EXEC (VM_DATA_DEFAULT_FLAGS being the default definition of VM_STACK_DEFAULT_FLAGS). This fails because those configurations are not generating .note.GNU-stack sections to indicate that programs do not need an executable stack. This patch fixes GCC to generate those sections on those architectures (when configured for a target using the Linux kernel), as it does on other architectures, together with adding that section to libgcc .S sources, with the same code as used on other architectures (or a variant using "#ifdef __linux__" instead of the usual "#if defined(__ELF__) && defined(__linux__)" for microblaze, as that configuration doesn't use elfos.h and so doesn't define __ELF__). This suffices to eliminate that glibc test failure. (For hppa, the compilation parts of the glibc testsuite still fail because of the separate elf/check-textrel failure.) gcc: * config/microblaze/linux.h (TARGET_ASM_FILE_END): Likewise. * config/pa/pa.h (NEED_INDICATE_EXEC_STACK): Likewise. * config/pa/pa-linux.h (NEED_INDICATE_EXEC_STACK): Likewise. * config/pa/pa.c (pa_hpux_file_end): Rename to pa_file_end. Define unconditionally, with [ASM_OUTPUT_EXTERNAL_REAL] conditionals inside the function instead of around it. Call file_end_indicate_exec_stack if NEED_INDICATE_EXEC_STACK. (TARGET_ASM_FILE_END): Define unconditionally to pa_file_end. libgcc: * config/microblaze/crti.S, config/microblaze/crtn.S, config/microblaze/divsi3.S, config/microblaze/moddi3.S, config/microblaze/modsi3.S, config/microblaze/muldi3_hard.S, config/microblaze/mulsi3.S, config/microblaze/stack_overflow_exit.S, config/microblaze/udivsi3.S, config/microblaze/umodsi3.S, config/pa/milli64.S: Add .note.GNU-stack section. From-SVN: r253204
2017-09-26re PR target/82267 (x32: unnecessary address-size prefixes. Why isn't ↵Jakub Jelinek1-1/+1
-maddress-mode=long the default?) PR target/82267 * config/i386/i386.c (ix86_print_operand_address_as): Only test REGNO (base) == SP_REG if base is a REG. From-SVN: r253202
2017-09-26S/390: Fix vmslg instruction and builtin.Andreas Krebbel2-3/+3
gcc/ChangeLog: 2017-09-26 Andreas Krebbel <krebbel@linux.vnet.ibm.com> * config/s390/vx-builtins.md ("vmslg"): Add missing operand in assembler output. * config/s390/s390-builtins.def: Fix constraint on op4. From-SVN: r253198
2017-09-26S/390: Fix vector fp unordered comparesAndreas Krebbel2-4/+68
V2DF mode was still hard-coded here. gcc/ChangeLog: 2017-09-26 Andreas Krebbel <krebbel@linux.vnet.ibm.com> * config/s390/s390.c (s390_expand_vec_compare): Use the new mode independent expanders. * config/s390/vector.md ("vec_cmpuneq", "vec_cmpltgt") ("vec_ordered", "vec_unordered"): New expanders. From-SVN: r253197
2017-09-26S/390: Set the preferred mode for float vectorsAndreas Krebbel1-0/+8
gcc/ChangeLog: 2017-09-26 Andreas Krebbel <krebbel@linux.vnet.ibm.com> * config/s390/s390.c (s390_preferred_simd_mode): Return V4SFmode for SFmode. From-SVN: r253196
2017-09-26S/390: Fix rtl standard names for vector unpack low->loAndreas Krebbel1-2/+2
gcc/ChangeLog: 2017-09-26 Andreas Krebbel <krebbel@linux.vnet.ibm.com> * config/s390/vector.md ("vec_unpacks_low_v16qi"): Rename to vec_unpacks_lo_v16qi. ("vec_unpacku_low_v16qi"): Rename to vec_unpacku_lo_v16qi. From-SVN: r253195
2017-09-26S/390: Add FP vec_pack/unpackAndreas Krebbel1-1/+95
gcc/ChangeLog: 2017-09-26 Andreas Krebbel <krebbel@linux.vnet.ibm.com> * config/s390/vector.md ("vec_unpacks_lo_v4sf") ("vec_unpacks_hi_v4sf", "vec_unpacks_lo_v2df") ("vec_unpacks_hi_v2df", "vec_pack_trunc_v2df"): New expanders. From-SVN: r253194
2017-09-26S/390: Add support for vec_shrAndreas Krebbel3-17/+52
gcc/ChangeLog: 2017-09-26 Andreas Krebbel <krebbel@linux.vnet.ibm.com> * config/s390/predicates.md ("const_shift_by_byte_operand"): New predicate. * config/s390/vector.md ("*vec_srb<mode>"): Change modes to V_128 and V16QI. ("*vec_slb<mode>"): New insn pattern. ("vec_shr_<mode>"): New expander. * config/s390/vx-builtins.md ("vec_slb<mode>"): Turn into expander and force the shift count operand to V16QImode. ("vec_srb<mode>"): Set shift count mode to V16QI. From-SVN: r253193
2017-09-26S/390: Add widening vector mult lo/hi patternsAndreas Krebbel1-4/+79
Add support for widening vector multiply lo/hi patterns. These do not directly match on IBM Z instructions but can be emulated with even/odd + vector merge. gcc/ChangeLog: 2017-09-26 Andreas Krebbel <krebbel@linux.vnet.ibm.com> * config/s390/vector.md ("vec_widen_umult_lo_<mode>") ("vec_widen_umult_hi_<mode>", "vec_widen_smult_lo_<mode>") ("vec_widen_smult_hi_<mode>"): New expander definitions. From-SVN: r253192
2017-09-26[ARM] PR82175 - fix -mcpu=native not working correctly.Richard Earnshaw1-2/+5
The new option processing machinery relies on %< rules in the specs to suppress options that are rewritten. Suppression appears to be a two phase process where the option is partially suppressed when %< is processed and then fully suppressed at the end of the string. Strings are separated by commas and there can be multiple strings used to form DRIVER_SELF_SPECS. The fix in this case is to separate the driver self specs for ARM into separate rules as described; this forces the -m{cpu,tune,arch}=native options to be properly removed before proceeding to the next rule set. PR target/82175 * config/arm/arm.h (DRIVER_SELF_SPECS): Separate sub-rules with commas. From-SVN: r253189
2017-09-25rs6000-protos.h (output_probe_stack_range): Update prototype for new argument.Jeff Law3-40/+373
* config/rs6000/rs6000-protos.h (output_probe_stack_range): Update prototype for new argument. * config/rs6000/rs6000.c (rs6000_emit_allocate_stack_1): New function, mostly extracted from rs6000_emit_allocate_stack. (rs6000_emit_probe_stack_range_stack_clash): New function. (rs6000_emit_allocate_stack): Call rs6000_emit_probe_stack_range_stack_clash as needed. (rs6000_emit_probe_stack_range): Add additional argument to call to gen_probe_stack_range{si,di}. (output_probe_stack_range): New. (output_probe_stack_range_1): Renamed from output_probe_stack_range. (output_probe_stack_range_stack_clash): New. (rs6000_emit_prologue): Emit notes into dump file as requested. * rs6000.md (allocate_stack): Handle -fstack-clash-protection. (probe_stack_range<P:mode>): Operand 0 is now early-clobbered. Add additional operand and pass it to output_probe_stack_range. * lib/target-supports.exp (check_effective_target_supports_stack_clash_protection): Enable for rs6000 and powerpc targets. From-SVN: r253179
2017-09-25Turn CONSTANT_ALIGNMENT into a hookRichard Sandiford71-259/+285
The definition: #define CONSTANT_ALIGNMENT(EXP, ALIGN) \ (TREE_CODE (EXP) == STRING_CST \ && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN)) was very common, so the patch adds a canned definition for that, called constant_alignment_word_strings. Some ports had a variation that used a port-local FASTEST_ALIGNMENT instead of BITS_PER_WORD; the patch uses constant_alignment_word_strings if FASTEST_ALIGNMENT was always BITS_PER_WORD and a port-local hook function otherwise. 2017-09-25 Richard Sandiford <richard.sandiford@linaro.org> gcc/ * target.def (constant_alignment): New hook. * defaults.h (CONSTANT_ALIGNMENT): Delete. * doc/tm.texi.in (CONSTANT_ALIGNMENT): Replace with... (TARGET_CONSTANT_ALIGNMENT): ...this new hook. * doc/tm.texi: Regenerate. * targhooks.h (default_constant_alignment): Declare. (constant_alignment_word_strings): Likewise. * targhooks.c (default_constant_alignment): New function. (constant_alignment_word_strings): Likewise. * builtins.c (get_object_alignment_2): Use targetm.constant_alignment instead of CONSTANT_ALIGNMENT. * varasm.c (align_variable, get_variable_align, build_constant_desc) (force_const_mem): Likewise. * config/aarch64/aarch64.h (CONSTANT_ALIGNMENT): Delete. * config/aarch64/aarch64.c (aarch64_constant_alignment): New function. (aarch64_classify_address): Call it instead of CONSTANT_ALIGNMENT. (TARGET_CONSTANT_ALIGNMENT): Redefine. * config/alpha/alpha.h (CONSTANT_ALIGNMENT): Delete commented-out definition. * config/arc/arc.h (CONSTANT_ALIGNMENT): Delete. * config/arc/arc.c (TARGET_CONSTANT_ALIGNMENT): Redefine to constant_alignment_word_strings. * config/arm/arm.h (CONSTANT_ALIGNMENT_FACTOR): Delete. (CONSTANT_ALIGNMENT): Likewise. * config/arm/arm.c (TARGET_CONSTANT_ALIGNMENT): Redefine. (arm_constant_alignment): New function. * config/bfin/bfin.h (CONSTANT_ALIGNMENT): Delete. * config/bfin/bfin.c (TARGET_CONSTANT_ALIGNMENT): Redefine to constant_alignment_word_strings. * config/cr16/cr16.h (CONSTANT_ALIGNMENT): Delete. * config/cr16/cr16.c (TARGET_CONSTANT_ALIGNMENT): Redefine to constant_alignment_word_strings. * config/cris/cris.h (CONSTANT_ALIGNMENT): Delete. * config/cris/cris.c (TARGET_CONSTANT_ALIGNMENT): Redefine. (cris_constant_alignment): New function. * config/epiphany/epiphany.h (CONSTANT_ALIGNMENT): Delete. * config/epiphany/epiphany.c (TARGET_CONSTANT_ALIGNMENT): Redefine. (epiphany_constant_alignment): New function. * config/fr30/fr30.h (CONSTANT_ALIGNMENT): Delete. * config/fr30/fr30.c (TARGET_CONSTANT_ALIGNMENT): Redefine to constant_alignment_word_strings. * config/frv/frv.h (CONSTANT_ALIGNMENT): Delete. * config/frv/frv.c (TARGET_CONSTANT_ALIGNMENT): Redefine to constant_alignment_word_strings. * config/ft32/ft32.h (CONSTANT_ALIGNMENT): Delete. * config/ft32/ft32.c (TARGET_CONSTANT_ALIGNMENT): Redefine to constant_alignment_word_strings. * config/i386/i386.h (CONSTANT_ALIGNMENT): Delete. * config/i386/i386-protos.h (ix86_constant_alignment): Delete. * config/i386/i386.c (ix86_constant_alignment): Make static. Use the same interface as the target hook. (TARGET_CONSTANT_ALIGNMENT): Redefine. * config/ia64/ia64.h (CONSTANT_ALIGNMENT): Delete. * config/ia64/ia64.c (TARGET_CONSTANT_ALIGNMENT): Redefine to constant_alignment_word_strings. * config/iq2000/iq2000.h (CONSTANT_ALIGNMENT): Delete. * config/iq2000/iq2000.c (iq2000_constant_alignment): New function. (TARGET_CONSTANT_ALIGNMENT): Redefine. * config/lm32/lm32.h (CONSTANT_ALIGNMENT): Delete. * config/lm32/lm32.c (TARGET_CONSTANT_ALIGNMENT): Redefine to constant_alignment_word_strings. * config/m32r/m32r.h (CONSTANT_ALIGNMENT): Delete. * config/m32r/m32r.c (TARGET_CONSTANT_ALIGNMENT): Redefine to constant_alignment_word_strings. * config/mcore/mcore.h (CONSTANT_ALIGNMENT): Delete. * config/mcore/mcore.c (TARGET_CONSTANT_ALIGNMENT): Redefine to constant_alignment_word_strings. * config/microblaze/microblaze.h (CONSTANT_ALIGNMENT): Delete. * config/microblaze/microblaze.c (microblaze_constant_alignment): New function. (TARGET_CONSTANT_ALIGNMENT): Redefine. * config/mips/mips.h (CONSTANT_ALIGNMENT): Delete. * config/mips/mips.c (mips_constant_alignment): New function. (TARGET_CONSTANT_ALIGNMENT): Redefine. * config/mmix/mmix.h (CONSTANT_ALIGNMENT): Delete. * config/mmix/mmix-protos.h (mmix_constant_alignment): Delete. * config/mmix/mmix.c (TARGET_CONSTANT_ALIGNMENT): Redefine. (mmix_constant_alignment): Make static. Use the same interface as the target hook. * config/moxie/moxie.h (CONSTANT_ALIGNMENT): Delete. * config/moxie/moxie.c (TARGET_CONSTANT_ALIGNMENT): Redefine to constant_alignment_word_strings. * config/nios2/nios2.h (CONSTANT_ALIGNMENT): Delete. * config/nios2/nios2.c (TARGET_CONSTANT_ALIGNMENT): Redefine to constant_alignment_word_strings. * config/pa/pa.h (CONSTANT_ALIGNMENT): Delete. * config/pa/pa.c (TARGET_CONSTANT_ALIGNMENT): Redefine to constant_alignment_word_strings. * config/powerpcspe/powerpcspe.h (CONSTANT_ALIGNMENT): Delete. * config/powerpcspe/powerpcspe.c (TARGET_CONSTANT_ALIGNMENT): Redefine. (rs6000_constant_alignment): New function. * config/riscv/riscv.h (CONSTANT_ALIGNMENT): Delete. * config/riscv/riscv.c (riscv_constant_alignment): New function. (TARGET_CONSTANT_ALIGNMENT): Redefine. * config/rs6000/rs6000.h (CONSTANT_ALIGNMENT): Delete. * config/rs6000/rs6000.c (TARGET_CONSTANT_ALIGNMENT): Redefine. (rs6000_constant_alignment): New function. * config/s390/s390.h (CONSTANT_ALIGNMENT): Delete. * config/s390/s390.c (s390_constant_alignment): New function. (TARGET_CONSTANT_ALIGNMENT): Redefine. * config/sh/sh.h (CONSTANT_ALIGNMENT): Delete. * config/sh/sh.c (TARGET_CONSTANT_ALIGNMENT): Redefine to constant_alignment_word_strings. * config/sparc/sparc.h (CONSTANT_ALIGNMENT): Delete. * config/sparc/sparc.c (TARGET_CONSTANT_ALIGNMENT): Redefine. (sparc_constant_alignment): New function. * config/spu/spu.h (CONSTANT_ALIGNMENT): Delete. * config/spu/spu.c (spu_constant_alignment): New function. (TARGET_CONSTANT_ALIGNMENT): Redefine. * config/stormy16/stormy16.h (CONSTANT_ALIGNMENT): Delete. * config/stormy16/stormy16.c (TARGET_CONSTANT_ALIGNMENT): Redefine to constant_alignment_word_strings. * config/tilegx/tilegx.h (CONSTANT_ALIGNMENT): Delete. * config/tilegx/tilegx.c (TARGET_CONSTANT_ALIGNMENT): Redefine to constant_alignment_word_strings. * config/tilepro/tilepro.h (CONSTANT_ALIGNMENT): Delete. * config/tilepro/tilepro.c (TARGET_CONSTANT_ALIGNMENT): Redefine to constant_alignment_word_strings. * config/visium/visium.h (CONSTANT_ALIGNMENT): Delete. * config/visium/visium.c (TARGET_CONSTANT_ALIGNMENT): Redefine. (visium_constant_alignment): New function. * config/xtensa/xtensa.h (CONSTANT_ALIGNMENT): Delete. * config/xtensa/xtensa.c (TARGET_CONSTANT_ALIGNMENT): Redefine. (xtensa_constant_alignment): New function. * system.h (CONSTANT_ALIGNMENT): Poison. From-SVN: r253154
2017-09-25rs6000.c (rs6000_gimple_fold_builtin): Add handling for early folding of ↵Will Schmidt2-75/+70
vector stores (ALTIVEC_BUILTIN_ST_*). [gcc] 2017-09-25 Will Schmidt <will_schmidt@vnet.ibm.com> * config/rs6000/rs6000.c (rs6000_gimple_fold_builtin): Add handling for early folding of vector stores (ALTIVEC_BUILTIN_ST_*). (rs6000_builtin_valid_without_lhs): New helper function. * config/rs6000/rs6000-c.c (altivec_resolve_overloaded_builtin): Remove obsoleted code for handling ALTIVEC_BUILTIN_VEC_ST. From-SVN: r253152
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