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| author | Uros Bizjak <ubizjak@gmail.com> | 2017-09-28 20:14:27 +0200 |
|---|---|---|
| committer | Uros Bizjak <uros@gcc.gnu.org> | 2017-09-28 20:14:27 +0200 |
| commit | 5f643b6f49f66ff4d6f18ff374d0418a5f36c3d0 (patch) | |
| tree | 78b10c27aaaf84de3497ac9ed25d3c1cff250be0 /gcc/config | |
| parent | 10e93cf5978ab63059438b2ea7e68d94e043db96 (diff) | |
| download | gcc-5f643b6f49f66ff4d6f18ff374d0418a5f36c3d0.zip gcc-5f643b6f49f66ff4d6f18ff374d0418a5f36c3d0.tar.gz gcc-5f643b6f49f66ff4d6f18ff374d0418a5f36c3d0.tar.bz2 | |
i386.c (ix86_print_operand_address_as): Do not check index when encoding %esp as %rsp to avoid 0x67 prefix.
* config/i386/i386.c (ix86_print_operand_address_as): Do not check
index when encoding %esp as %rsp to avoid 0x67 prefix.
From-SVN: r253260
Diffstat (limited to 'gcc/config')
| -rw-r--r-- | gcc/config/i386/i386.c | 9 |
1 files changed, 4 insertions, 5 deletions
diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c index 63db7ac..e282546 100644 --- a/gcc/config/i386/i386.c +++ b/gcc/config/i386/i386.c @@ -19953,12 +19953,11 @@ ix86_print_operand_address_as (FILE *file, rtx addr, code = 'k'; } - /* Since the upper 32 bits of RSP are always zero for x32, we can - encode %esp as %rsp to avoid 0x67 prefix if there is no index or - base register. */ + /* Since the upper 32 bits of RSP are always zero for x32, + we can encode %esp as %rsp to avoid 0x67 prefix if + there is no index register. */ if (TARGET_X32 && Pmode == SImode - && ((!index && base && REG_P (base) && REGNO (base) == SP_REG) - || (!base && index && REGNO (index) == SP_REG))) + && !index && base && REG_P (base) && REGNO (base) == SP_REG) code = 'q'; if (ASSEMBLER_DIALECT == ASM_ATT) |