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| author | Andreas Krebbel <krebbel@linux.vnet.ibm.com> | 2017-09-26 10:35:27 +0000 |
|---|---|---|
| committer | Andreas Krebbel <krebbel@gcc.gnu.org> | 2017-09-26 10:35:27 +0000 |
| commit | 0c9ce4e61873debeede4b37b437ece5432c23ac7 (patch) | |
| tree | fac7a03c8e10c80e1fcac373ffcc4ea08e713b45 /gcc/config | |
| parent | 41067f07b9eb7bff5c26fe67ff9baefec2556a6b (diff) | |
| download | gcc-0c9ce4e61873debeede4b37b437ece5432c23ac7.zip gcc-0c9ce4e61873debeede4b37b437ece5432c23ac7.tar.gz gcc-0c9ce4e61873debeede4b37b437ece5432c23ac7.tar.bz2 | |
S/390: Fix vector fp unordered compares
V2DF mode was still hard-coded here.
gcc/ChangeLog:
2017-09-26 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
* config/s390/s390.c (s390_expand_vec_compare): Use the new mode
independent expanders.
* config/s390/vector.md ("vec_cmpuneq", "vec_cmpltgt")
("vec_ordered", "vec_unordered"): New expanders.
From-SVN: r253197
Diffstat (limited to 'gcc/config')
| -rw-r--r-- | gcc/config/s390/s390.c | 8 | ||||
| -rw-r--r-- | gcc/config/s390/vector.md | 64 |
2 files changed, 68 insertions, 4 deletions
diff --git a/gcc/config/s390/s390.c b/gcc/config/s390/s390.c index 0ceeef4..d2671ba 100644 --- a/gcc/config/s390/s390.c +++ b/gcc/config/s390/s390.c @@ -6396,16 +6396,16 @@ s390_expand_vec_compare (rtx target, enum rtx_code cond, /* UNLT: a u< b -> !(a >= b) */ case UNLT: cond = GE; neg_p = true; break; case UNEQ: - emit_insn (gen_vec_cmpuneqv2df (target, cmp_op1, cmp_op2)); + emit_insn (gen_vec_cmpuneq (target, cmp_op1, cmp_op2)); return; case LTGT: - emit_insn (gen_vec_cmpltgtv2df (target, cmp_op1, cmp_op2)); + emit_insn (gen_vec_cmpltgt (target, cmp_op1, cmp_op2)); return; case ORDERED: - emit_insn (gen_vec_orderedv2df (target, cmp_op1, cmp_op2)); + emit_insn (gen_vec_ordered (target, cmp_op1, cmp_op2)); return; case UNORDERED: - emit_insn (gen_vec_unorderedv2df (target, cmp_op1, cmp_op2)); + emit_insn (gen_vec_unordered (target, cmp_op1, cmp_op2)); return; default: break; } diff --git a/gcc/config/s390/vector.md b/gcc/config/s390/vector.md index 06c88c1..d40bf1e 100644 --- a/gcc/config/s390/vector.md +++ b/gcc/config/s390/vector.md @@ -1406,6 +1406,22 @@ operands[3] = gen_reg_rtx (<tointvec>mode); }) +(define_expand "vec_cmpuneq" + [(match_operand 0 "register_operand" "") + (match_operand 1 "register_operand" "") + (match_operand 2 "register_operand" "")] + "TARGET_VX" +{ + if (GET_MODE (operands[1]) == V4SFmode) + emit_insn (gen_vec_cmpuneqv4sf (operands[0], operands[1], operands[2])); + else if (GET_MODE (operands[1]) == V2DFmode) + emit_insn (gen_vec_cmpuneqv2df (operands[0], operands[1], operands[2])); + else + gcc_unreachable (); + + DONE; +}) + ; LTGT a <> b -> a > b | b > a (define_expand "vec_cmpltgt<mode>" [(set (match_operand:<tointvec> 0 "register_operand" "=v") @@ -1418,6 +1434,22 @@ operands[3] = gen_reg_rtx (<tointvec>mode); }) +(define_expand "vec_cmpltgt" + [(match_operand 0 "register_operand" "") + (match_operand 1 "register_operand" "") + (match_operand 2 "register_operand" "")] + "TARGET_VX" +{ + if (GET_MODE (operands[1]) == V4SFmode) + emit_insn (gen_vec_cmpltgtv4sf (operands[0], operands[1], operands[2])); + else if (GET_MODE (operands[1]) == V2DFmode) + emit_insn (gen_vec_cmpltgtv2df (operands[0], operands[1], operands[2])); + else + gcc_unreachable (); + + DONE; +}) + ; ORDERED (a, b): a >= b | b > a (define_expand "vec_ordered<mode>" [(set (match_operand:<tointvec> 0 "register_operand" "=v") @@ -1430,6 +1462,22 @@ operands[3] = gen_reg_rtx (<tointvec>mode); }) +(define_expand "vec_ordered" + [(match_operand 0 "register_operand" "") + (match_operand 1 "register_operand" "") + (match_operand 2 "register_operand" "")] + "TARGET_VX" +{ + if (GET_MODE (operands[1]) == V4SFmode) + emit_insn (gen_vec_orderedv4sf (operands[0], operands[1], operands[2])); + else if (GET_MODE (operands[1]) == V2DFmode) + emit_insn (gen_vec_orderedv2df (operands[0], operands[1], operands[2])); + else + gcc_unreachable (); + + DONE; +}) + ; UNORDERED (a, b): !ORDERED (a, b) (define_expand "vec_unordered<mode>" [(set (match_operand:<tointvec> 0 "register_operand" "=v") @@ -1443,6 +1491,22 @@ operands[3] = gen_reg_rtx (<tointvec>mode); }) +(define_expand "vec_unordered" + [(match_operand 0 "register_operand" "") + (match_operand 1 "register_operand" "") + (match_operand 2 "register_operand" "")] + "TARGET_VX" +{ + if (GET_MODE (operands[1]) == V4SFmode) + emit_insn (gen_vec_unorderedv4sf (operands[0], operands[1], operands[2])); + else if (GET_MODE (operands[1]) == V2DFmode) + emit_insn (gen_vec_unorderedv2df (operands[0], operands[1], operands[2])); + else + gcc_unreachable (); + + DONE; +}) + (define_insn "*vec_load_pair<mode>" [(set (match_operand:V_HW_64 0 "register_operand" "=v,v") (vec_concat:V_HW_64 (match_operand:<non_vec> 1 "register_operand" "d,v") |