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| author | Carl Love <cel@us.ibm.com> | 2017-09-27 22:45:49 +0000 |
|---|---|---|
| committer | Carl Love <carll@gcc.gnu.org> | 2017-09-27 22:45:49 +0000 |
| commit | 4ca4cf4e420cc817fc66949d4c8069f951d857b4 (patch) | |
| tree | d7de4843e9fcb20ffdf233368801957c8bc56a86 /gcc/config | |
| parent | c32026239618bac471c9c08a723b58885061ed62 (diff) | |
| download | gcc-4ca4cf4e420cc817fc66949d4c8069f951d857b4.zip gcc-4ca4cf4e420cc817fc66949d4c8069f951d857b4.tar.gz gcc-4ca4cf4e420cc817fc66949d4c8069f951d857b4.tar.bz2 | |
rs6000-builtin.def (BU_FP_1MISC_1): Add define macro.
gcc/ChangeLog:
2017-09-27 Carl Love <cel@us.ibm.com>
* config/rs6000/rs6000-builtin.def (BU_FP_1MISC_1): Add define macro.
(FCTID, FCTIW): Add BU_FP_MISC_1 macro expansion for builtins.
* config/rs6000/rs6000.md (lrintsfsi2): Add define_insn for the
fctiw instruction.
gcc/testsuite/ChangeLog:
2017-09-27 Carl Love <cel@us.ibm.com>
* gcc.target/powerpc/builtin-fctid-fctiw-runnable.c: New test file
for the __builtin_fctid and __builtin_fctiw.
From-SVN: r253238
Diffstat (limited to 'gcc/config')
| -rw-r--r-- | gcc/config/rs6000/rs6000-builtin.def | 14 | ||||
| -rw-r--r-- | gcc/config/rs6000/rs6000.md | 8 |
2 files changed, 22 insertions, 0 deletions
diff --git a/gcc/config/rs6000/rs6000-builtin.def b/gcc/config/rs6000/rs6000-builtin.def index 151ac64..868b0cd 100644 --- a/gcc/config/rs6000/rs6000-builtin.def +++ b/gcc/config/rs6000/rs6000-builtin.def @@ -608,6 +608,16 @@ CODE_FOR_ ## ICODE) /* ICODE */ +/* Miscellaneous builtins for instructions added prior to ISA 2.04. These + operate on floating point registers. */ +#define BU_FP_MISC_1(ENUM, NAME, ATTR, ICODE) \ + RS6000_BUILTIN_1 (MISC_BUILTIN_ ## ENUM, /* ENUM */ \ + "__builtin_" NAME, /* NAME */ \ + RS6000_BTM_HARD_FLOAT, /* MASK */ \ + (RS6000_BTC_ ## ATTR /* ATTR */ \ + | RS6000_BTC_UNARY), \ + CODE_FOR_ ## ICODE) /* ICODE */ + /* Miscellaneous builtins for instructions added in ISA 2.06. These instructions don't require either the DFP or VSX options, just the basic ISA 2.06 (popcntd) enablement since they operate on general purpose @@ -1863,6 +1873,10 @@ BU_VSX_OVERLOAD_X (XL, "xl") BU_VSX_OVERLOAD_X (XL_BE, "xl_be") BU_VSX_OVERLOAD_X (XST, "xst") +/* 1 argument builtins pre ISA 2.04. */ +BU_FP_MISC_1 (FCTID, "fctid", CONST, lrintdfdi2) +BU_FP_MISC_1 (FCTIW, "fctiw", CONST, lrintsfsi2) + /* 2 argument CMPB instructions added in ISA 2.05. */ BU_P6_2 (CMPB_32, "cmpb_32", CONST, cmpbsi3) BU_P6_64BIT_2 (CMPB, "cmpb", CONST, cmpbdi3) diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index 9b10e7f..3181291 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -5915,6 +5915,14 @@ [(set_attr "type" "fpload") (set_attr "length" "16")]) +(define_insn "lrintsfsi2" + [(set (match_operand:SI 0 "gpc_reg_operand" "=d") + (unspec:SI [(match_operand:DF 1 "gpc_reg_operand" "d")] + UNSPEC_FCTIW))] + "TARGET_SF_FPR && TARGET_FPRND" + "fctiw %0,%1" + [(set_attr "type" "fp")]) + ;; No VSX equivalent to fctid (define_insn "lrint<mode>di2" [(set (match_operand:DI 0 "gpc_reg_operand" "=d") |