riscv-gnu-toolchain/gcc.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2023-01-31	RISC-V: Add indexed loads/stores C/C++ intrinsic support	Ju-Zhe Zhong	11	-33/+845
2023-01-30	Add support for x86_64--gnu- targets to build x86_64 gnumach/hurd	Flavio Cruz	1	-0/+40
2023-01-30	aarch64: Update Ampere-1A (-mcpu=ampere1a) to include SM4	Philipp Tomsich	1	-1/+1
2023-01-30	Change AVX512FP16 to AVX512-FP16 in the document.	liuhongt	1	-1/+1
2023-01-29	aarch64: Correct the maximum shift amount for shifted operands	Philipp Tomsich	1	-1/+1
2023-01-28	RISC-V: Add vlse/vsse intrinsics support	Ju-Zhe Zhong	6	-14/+143
2023-01-28	RISC-V: Remove redundant attributes [NFC]	Ju-Zhe Zhong	1	-20/+0
2023-01-27	mips: Don't add crtfastmath.o for -shared	Richard Biener	1	-1/+1
2023-01-27	ia64: Don't add crtfastmath.o for -shared	Richard Biener	1	-1/+1
2023-01-27	alpha: Don't add crtfastmath.o for -shared	Richard Biener	1	-1/+1
2023-01-27	RISC-V: Fix vop_m overloaded C++ API name.	Ju-Zhe Zhong	1	-0/+4
2023-01-27	RISC-V: Add vlm/vsm C/C++ API intrinsics support	Ju-Zhe Zhong	7	-8/+86
2023-01-27	RISC-V: Finalize VSETVL PASS implementation	Ju-Zhe Zhong	2	-223/+737
2023-01-27	RISC-V: Fix bug of before_p function	Ju-Zhe Zhong	1	-1/+1
2023-01-27	RISC-V: Refine function args of some functions.	Ju-Zhe Zhong	1	-3/+3
2023-01-27	RISC-V: Fix pred_mov constraint for vle.v	Ju-Zhe Zhong	1	-14/+15
2023-01-27	RISC-V: Add TARGET_MIN_VLEN > 32 into iterators of EEW = 64 vector modes	Ju-Zhe Zhong	1	-2/+4
2023-01-27	RISC-V: Change parse_insn into public for future use.	Ju-Zhe Zhong	1	-3/+4
2023-01-27	RISC-V: Reorder VSETVL pass location	Ju-Zhe Zhong	1	-1/+1
2023-01-27	RISC-V: Change VSETVL PASS always call split_all_insns	Ju-Zhe Zhong	1	-6/+4
2023-01-27	RISC-V: Fix incorrect attributes of vsetvl instructions pattern	Ju-Zhe Zhong	1	-15/+12
2023-01-27	LoongArch: Don't add crtfastmath.o for -shared	Richard Biener	1	-1/+1
2023-01-27	RISC-V: Use get_typenode_from_name to get fixed-width integer type nodes	Kito Cheng	2	-47/+48
2023-01-27	RISC-V: Fix bugs of supporting AVL=REG (single-real-def) in VSETVL PASS	Ju-Zhe Zhong	2	-285/+709
2023-01-27	RISC-V: Add probability model of each block to prevent endless loop of Phase 3	Ju-Zhe Zhong	2	-0/+42
2023-01-27	RISC-V: Remove dirty_pat since it is redundant	Ju-Zhe Zhong	2	-26/+13
2023-01-27	RISC-V: Rename insn into rinsn for rtx_insn * [NFC]	Ju-Zhe Zhong	1	-5/+5
2023-01-27	RISC-V: Refine codes in backward fusion [NFC]	Ju-Zhe Zhong	1	-4/+4
2023-01-27	RISC-V: Avoid redundant flow in forward fusion	Ju-Zhe Zhong	1	-0/+8
2023-01-27	RISC-V: Cleanup the codes of bitmap create and free [NFC]	Ju-Zhe Zhong	2	-38/+59
2023-01-27	RISC-V: Refine Phase 3 of VSETVL PASS	Ju-Zhe Zhong	2	-10/+128
2023-01-27	RISC-V: Fix bugs of available condition.	Ju-Zhe Zhong	1	-4/+2
2023-01-27	RISC-V: Simplify codes of changing vsetvl instruction	Ju-Zhe Zhong	1	-16/+20
2023-01-27	RISC-V: Fix backward_propagate_worthwhile_p	Ju-Zhe Zhong	1	-20/+71
2023-01-27	RISC-V: Fix wrong in_group flag in validate_change call function	Ju-Zhe Zhong	1	-1/+1
2023-01-27	RISC-V: Fix bugs for refine vsetvl a5, zero into vsetvl zero, zero incorrectly	Ju-Zhe Zhong	2	-4/+34
2023-01-27	RISC-V: Fix vsetivli instruction asm for IMM AVL	Ju-Zhe Zhong	1	-1/+1
2023-01-27	RISC-V: Fix inferior codegen for vse intrinsics.	Ju-Zhe Zhong	4	-24/+31
2023-01-27	RISC-V: Fix pointer tree type for store pointer.	Ju-Zhe Zhong	1	-1/+1
2023-01-26	aarch64: Add Linux kernel hwcap string for FEAT_CSSC	Kyrylo Tkachov	1	-1/+1
2023-01-25	arm: improve tests and fix vqnegq*	Andrea Corallo	1	-1/+1
2023-01-25	arm: improve tests and fix vqabsq*	Andrea Corallo	1	-1/+1
2023-01-25	arm: improve tests and fix vnegq*	Andrea Corallo	1	-2/+2
2023-01-25	arm: improve tests and fix vclzq*	Andrea Corallo	1	-1/+1
2023-01-25	arm: improve tests and fix vclsq*	Andrea Corallo	1	-1/+1
2023-01-25	aarch64: Restore generation of SVE UQDEC instructions	Richard Sandiford	1	-2/+3
2023-01-24	xtensa: Revise complex hard register clobber elimination	Takayuki 'January June' Suwa	1	-35/+37
2023-01-24	IBM zSystems: Fix TARGET_D_CPU_VERSIONS	Stefan Schulze Frielinghaus	1	-4/+5
2023-01-24	arm: Make MVE masked stores read memory operand [PR 108177]	Andre Vieira	1	-21/+24
2023-01-25	C-SKY: Fix wrong sysroot suffix when disable multilib.	Xianmiao Qu	1	-0/+3