arm: Make MVE masked stores read memory operand [PR 108177]

This patch adds the memory operand of MVE masked stores as input operands to
mimic the 'partial' writes, to prevent erroneous write-after-write
optimizations as described in the PR.

gcc/ChangeLog:

	PR target/108177
	* config/arm/mve.md (mve_vstrbq_p_<supf><mode>, mve_vstrhq_p_fv8hf,
	mve_vstrhq_p_<supf><mode>, mve_vstrwq_p_<supf>v4si): Add memory operand
	as input operand.

gcc/testsuite/ChangeLog:

	* gcc.target/arm/mve/pr108177-1-run.c: New test.
	* gcc.target/arm/mve/pr108177-1.c: New test.
	* gcc.target/arm/mve/pr108177-10-run.c: New test.
	* gcc.target/arm/mve/pr108177-10.c: New test.
	* gcc.target/arm/mve/pr108177-11-run.c: New test.
	* gcc.target/arm/mve/pr108177-11.c: New test.
	* gcc.target/arm/mve/pr108177-12-run.c: New test.
	* gcc.target/arm/mve/pr108177-12.c: New test.
	* gcc.target/arm/mve/pr108177-13-run.c: New test.
	* gcc.target/arm/mve/pr108177-13.c: New test.
	* gcc.target/arm/mve/pr108177-14-run.c: New test.
	* gcc.target/arm/mve/pr108177-14.c: New test.
	* gcc.target/arm/mve/pr108177-2-run.c: New test.
	* gcc.target/arm/mve/pr108177-2.c: New test.
	* gcc.target/arm/mve/pr108177-3-run.c: New test.
	* gcc.target/arm/mve/pr108177-3.c: New test.
	* gcc.target/arm/mve/pr108177-4-run.c: New test.
	* gcc.target/arm/mve/pr108177-4.c: New test.
	* gcc.target/arm/mve/pr108177-5-run.c: New test.
	* gcc.target/arm/mve/pr108177-5.c: New test.
	* gcc.target/arm/mve/pr108177-6-run.c: New test.
	* gcc.target/arm/mve/pr108177-6.c: New test.
	* gcc.target/arm/mve/pr108177-7-run.c: New test.
	* gcc.target/arm/mve/pr108177-7.c: New test.
	* gcc.target/arm/mve/pr108177-8-run.c: New test.
	* gcc.target/arm/mve/pr108177-8.c: New test.
	* gcc.target/arm/mve/pr108177-9-run.c: New test.
	* gcc.target/arm/mve/pr108177-9.c: New test.
	* gcc.target/arm/mve/pr108177-main.x: New test include.
	* gcc.target/arm/mve/pr108177.x: New test include.

1 files changed, 24 insertions, 21 deletions

diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md
index f123edc..2e58ad1 100644
--- a/gcc/config/arm/mve.md
+++ b/gcc/config/arm/mve.md
@@ -7272,15 +7272,13 @@
 }
   [(set_attr "length" "8")])
 
-;;
-;; [vstrbq_p_s vstrbq_p_u]
-;;
 (define_insn "mve_vstrbq_p_<supf><mode>"
   [(set (match_operand:<MVE_B_ELEM> 0 "mve_memory_operand" "=Ux")
-	(unspec:<MVE_B_ELEM> [(match_operand:MVE_2 1 "s_register_operand" "w")
-			      (match_operand:<MVE_VPRED> 2 "vpr_register_operand" "Up")]
-	 VSTRBQ))
-  ]
+	(unspec:<MVE_B_ELEM>
+	 [(match_operand:MVE_2 1 "s_register_operand" "w")
+	  (match_operand:<MVE_VPRED> 2 "vpr_register_operand" "Up")
+	  (match_dup 0)]
+	 VSTRBQ))]
   "TARGET_HAVE_MVE"
 {
    rtx ops[2];
@@ -8079,10 +8077,11 @@
 ;;
 (define_insn "mve_vstrhq_p_fv8hf"
   [(set (match_operand:V8HI 0 "mve_memory_operand" "=Ux")
-	(unspec:V8HI [(match_operand:V8HF 1 "s_register_operand" "w")
-		      (match_operand:V8BI 2 "vpr_register_operand" "Up")]
-	 VSTRHQ_F))
-  ]
+	(unspec:V8HI
+	 [(match_operand:V8HF 1 "s_register_operand" "w")
+	  (match_operand:V8BI 2 "vpr_register_operand" "Up")
+	  (match_dup 0)]
+	 VSTRHQ_F))]
   "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
 {
    rtx ops[2];
@@ -8099,8 +8098,10 @@
 ;;
 (define_insn "mve_vstrhq_p_<supf><mode>"
   [(set (match_operand:<MVE_H_ELEM> 0 "mve_memory_operand" "=Ux")
-	(unspec:<MVE_H_ELEM> [(match_operand:MVE_6 1 "s_register_operand" "w")
-			      (match_operand:<MVE_VPRED> 2 "vpr_register_operand" "Up")]
+	(unspec:<MVE_H_ELEM>
+	 [(match_operand:MVE_6 1 "s_register_operand" "w")
+	  (match_operand:<MVE_VPRED> 2 "vpr_register_operand" "Up")
+	  (match_dup 0)]
 	 VSTRHQ))
   ]
   "TARGET_HAVE_MVE"
@@ -8278,10 +8279,11 @@
 ;;
 (define_insn "mve_vstrwq_p_fv4sf"
   [(set (match_operand:V4SI 0 "mve_memory_operand" "=Ux")
-	(unspec:V4SI [(match_operand:V4SF 1 "s_register_operand" "w")
-		      (match_operand:<MVE_VPRED> 2 "vpr_register_operand" "Up")]
-	 VSTRWQ_F))
-  ]
+	(unspec:V4SI
+	 [(match_operand:V4SF 1 "s_register_operand" "w")
+	  (match_operand:<MVE_VPRED> 2 "vpr_register_operand" "Up")
+	  (match_dup 0)]
+	 VSTRWQ_F))]
   "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
 {
    rtx ops[2];
@@ -8298,10 +8300,11 @@
 ;;
 (define_insn "mve_vstrwq_p_<supf>v4si"
   [(set (match_operand:V4SI 0 "mve_memory_operand" "=Ux")
-	(unspec:V4SI [(match_operand:V4SI 1 "s_register_operand" "w")
-		      (match_operand:V4BI 2 "vpr_register_operand" "Up")]
-	 VSTRWQ))
-  ]
+	(unspec:V4SI
+	 [(match_operand:V4SI 1 "s_register_operand" "w")
+	  (match_operand:V4BI 2 "vpr_register_operand" "Up")
+	  (match_dup 0)]
+	 VSTRWQ))]
   "TARGET_HAVE_MVE"
 {
    rtx ops[2];