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AgeCommit message (Expand)AuthorFilesLines
2024-10-25gcc: Remove trailing whitespaceJakub Jelinek180-1688/+1688
2024-10-25SVE intrinsics: Fold svaba with op1 all zeros to svabd.Jennifer Schmitz1-0/+18
2024-10-24AVR: target/116953 - Restore recog_data after calling jump_over_one_insn_p.Georg-Johann Lay1-5/+5
2024-10-24Use unique_ptr in more places in pretty_printer/diagnostics: 'gcc/config/gcn/...Thomas Schwinge1-0/+1
2024-10-24Use unique_ptr in more places in pretty_printer/diagnostics [PR116613]David Malcolm35-0/+35
2024-10-24SVE intrinsics: Fold svsra with op1 all zeros to svlsr/svasr.Jennifer Schmitz1-0/+28
2024-10-24SVE intrinsics: Fold constant operands for svlsl.Soumya AR2-2/+18
2024-10-24SVE intrinsics: Fold division and multiplication by -1 to negJennifer Schmitz1-11/+62
2024-10-24SVE intrinsics: Add constant folding for svindex.Jennifer Schmitz1-0/+14
2024-10-23[PATCH] RISC-V: override alignment of function/jump/loopWang Pengcheng1-0/+15
2024-10-23aarch64: Fix warning in aarch64_ptrue_regAndrew Pinski1-2/+2
2024-10-23aarch64: Improve scalar mode popcount expansion by using SVE [PR113860]Pengxuan Zheng5-6/+56
2024-10-23AArch64: Remove redundant check in aarch64_simd_movWilco Dijkstra1-1/+0
2024-10-23AArch64: Fix copysign patternsWilco Dijkstra2-29/+27
2024-10-23AArch64: Add support for SIMD xor immediate (3/3)Wilco Dijkstra4-6/+35
2024-10-23AArch64: Improve SIMD immediate generation (2/3)Wilco Dijkstra3-19/+37
2024-10-23AArch64: Improve SIMD immediate generation (1/3)Wilco Dijkstra5-76/+118
2024-10-23Fix ICE due to isa mismatch for the builtins.liuhongt1-8/+8
2024-10-22i386: Optimize EQ/NE comparison between avx512 kmask and -1.liuhongt1-0/+85
2024-10-22GCN: Initial generic-target handling, add more GCN macro definesTobias Burnus7-32/+147
2024-10-22amdgcn: Refactor device settings into a def fileAndrew Stubbs13-271/+476
2024-10-21RISC-V: Implement vector SAT_TRUNC for signed integerPan Li3-0/+84
2024-10-21aarch64: Fix costing of move to/from MOVEABLE_SYSREGSAndrew Carlotti1-0/+6
2024-10-21amdgcn: silence warningAndrew Stubbs1-1/+1
2024-10-21rs6000: Correct the function code for _AMO_LD_DEC_BOUNDEDJeevitha1-1/+1
2024-10-21Refine splitters related to "combine vpcmpuw + zero_extend to vpcmpuw"liuhongt1-117/+81
2024-10-20Revert "[PATCH 7/7] RISC-V: Disable by pieces for vector setmem length > UNIT...Jeff Law1-19/+0
2024-10-19[PATCH][v5] RISC-V: add option -m(no-)autovec-segmentGreg McGary3-2/+11
2024-10-19[PATCH 7/7] RISC-V: Disable by pieces for vector setmem length > UNITS_PER_WORDCraig Blackmore1-0/+19
2024-10-19[PATCH 5/7] RISC-V: Move vector memcpy decision making to separate function [...Craig Blackmore1-56/+87
2024-10-19[PATCH 4/7] RISC-V: Honour -mrvv-max-lmul in riscv_vector::expand_block_moveCraig Blackmore4-38/+54
2024-10-18gcc/: Rename array_type_nelts => array_type_nelts_minus_oneAlejandro Colomar2-2/+2
2024-10-18hppa: Fix up pa.opt.urlsJohn David Anglin1-0/+2
2024-10-18hppa: Add LRA supportJohn David Anglin3-38/+66
2024-10-18[PATCH 3/7] RISC-V: Fix vector memcpy smaller LMUL generationCraig Blackmore1-3/+5
2024-10-18[PATCH 2/7] RISC-V: Fix uninitialized reg in memcpyCraig Blackmore1-2/+1
2024-10-18[PATCH 1/7] RISC-V: Fix indentation in riscv_vector::expand_block_move [NFC]Craig Blackmore1-16/+16
2024-10-18i386: Fix the order of operands in andn<MMXMODEI:mode>3 [PR117192]Uros Bizjak1-3/+3
2024-10-18SVE intrinsics: Add fold_active_lanes_to method to refactor svmul and svdiv.Jennifer Schmitz3-22/+45
2024-10-18AArch64: use movi d0, #0 to clear SVE registers instead of mov z0.d, #0Tamar Christina1-2/+5
2024-10-18AArch64: support encoding integer immediates using floating point movesTamar Christina1-128/+154
2024-10-18arm: [MVE intrinsics] use long_type_suffix / half_type_suffix helpersChristophe Lyon1-46/+68
2024-10-18arm: [MVE intrinsics] rework vsbcq vsbciqChristophe Lyon4-188/+42
2024-10-18arm: [MVE intrinsics] rework vadcqChristophe Lyon4-94/+56
2024-10-18arm: [MVE intrinsics] rework vadciqChristophe Lyon4-89/+95
2024-10-18arm: [MVE intrinsics] factorize vadc vadci vsbc vsbciChristophe Lyon2-109/+42
2024-10-18arm: [MVE intrinsics] add vadc_vsbc shapeChristophe Lyon2-0/+37
2024-10-18arm: [MVE intrinsics] remove vshlcq useless expandersChristophe Lyon3-81/+0
2024-10-18arm: [MVE intrinsics] rework vshlcqChristophe Lyon6-235/+77
2024-10-18arm: [MVE intrinsics] add vshlc shapeChristophe Lyon2-0/+45
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