diff options
Diffstat (limited to 'gcc/config')
180 files changed, 1688 insertions, 1688 deletions
diff --git a/gcc/config/aarch64/aarch64-builtins.cc b/gcc/config/aarch64/aarch64-builtins.cc index 7d73787..c488563 100644 --- a/gcc/config/aarch64/aarch64-builtins.cc +++ b/gcc/config/aarch64/aarch64-builtins.cc @@ -1161,7 +1161,7 @@ aarch64_simd_builtin_type (machine_mode mode, return type; } - + static void aarch64_init_simd_builtin_types (void) { diff --git a/gcc/config/aarch64/aarch64-cost-tables.h b/gcc/config/aarch64/aarch64-cost-tables.h index 7c79491..5e0c1f7 100644 --- a/gcc/config/aarch64/aarch64-cost-tables.h +++ b/gcc/config/aarch64/aarch64-cost-tables.h @@ -346,7 +346,7 @@ const struct cpu_cost_table thunderx2t99_extra_costs = } }; -const struct cpu_cost_table thunderx3t110_extra_costs = +const struct cpu_cost_table thunderx3t110_extra_costs = { /* ALU */ { diff --git a/gcc/config/aarch64/aarch64-protos.h b/gcc/config/aarch64/aarch64-protos.h index 75f30a5..9be6491 100644 --- a/gcc/config/aarch64/aarch64-protos.h +++ b/gcc/config/aarch64/aarch64-protos.h @@ -627,7 +627,7 @@ struct aarch64_address_info { }; #define AARCH64_FUSION_PAIR(x, name) \ - AARCH64_FUSE_##name##_index, + AARCH64_FUSE_##name##_index, /* Supported fusion operations. */ enum aarch64_fusion_pairs_index { diff --git a/gcc/config/aarch64/aarch64.cc b/gcc/config/aarch64/aarch64.cc index 7fbe3a7..a6cc00e 100644 --- a/gcc/config/aarch64/aarch64.cc +++ b/gcc/config/aarch64/aarch64.cc @@ -9105,7 +9105,7 @@ aarch64_process_components (sbitmap components, bool prologue_p) { bool frame_related_p = aarch64_emit_cfi_for_reg_p (regno); machine_mode mode = aarch64_reg_save_mode (regno); - + rtx reg = gen_rtx_REG (mode, regno); poly_int64 offset = frame.reg_offset[regno]; if (frame_pointer_needed) @@ -10290,7 +10290,7 @@ aarch64_cannot_force_const_mem (machine_mode mode ATTRIBUTE_UNUSED, rtx x) /* Implement TARGET_CASE_VALUES_THRESHOLD. The expansion for a table switch is quite expensive due to the number of instructions, the table lookup and hard to predict indirect jump. - When optimizing for speed, and -O3 enabled, use the per-core tuning if + When optimizing for speed, and -O3 enabled, use the per-core tuning if set, otherwise use tables for >= 11 cases as a tradeoff between size and performance. When optimizing for size, use 8 for smallest codesize. */ diff --git a/gcc/config/alpha/alpha.cc b/gcc/config/alpha/alpha.cc index 74631a4..d7f5e3b 100644 --- a/gcc/config/alpha/alpha.cc +++ b/gcc/config/alpha/alpha.cc @@ -3269,7 +3269,7 @@ alpha_emit_xfloating_cvt (enum rtx_code orig_code, rtx operands[]) set (OP[1] OP[3]) is valid. Naturally, output operand ordering is little-endian. This is used by *movtf_internal and *movti_internal. */ - + void alpha_split_tmode_pair (rtx operands[4], machine_mode mode, bool fixup_overlap) @@ -4410,7 +4410,7 @@ emit_insxl (machine_mode mode, rtx op1, rtx op2) } /* Expand an atomic fetch-and-operate pattern. CODE is the binary operation - to perform. MEM is the memory on which to operate. VAL is the second + to perform. MEM is the memory on which to operate. VAL is the second operand of the binary operator. BEFORE and AFTER are optional locations to return the value of MEM either before of after the operation. SCRATCH is a scratch register. */ @@ -4594,7 +4594,7 @@ alpha_split_compare_and_swap_12 (rtx operands[]) label2 = gen_rtx_LABEL_REF (DImode, gen_label_rtx ()); emit_insn (gen_load_locked (DImode, scratch, mem)); - + width = GEN_INT (GET_MODE_BITSIZE (mode)); mask = GEN_INT (mode == QImode ? 0xff : 0xffff); emit_insn (gen_extxl (dest, scratch, width, addr)); @@ -4725,7 +4725,7 @@ alpha_split_atomic_exchange_12 (rtx operands[]) emit_label (XEXP (label, 0)); emit_insn (gen_load_locked (DImode, scratch, mem)); - + width = GEN_INT (GET_MODE_BITSIZE (mode)); mask = GEN_INT (mode == QImode ? 0xff : 0xffff); emit_insn (gen_extxl (dest, scratch, width, addr)); @@ -5019,7 +5019,7 @@ get_trap_mode_suffix (void) gcc_unreachable (); } break; - + default: gcc_unreachable (); } @@ -5056,7 +5056,7 @@ get_round_mode_suffix (void) case ROUND_SUFFIX_C: return "c"; - + default: gcc_unreachable (); } @@ -6151,7 +6151,7 @@ alpha_setup_incoming_varargs (cumulative_args_t pcum, /* Detect whether integer registers or floating-point registers are needed by the detected va_arg statements. See above for how these values are computed. Note that the "escape" value - is VA_LIST_MAX_FPR_SIZE, which is 255, which has both of + is VA_LIST_MAX_FPR_SIZE, which is 255, which has both of these bits set. */ gcc_assert ((VA_LIST_MAX_FPR_SIZE & 3) == 3); @@ -6754,7 +6754,7 @@ alpha_fold_builtin_cmpbge (unsigned HOST_WIDE_INT opint[], long op_const) return NULL; } -/* Fold the builtin for the ZAPNOT instruction. This is essentially a +/* Fold the builtin for the ZAPNOT instruction. This is essentially a specialized form of an AND operation. Other byte manipulation instructions are defined in terms of this instruction, so this is also used as a subroutine for other builtins. @@ -6821,7 +6821,7 @@ alpha_fold_builtin_extxx (tree op[], unsigned HOST_WIDE_INT opint[], else zap_op = op; } - + opint[1] = bytemask; return alpha_fold_builtin_zapnot (zap_op, opint, zap_const); } @@ -7422,7 +7422,7 @@ alpha_vms_can_eliminate (const int from ATTRIBUTE_UNUSED, const int to) HOST_WIDE_INT alpha_vms_initial_elimination_offset (unsigned int from, unsigned int to) -{ +{ /* The only possible attempts we ever expect are ARG or FRAME_PTR to HARD_FRAME or STACK_PTR. We need the alpha_procedure_type to decide on the proper computations and will need the register save area size @@ -7433,7 +7433,7 @@ alpha_vms_initial_elimination_offset (unsigned int from, unsigned int to) /* PT_NULL procedures have no frame of their own and we only allow elimination to the stack pointer. This is the argument pointer and we resolve the soft frame pointer to that as well. */ - + if (alpha_procedure_type == PT_NULL) return 0; @@ -7448,13 +7448,13 @@ alpha_vms_initial_elimination_offset (unsigned int from, unsigned int to) ^ ^ ^ ^ ARG_PTR FRAME_PTR HARD_FRAME_PTR STACK_PTR - + PT_REGISTER procedures are similar in that they may have a frame of their own. They have no regs-sa/pv/outgoing-args area. We first compute offset to HARD_FRAME_PTR, then add what we need to get to STACK_PTR if need be. */ - + { HOST_WIDE_INT offset; HOST_WIDE_INT pv_save_size = alpha_procedure_type == PT_STACK ? 8 : 0; @@ -7473,10 +7473,10 @@ alpha_vms_initial_elimination_offset (unsigned int from, unsigned int to) default: gcc_unreachable (); } - + if (to == STACK_POINTER_REGNUM) offset += ALPHA_ROUND (crtl->outgoing_args_size); - + return offset; } } @@ -8828,7 +8828,7 @@ alpha_handle_trap_shadows (void) suitably aligned. This is very processor-specific. */ /* There are a number of entries in alphaev4_insn_pipe and alphaev5_insn_pipe that are marked "fake". These instructions do not exist on that target, - but it is possible to see these insns with deranged combinations of + but it is possible to see these insns with deranged combinations of command-line options, such as "-mtune=ev4 -mmax". Instead of aborting, choose a result at random. */ @@ -9465,7 +9465,7 @@ And in the noreturn case: after the insn. In case trap is the last insn in the function, emit NOP to guarantee that PC remains inside function boundaries. This workaround is needed to get reliable backtraces. */ - + rtx_insn *insn = prev_active_insn (get_last_insn ()); if (insn && NONJUMP_INSN_P (insn)) @@ -9725,7 +9725,7 @@ alpha_write_linkage (FILE *stream, const char *funname) the section; 0 if the default should be used. */ static void -vms_asm_named_section (const char *name, unsigned int flags, +vms_asm_named_section (const char *name, unsigned int flags, tree decl ATTRIBUTE_UNUSED) { fputc ('\n', asm_out_file); diff --git a/gcc/config/alpha/driver-alpha.cc b/gcc/config/alpha/driver-alpha.cc index 816d06b..16f0e7f 100644 --- a/gcc/config/alpha/driver-alpha.cc +++ b/gcc/config/alpha/driver-alpha.cc @@ -33,7 +33,7 @@ along with GCC; see the file COPYING3. If not see /* Bit defines for amask instruction. */ #define AMASK_BWX 0x1 /* byte/word extension. */ -#define AMASK_FIX 0x2 /* sqrt and f <-> i conversions +#define AMASK_FIX 0x2 /* sqrt and f <-> i conversions extension. */ #define AMASK_CIX 0x4 /* count extension. */ #define AMASK_MVI 0x100 /* multimedia extension. */ diff --git a/gcc/config/alpha/elf.h b/gcc/config/alpha/elf.h index a10454a..d4f1d40 100644 --- a/gcc/config/alpha/elf.h +++ b/gcc/config/alpha/elf.h @@ -25,7 +25,7 @@ along with GCC; see the file COPYING3. If not see #define ASM_SPEC "%{G*} %{relax:-relax} %{mcpu=*:-m%*}" /* Do not output a .file directive at the beginning of the input file. */ - + #undef TARGET_ASM_FILE_START_FILE_DIRECTIVE #define TARGET_ASM_FILE_START_FILE_DIRECTIVE false diff --git a/gcc/config/alpha/vms.h b/gcc/config/alpha/vms.h index 8038f0e..4226804 100644 --- a/gcc/config/alpha/vms.h +++ b/gcc/config/alpha/vms.h @@ -188,8 +188,8 @@ typedef struct {int num_args; enum avms_arg_type atypes[6];} avms_arg_info; #define ASM_OUTPUT_CASE_LABEL(FILE,PREFIX,NUM,TABLEINSN) \ { ASM_OUTPUT_ALIGN (FILE, 3); (*targetm.asm_out.internal_label) (FILE, PREFIX, NUM); } -/* This says how to output assembler code to declare an - uninitialized external linkage data object. */ +/* This says how to output assembler code to declare an + uninitialized external linkage data object. */ #define COMMON_ASM_OP "\t.comm\t" diff --git a/gcc/config/arc/arc.cc b/gcc/config/arc/arc.cc index db81686..95d3285 100644 --- a/gcc/config/arc/arc.cc +++ b/gcc/config/arc/arc.cc @@ -4229,7 +4229,7 @@ enum arc_shift_alg { SHIFT_MOVE, /* Register-to-register move. */ SHIFT_LOOP, /* Zero-overhead loop implementation. */ - SHIFT_INLINE, /* Mmultiple LSHIFTs and LSHIFT-PLUSs. */ + SHIFT_INLINE, /* Mmultiple LSHIFTs and LSHIFT-PLUSs. */ SHIFT_AND_ROT, /* Bitwise AND, then ROTATERTs. */ SHIFT_SWAP, /* SWAP then multiple LSHIFTs/LSHIFT-PLUSs. */ SHIFT_AND_SWAP_ROT /* Bitwise AND, then SWAP, then ROTATERTs. */ diff --git a/gcc/config/arm/aout.h b/gcc/config/arm/aout.h index db9e8dd..0c32c1e 100644 --- a/gcc/config/arm/aout.h +++ b/gcc/config/arm/aout.h @@ -1,7 +1,7 @@ /* Definitions of target machine for GNU compiler, for ARM with a.out Copyright (C) 1995-2024 Free Software Foundation, Inc. Contributed by Richard Earnshaw (rearnsha@armltd.co.uk). - + This file is part of GCC. GCC is free software; you can redistribute it and/or modify it @@ -165,7 +165,7 @@ #define ASM_GENERATE_INTERNAL_LABEL(STRING, PREFIX, NUM) \ sprintf (STRING, "*%s%s%u", LOCAL_LABEL_PREFIX, PREFIX, (unsigned int)(NUM)) #endif - + /* Output an element of a dispatch table. */ #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE) \ do \ @@ -174,7 +174,7 @@ asm_fprintf (STREAM, "\t.word\t%LL%d\n", VALUE); \ } \ while (0) - + /* Thumb-2 always uses addr_diff_elf so that the Table Branch instructions can be used. For non-pic code where the offsets do not suitable for @@ -266,7 +266,7 @@ fprintf (STREAM, "\t.space\t%d\n", (int) (NBYTES)) /* Align output to a power of two. Horrible /bin/as. */ -#ifndef ASM_OUTPUT_ALIGN +#ifndef ASM_OUTPUT_ALIGN #define ASM_OUTPUT_ALIGN(STREAM, POWER) \ do \ { \ @@ -292,7 +292,7 @@ } \ while (0) #endif - + /* Output a local common block. /bin/as can't do this, so hack a `.space' into the bss segment. Note that this is *bad* practice, which is guaranteed NOT to work since it doesn't define STATIC @@ -308,7 +308,7 @@ } \ while (0) #endif - + /* Output a zero-initialized block. */ #ifndef ASM_OUTPUT_ALIGNED_BSS #define ASM_OUTPUT_ALIGNED_BSS(STREAM, DECL, NAME, SIZE, ALIGN) \ diff --git a/gcc/config/arm/arm-mve-builtins.h b/gcc/config/arm/arm-mve-builtins.h index fe7adf0..2e48d91 100644 --- a/gcc/config/arm/arm-mve-builtins.h +++ b/gcc/config/arm/arm-mve-builtins.h @@ -401,7 +401,7 @@ public: bool require_integer_immediate (unsigned int); bool require_derived_scalar_type (unsigned int, type_class_index, unsigned int = SAME_SIZE); - + bool check_num_arguments (unsigned int); bool check_gp_argument (unsigned int, unsigned int &, unsigned int &); tree resolve_unary (type_class_index = SAME_TYPE_CLASS, diff --git a/gcc/config/arm/arm.cc b/gcc/config/arm/arm.cc index 0d32b70..8ccdf1a 100644 --- a/gcc/config/arm/arm.cc +++ b/gcc/config/arm/arm.cc @@ -15367,9 +15367,9 @@ arm_block_move_unaligned_straight (rtx dstbase, rtx srcbase, HOST_WIDE_INT srcoffset, dstoffset; HOST_WIDE_INT src_autoinc, dst_autoinc; rtx mem, addr; - + gcc_assert (interleave_factor >= 1 && interleave_factor <= 4); - + /* Use hard registers if we have aligned source or destination so we can use load/store multiple with contiguous registers. */ if (dst_aligned || src_aligned) @@ -15383,7 +15383,7 @@ arm_block_move_unaligned_straight (rtx dstbase, rtx srcbase, src = copy_addr_to_reg (XEXP (srcbase, 0)); srcoffset = dstoffset = 0; - + /* Calls to arm_gen_load_multiple and arm_gen_store_multiple update SRC/DST. For copying the last bytes we want to subtract this offset again. */ src_autoinc = dst_autoinc = 0; @@ -15437,14 +15437,14 @@ arm_block_move_unaligned_straight (rtx dstbase, rtx srcbase, remaining -= block_size_bytes; } - + /* Copy any whole words left (note these aren't interleaved with any subsequent halfword/byte load/stores in the interests of simplicity). */ - + words = remaining / UNITS_PER_WORD; gcc_assert (words < interleave_factor); - + if (src_aligned && words > 1) { emit_insn (arm_gen_load_multiple (regnos, words, src, TRUE, srcbase, @@ -15490,11 +15490,11 @@ arm_block_move_unaligned_straight (rtx dstbase, rtx srcbase, } remaining -= words * UNITS_PER_WORD; - + gcc_assert (remaining < 4); - + /* Copy a halfword if necessary. */ - + if (remaining >= 2) { halfword_tmp = gen_reg_rtx (SImode); @@ -15518,11 +15518,11 @@ arm_block_move_unaligned_straight (rtx dstbase, rtx srcbase, remaining -= 2; srcoffset += 2; } - + gcc_assert (remaining < 2); - + /* Copy last byte. */ - + if ((remaining & 1) != 0) { byte_tmp = gen_reg_rtx (SImode); @@ -15543,9 +15543,9 @@ arm_block_move_unaligned_straight (rtx dstbase, rtx srcbase, remaining--; srcoffset++; } - + /* Store last halfword if we haven't done so already. */ - + if (halfword_tmp) { addr = plus_constant (Pmode, dst, dstoffset - dst_autoinc); @@ -15564,7 +15564,7 @@ arm_block_move_unaligned_straight (rtx dstbase, rtx srcbase, emit_move_insn (mem, gen_lowpart (QImode, byte_tmp)); dstoffset++; } - + gcc_assert (remaining == 0 && srcoffset == dstoffset); } @@ -15583,7 +15583,7 @@ arm_adjust_block_mem (rtx mem, HOST_WIDE_INT length, rtx *loop_reg, rtx *loop_mem) { *loop_reg = copy_addr_to_reg (XEXP (mem, 0)); - + /* Although the new mem does not refer to a known location, it does keep up to LENGTH bytes of alignment. */ *loop_mem = change_address (mem, BLKmode, *loop_reg); @@ -15603,14 +15603,14 @@ arm_block_move_unaligned_loop (rtx dest, rtx src, HOST_WIDE_INT length, { rtx src_reg, dest_reg, final_src, test; HOST_WIDE_INT leftover; - + leftover = length % bytes_per_iter; length -= leftover; - + /* Create registers and memory references for use within the loop. */ arm_adjust_block_mem (src, bytes_per_iter, &src_reg, &src); arm_adjust_block_mem (dest, bytes_per_iter, &dest_reg, &dest); - + /* Calculate the value that SRC_REG should have after the last iteration of the loop. */ final_src = expand_simple_binop (Pmode, PLUS, src_reg, GEN_INT (length), @@ -15619,7 +15619,7 @@ arm_block_move_unaligned_loop (rtx dest, rtx src, HOST_WIDE_INT length, /* Emit the start of the loop. */ rtx_code_label *label = gen_label_rtx (); emit_label (label); - + /* Emit the loop body. */ arm_block_move_unaligned_straight (dest, src, bytes_per_iter, interleave_factor); @@ -15627,11 +15627,11 @@ arm_block_move_unaligned_loop (rtx dest, rtx src, HOST_WIDE_INT length, /* Move on to the next block. */ emit_move_insn (src_reg, plus_constant (Pmode, src_reg, bytes_per_iter)); emit_move_insn (dest_reg, plus_constant (Pmode, dest_reg, bytes_per_iter)); - + /* Emit the loop condition. */ test = gen_rtx_NE (VOIDmode, src_reg, final_src); emit_jump_insn (gen_cbranchsi4 (test, src_reg, final_src, label)); - + /* Mop up any left-over bytes. */ if (leftover) arm_block_move_unaligned_straight (dest, src, leftover, interleave_factor); @@ -15645,7 +15645,7 @@ static int arm_cpymemqi_unaligned (rtx *operands) { HOST_WIDE_INT length = INTVAL (operands[2]); - + if (optimize_size) { bool src_aligned = MEM_ALIGN (operands[1]) >= BITS_PER_WORD; @@ -15656,7 +15656,7 @@ arm_cpymemqi_unaligned (rtx *operands) resulting code can be smaller. */ unsigned int interleave_factor = (src_aligned || dst_aligned) ? 2 : 1; HOST_WIDE_INT bytes_per_iter = (src_aligned || dst_aligned) ? 8 : 4; - + if (length > 12) arm_block_move_unaligned_loop (operands[0], operands[1], length, interleave_factor, bytes_per_iter); @@ -15674,7 +15674,7 @@ arm_cpymemqi_unaligned (rtx *operands) else arm_block_move_unaligned_straight (operands[0], operands[1], length, 4); } - + return 1; } @@ -31165,10 +31165,10 @@ int vfp3_const_double_for_fract_bits (rtx operand) { REAL_VALUE_TYPE r0; - + if (!CONST_DOUBLE_P (operand)) return 0; - + r0 = *CONST_DOUBLE_REAL_VALUE (operand); if (exact_real_inverse (DFmode, &r0) && !REAL_VALUE_NEGATIVE (r0)) @@ -32430,7 +32430,7 @@ arm_autoinc_modes_ok_p (machine_mode mode, enum arm_auto_incmodes code) else return false; } - + return true; case ARM_POST_DEC: @@ -32447,10 +32447,10 @@ arm_autoinc_modes_ok_p (machine_mode mode, enum arm_auto_incmodes code) return false; return true; - + default: return false; - + } return false; @@ -32461,7 +32461,7 @@ arm_autoinc_modes_ok_p (machine_mode mode, enum arm_auto_incmodes code) Additionally, the default expansion code is not available or suitable for post-reload insn splits (this can occur when the register allocator chooses not to do a shift in NEON). - + This function is used in both initial expand and post-reload splits, and handles all kinds of 64-bit shifts. @@ -33531,7 +33531,7 @@ arm_asan_shadow_offset (void) /* This is a temporary fix for PR60655. Ideally we need to handle most of these cases in the generic part but - currently we reject minus (..) (sym_ref). We try to + currently we reject minus (..) (sym_ref). We try to ameliorate the case with minus (sym_ref1) (sym_ref2) where they are in the same section. */ @@ -33854,7 +33854,7 @@ arm_valid_target_attribute_tree (tree args, struct gcc_options *opts, return build_target_option_node (opts, opts_set); } -static void +static void add_attribute (const char * mode, tree *attributes) { size_t len = strlen (mode); @@ -33885,7 +33885,7 @@ arm_insert_attributes (tree fndecl, tree * attributes) /* Nested definitions must inherit mode. */ if (current_function_decl) { - mode = TARGET_THUMB ? "thumb" : "arm"; + mode = TARGET_THUMB ? "thumb" : "arm"; add_attribute (mode, attributes); return; } diff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h index b092ba6..13a90d8 100644 --- a/gcc/config/arm/arm.h +++ b/gcc/config/arm/arm.h @@ -1426,7 +1426,7 @@ extern const char *fp_sysreg_names[NB_FP_SYSREGS]; but prevents the compiler from extending the lifetime of these registers. */ #define TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P \ - arm_small_register_classes_for_mode_p + arm_small_register_classes_for_mode_p /* Must leave BASE_REGS reloads alone */ #define THUMB_SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \ @@ -1479,7 +1479,7 @@ extern const char *fp_sysreg_names[NB_FP_SYSREGS]; /* Return the maximum number of consecutive registers needed to represent mode MODE in a register of class CLASS. - ARM regs are UNITS_PER_WORD bits. + ARM regs are UNITS_PER_WORD bits. FIXME: Is this true for iWMMX? */ #define CLASS_MAX_NREGS(CLASS, MODE) \ (CLASS == VPR_REG) \ @@ -1647,14 +1647,14 @@ machine_function; #define ARM_Q_BIT_READ (arm_q_bit_access ()) #define ARM_GE_BITS_READ (arm_ge_bits_access ()) -/* As in the machine_function, a global set of call-via labels, for code +/* As in the machine_function, a global set of call-via labels, for code that is in text_section. */ extern GTY(()) rtx thumb_call_via_label[14]; /* The number of potential ways of assigning to a co-processor. */ #define ARM_NUM_COPROC_SLOTS 1 -/* Enumeration of procedure calling standard variants. We don't really +/* Enumeration of procedure calling standard variants. We don't really support all of these yet. */ enum arm_pcs { diff --git a/gcc/config/arm/bpabi.h b/gcc/config/arm/bpabi.h index 7a279f3..2e418fa 100644 --- a/gcc/config/arm/bpabi.h +++ b/gcc/config/arm/bpabi.h @@ -1,6 +1,6 @@ /* Configuration file for ARM BPABI targets. Copyright (C) 2004-2024 Free Software Foundation, Inc. - Contributed by CodeSourcery, LLC + Contributed by CodeSourcery, LLC This file is part of GCC. diff --git a/gcc/config/arm/elf.h b/gcc/config/arm/elf.h index 97230d1..5f176de 100644 --- a/gcc/config/arm/elf.h +++ b/gcc/config/arm/elf.h @@ -3,7 +3,7 @@ Copyright (C) 1995-2024 Free Software Foundation, Inc. Contributed by Philip Blundell <philb@gnu.org> and Catherine Moore <clm@cygnus.com> - + This file is part of GCC. GCC is free software; you can redistribute it and/or modify it @@ -111,7 +111,7 @@ #ifndef LINK_SPEC #define LINK_SPEC "%{mbig-endian:-EB} %{mlittle-endian:-EL} -X" #endif - + /* Run-time Target Specification. */ #ifndef TARGET_DEFAULT #define TARGET_DEFAULT (MASK_APCS_FRAME) diff --git a/gcc/config/arm/linux-eabi.h b/gcc/config/arm/linux-eabi.h index eef791f..50b753d 100644 --- a/gcc/config/arm/linux-eabi.h +++ b/gcc/config/arm/linux-eabi.h @@ -1,6 +1,6 @@ /* Configuration file for ARM GNU/Linux EABI targets. Copyright (C) 2004-2024 Free Software Foundation, Inc. - Contributed by CodeSourcery, LLC + Contributed by CodeSourcery, LLC This file is part of GCC. diff --git a/gcc/config/arm/symbian.h b/gcc/config/arm/symbian.h index 6431d61..4bfe9c8 100644 --- a/gcc/config/arm/symbian.h +++ b/gcc/config/arm/symbian.h @@ -1,6 +1,6 @@ /* Configuration file for Symbian OS on ARM processors. Copyright (C) 2004-2024 Free Software Foundation, Inc. - Contributed by CodeSourcery, LLC + Contributed by CodeSourcery, LLC This file is part of GCC. @@ -29,7 +29,7 @@ Make all symbols hidden by default. Symbian OS expects that all exported symbols will be explicitly marked with - "__declspec(dllexport)". + "__declspec(dllexport)". Enumeration types use 4 bytes, even if the enumerals are small, unless explicitly overridden. @@ -63,7 +63,7 @@ #undef SUBTARGET_ASM_FLOAT_SPEC #define SUBTARGET_ASM_FLOAT_SPEC \ "%{!mfpu=*:-mfpu=vfp} %{!mcpu=*:%{!march=*:-march=armv5t}}" - + /* Define the __symbian__ macro. */ #undef TARGET_OS_CPP_BUILTINS #define TARGET_OS_CPP_BUILTINS() \ diff --git a/gcc/config/arm/unknown-elf.h b/gcc/config/arm/unknown-elf.h index 6b31304..b1a1764 100644 --- a/gcc/config/arm/unknown-elf.h +++ b/gcc/config/arm/unknown-elf.h @@ -91,6 +91,6 @@ /* The libgcc udivmod functions may throw exceptions. If newlib is configured to support long longs in I/O, then printf will depend on udivmoddi4, which will depend on the exception unwind routines, - which will depend on abort, which is defined in libc. */ + which will depend on abort, which is defined in libc. */ #undef LINK_GCC_C_SEQUENCE_SPEC #define LINK_GCC_C_SEQUENCE_SPEC "--start-group %G %{!nolibc:%L} --end-group" diff --git a/gcc/config/arm/vxworks.h b/gcc/config/arm/vxworks.h index 7765d92..bafc650 100644 --- a/gcc/config/arm/vxworks.h +++ b/gcc/config/arm/vxworks.h @@ -1,10 +1,10 @@ /* Definitions of target machine for GCC, - for ARM with targeting the VXWorks run time environment. + for ARM with targeting the VXWorks run time environment. Copyright (C) 1999-2024 Free Software Foundation, Inc. Contributed by: Mike Stump <mrs@wrs.com> Brought up to date by CodeSourcery, LLC. - + This file is part of GCC. GCC is free software; you can redistribute it and/or modify diff --git a/gcc/config/avr/avr-arch.h b/gcc/config/avr/avr-arch.h index e7c02eb..072e44d 100644 --- a/gcc/config/avr/avr-arch.h +++ b/gcc/config/avr/avr-arch.h @@ -13,7 +13,7 @@ GCC is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. - + You should have received a copy of the GNU General Public License along with GCC; see the file COPYING3. If not see <http://www.gnu.org/licenses/>. */ diff --git a/gcc/config/avr/avr-c.cc b/gcc/config/avr/avr-c.cc index 81c91c3..d3c40d7 100644 --- a/gcc/config/avr/avr-c.cc +++ b/gcc/config/avr/avr-c.cc @@ -8,12 +8,12 @@ it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 3, or (at your option) any later version. - + GCC is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. - + You should have received a copy of the GNU General Public License along with GCC; see the file COPYING3. If not see <http://www.gnu.org/licenses/>. */ diff --git a/gcc/config/avr/avr-devices.cc b/gcc/config/avr/avr-devices.cc index 83b4a2e..9bb55dc 100644 --- a/gcc/config/avr/avr-devices.cc +++ b/gcc/config/avr/avr-devices.cc @@ -7,12 +7,12 @@ it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 3, or (at your option) any later version. - + GCC is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. - + You should have received a copy of the GNU General Public License along with GCC; see the file COPYING3. If not see <http://www.gnu.org/licenses/>. */ diff --git a/gcc/config/avr/avr-log.cc b/gcc/config/avr/avr-log.cc index 5aacab1..5708ac3 100644 --- a/gcc/config/avr/avr-log.cc +++ b/gcc/config/avr/avr-log.cc @@ -8,12 +8,12 @@ it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 3, or (at your option) any later version. - + GCC is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. - + You should have received a copy of the GNU General Public License along with GCC; see the file COPYING3. If not see <http://www.gnu.org/licenses/>. */ diff --git a/gcc/config/avr/avr.cc b/gcc/config/avr/avr.cc index b69a9c2..f62ea8a 100644 --- a/gcc/config/avr/avr.cc +++ b/gcc/config/avr/avr.cc @@ -8,12 +8,12 @@ it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 3, or (at your option) any later version. - + GCC is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. - + You should have received a copy of the GNU General Public License along with GCC; see the file COPYING3. If not see <http://www.gnu.org/licenses/>. */ diff --git a/gcc/config/avr/avr.h b/gcc/config/avr/avr.h index 3fa2ee7..3ef1897 100644 --- a/gcc/config/avr/avr.h +++ b/gcc/config/avr/avr.h @@ -326,7 +326,7 @@ enum reg_class { #define RETURN_ADDR_RTX(count, tem) avr_return_addr_rtx (count, tem) -/* Don't use Push rounding. expr.cc: emit_single_push_insn is broken +/* Don't use Push rounding. expr.cc: emit_single_push_insn is broken for POST_DEC targets (PR27386). */ /*#define PUSH_ROUNDING(NPUSHED) (NPUSHED)*/ @@ -485,7 +485,7 @@ typedef struct avr_args /* Set MOVE_RATIO to 3 to allow memory moves upto 4 bytes to happen by pieces when optimizing for speed, like it did when MOVE_MAX_PIECES - was 4. When optimizing for size, allow memory moves upto 2 bytes. + was 4. When optimizing for size, allow memory moves upto 2 bytes. Also see avr_use_by_pieces_infrastructure_p. */ #define MOVE_RATIO(speed) ((speed) ? 3 : 2) @@ -568,19 +568,19 @@ struct GTY(()) machine_function -1 when "signal" attribute(s) with arguments are present but none without argument. */ int is_signal; - + /* 'true' - if current function is a non-blocking interrupt service routine as specified by the "isr_noblock" attribute. */ int is_noblock; - /* 'true' - if current function is a 'task' function + /* 'true' - if current function is a 'task' function as specified by the "OS_task" attribute. */ int is_OS_task; - /* 'true' - if current function is a 'main' function + /* 'true' - if current function is a 'main' function as specified by the "OS_main" attribute. */ int is_OS_main; - + /* Current function stack size. */ int stack_usage; diff --git a/gcc/config/avr/elf.h b/gcc/config/avr/elf.h index 794f4c9..1e769f6 100644 --- a/gcc/config/avr/elf.h +++ b/gcc/config/avr/elf.h @@ -8,12 +8,12 @@ it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 3, or (at your option) any later version. - + GCC is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. - + You should have received a copy of the GNU General Public License along with GCC; see the file COPYING3. If not see <http://www.gnu.org/licenses/>. */ diff --git a/gcc/config/avr/gen-avr-mmcu-specs.cc b/gcc/config/avr/gen-avr-mmcu-specs.cc index af519c9..4bdc0c2 100644 --- a/gcc/config/avr/gen-avr-mmcu-specs.cc +++ b/gcc/config/avr/gen-avr-mmcu-specs.cc @@ -8,12 +8,12 @@ it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 3, or (at your option) any later version. - + GCC is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. - + You should have received a copy of the GNU General Public License along with GCC; see the file COPYING3. If not see <http://www.gnu.org/licenses/>. */ diff --git a/gcc/config/avr/gen-avr-mmcu-texi.cc b/gcc/config/avr/gen-avr-mmcu-texi.cc index 597ba22..df2620f 100644 --- a/gcc/config/avr/gen-avr-mmcu-texi.cc +++ b/gcc/config/avr/gen-avr-mmcu-texi.cc @@ -8,12 +8,12 @@ it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 3, or (at your option) any later version. - + GCC is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. - + You should have received a copy of the GNU General Public License along with GCC; see the file COPYING3. If not see <http://www.gnu.org/licenses/>. */ diff --git a/gcc/config/avr/stdfix.h b/gcc/config/avr/stdfix.h index e130a26..9a594f9 100644 --- a/gcc/config/avr/stdfix.h +++ b/gcc/config/avr/stdfix.h @@ -108,12 +108,12 @@ typedef long long unsigned int uint_uk_t; /* The Embedded-C paper specifies results only for rounding points 0 < RP < FBIT - + As an extension, the following functions work as expected with rounding points -IBIT < RP < FBIT - + For example, rounding an accum with a rounding point of -1 will result in an even integer value. */ diff --git a/gcc/config/bfin/bfin-protos.h b/gcc/config/bfin/bfin-protos.h index bd49329..053fc4a 100644 --- a/gcc/config/bfin/bfin-protos.h +++ b/gcc/config/bfin/bfin-protos.h @@ -71,7 +71,7 @@ extern char *bfin_asm_long (void); extern char *bfin_asm_short (void); extern int log2constp (unsigned HOST_WIDE_INT); -extern void init_cumulative_args (CUMULATIVE_ARGS *, tree, rtx); +extern void init_cumulative_args (CUMULATIVE_ARGS *, tree, rtx); extern HOST_WIDE_INT bfin_initial_elimination_offset (int, int); extern int effective_address_32bit_p (rtx, machine_mode); diff --git a/gcc/config/bfin/bfin.cc b/gcc/config/bfin/bfin.cc index 3e40f2c..13d2e10 100644 --- a/gcc/config/bfin/bfin.cc +++ b/gcc/config/bfin/bfin.cc @@ -97,14 +97,14 @@ bfin_globalize_label (FILE *stream, const char *name) fputc ('\n',stream); } -static void -output_file_start (void) +static void +output_file_start (void) { FILE *file = asm_out_file; int i; fprintf (file, ".file \"%s\";\n", LOCATION_FILE (input_location)); - + for (i = 0; arg_regs[i] >= 0; i++) ; max_arg_registers = i; /* how many arg reg used */ @@ -417,7 +417,7 @@ expand_prologue_reg_save (rtx spreg, int saveall, bool is_inthandler) } } for (i = REG_P7 + 1; i < REG_CC; i++) - if (saveall + if (saveall || (is_inthandler && (df_regs_ever_live_p (i) || (!leaf_function_p () && call_used_or_fixed_reg_p (i))))) @@ -548,7 +548,7 @@ expand_epilogue_reg_restore (rtx spreg, bool saveall, bool is_inthandler) it. Normally, this macro will push all remaining incoming registers on the - stack and set PRETEND_SIZE to the length of the registers pushed. + stack and set PRETEND_SIZE to the length of the registers pushed. Blackfin specific : - VDSP C compiler manual (our ABI) says that a variable args function @@ -590,7 +590,7 @@ setup_incoming_varargs (cumulative_args_t cum, be accessed via the stack pointer) in functions that seem suitable. */ static bool -bfin_frame_pointer_required (void) +bfin_frame_pointer_required (void) { e_funkind fkind = funkind (TREE_TYPE (current_function_decl)); @@ -906,7 +906,7 @@ do_unlink (rtx spreg, HOST_WIDE_INT frame_size, bool all, int epilogue_p) if (stack_frame_needed_p ()) emit_insn (gen_unlink ()); - else + else { rtx postinc = gen_rtx_MEM (Pmode, gen_rtx_POST_INC (Pmode, spreg)); @@ -968,7 +968,7 @@ expand_interrupt_handler_prologue (rtx spreg, e_funkind fkind, bool all) emit_insn (gen_movsi_low (p5reg, p5reg, chipid)); emit_insn (gen_dummy_load (p5reg, bfin_cc_rtx)); } - + if (lookup_attribute ("nesting", attrs)) { rtx srcreg = gen_rtx_REG (Pmode, ret_regs[fkind]); @@ -1046,7 +1046,7 @@ bfin_load_pic_reg (rtx dest) pic reg, since the caller always passes a usable one. */ if (local_info_node && local_info_node->local) return pic_offset_table_rtx; - + if (OPTION_SET_P (bfin_library_id)) addr = plus_constant (Pmode, pic_offset_table_rtx, -4 - bfin_library_id * 4); @@ -1236,7 +1236,7 @@ bfin_delegitimize_address (rtx orig_x) 32-bit instruction. */ int -effective_address_32bit_p (rtx op, machine_mode mode) +effective_address_32bit_p (rtx op, machine_mode mode) { HOST_WIDE_INT offset; @@ -1312,7 +1312,7 @@ print_address_operand (FILE *file, rtx x) case PRE_DEC: fprintf (file, "--"); - output_address (VOIDmode, XEXP (x, 0)); + output_address (VOIDmode, XEXP (x, 0)); break; case POST_INC: output_address (VOIDmode, XEXP (x, 0)); @@ -1390,7 +1390,7 @@ print_operand (FILE *file, rtx x, char code) output_operand_lossage ("invalid %%j value"); } break; - + case 'J': /* reverse logic */ switch (GET_CODE(x)) { @@ -1491,7 +1491,7 @@ print_operand (FILE *file, rtx x, char code) else output_operand_lossage ("invalid operand for code '%c'", code); } - else + else fprintf (file, "%s", reg_names[REGNO (x)]); break; @@ -1620,7 +1620,7 @@ print_operand (FILE *file, rtx x, char code) /* Initialize a variable CUM of type CUMULATIVE_ARGS for a call to a function whose data type is FNTYPE. - For a library call, FNTYPE is 0. + For a library call, FNTYPE is 0. VDSP C Compiler manual, our ABI says that first 3 words of arguments will use R0, R1 and R2. */ @@ -1718,7 +1718,7 @@ bfin_arg_partial_bytes (cumulative_args_t cum, const function_arg_info &arg) { int bytes = arg.promoted_size_in_bytes (); int bytes_left = get_cumulative_args (cum)->nregs * UNITS_PER_WORD; - + if (bytes == -1) return 0; @@ -1759,7 +1759,7 @@ bfin_struct_value_rtx (tree fntype ATTRIBUTE_UNUSED, /* Return true when register may be used to pass function parameters. */ -bool +bool function_arg_regno_p (int n) { int i; @@ -2701,7 +2701,7 @@ bfin_valid_reg_p (unsigned int regno, int strict, machine_mode mode, /* Recognize an RTL expression that is a valid memory address for an instruction. The MODE argument is the machine mode for the MEM expression - that wants to use this address. + that wants to use this address. Blackfin addressing modes are as follows: @@ -2710,7 +2710,7 @@ bfin_valid_reg_p (unsigned int regno, int strict, machine_mode mode, B [ Preg + uimm15 ] W [ Preg + uimm16m2 ] - [ Preg + uimm17m4 ] + [ Preg + uimm17m4 ] [preg++] [preg--] @@ -2888,8 +2888,8 @@ bfin_rtx_costs (rtx x, machine_mode mode, int outer_code_i, int opno, else *total = cost2; return true; - - case ASHIFT: + + case ASHIFT: case ASHIFTRT: case LSHIFTRT: if (mode == DImode) @@ -2904,7 +2904,7 @@ bfin_rtx_costs (rtx x, machine_mode mode, int outer_code_i, int opno, *total += rtx_cost (op0, mode, code, 0, speed); return true; - + case IOR: case AND: case XOR: @@ -3152,11 +3152,11 @@ output_push_multiple (rtx insn, rtx *operands) { char buf[80]; int ok; - + /* Validate the insn again, and compute first_[dp]reg_to_save. */ ok = analyze_push_multiple_operation (PATTERN (insn)); gcc_assert (ok); - + if (first_dreg_to_save == 8) sprintf (buf, "[--sp] = ( p5:%d );\n", first_preg_to_save); else if (first_preg_to_save == 6) @@ -3176,7 +3176,7 @@ output_pop_multiple (rtx insn, rtx *operands) { char buf[80]; int ok; - + /* Validate the insn again, and compute first_[dp]reg_to_save. */ ok = analyze_pop_multiple_operation (PATTERN (insn)); gcc_assert (ok); @@ -3856,7 +3856,7 @@ static void hwloop_fail (hwloop_info loop) { rtx insn = loop->loop_end; - + if (DPREG_P (loop->iter_reg)) { /* If loop->iter_reg is a DREG or PREG, we can split it here @@ -3880,7 +3880,7 @@ hwloop_fail (hwloop_info loop) } else { - splitting_loops = 1; + splitting_loops = 1; try_split (PATTERN (insn), safe_as_a <rtx_insn *> (insn), 1); splitting_loops = 0; } @@ -4132,7 +4132,7 @@ workaround_rts_anomaly (void) if (BARRIER_P (insn)) return; - + if (NOTE_P (insn) || LABEL_P (insn)) continue; @@ -4286,7 +4286,7 @@ indirect_call_p (rtx pat) pat = XEXP (pat, 0); gcc_assert (GET_CODE (pat) == MEM); pat = XEXP (pat, 0); - + return REG_P (pat); } @@ -4329,7 +4329,7 @@ workaround_speculation (void) int delay_needed = 0; next = find_next_insn_start (insn); - + if (NOTE_P (insn) || BARRIER_P (insn)) continue; if (JUMP_TABLE_DATA_P (insn)) @@ -4344,7 +4344,7 @@ workaround_speculation (void) pat = PATTERN (insn); if (GET_CODE (pat) == USE || GET_CODE (pat) == CLOBBER) continue; - + if (GET_CODE (pat) == ASM_INPUT || asm_noperands (pat) >= 0) { np_check_regno = -1; @@ -4603,7 +4603,7 @@ add_sched_insns_for_speculation (void) if (GET_CODE (PATTERN (next)) == UNSPEC_VOLATILE && get_attr_type (next) == TYPE_STALL) continue; - emit_insn_before (gen_stall (GEN_INT (1)), next); + emit_insn_before (gen_stall (GEN_INT (1)), next); } } } @@ -4719,7 +4719,7 @@ bfin_comp_type_attributes (const_tree type1, const_tree type2) if (kind1 != kind2) return 0; - + /* Check for mismatched modifiers */ if (!lookup_attribute ("nesting", TYPE_ATTRIBUTES (type1)) != !lookup_attribute ("nesting", TYPE_ATTRIBUTES (type2))) @@ -4744,9 +4744,9 @@ bfin_comp_type_attributes (const_tree type1, const_tree type2) struct attribute_spec.handler. */ static tree -bfin_handle_longcall_attribute (tree *node, tree name, - tree args ATTRIBUTE_UNUSED, - int flags ATTRIBUTE_UNUSED, +bfin_handle_longcall_attribute (tree *node, tree name, + tree args ATTRIBUTE_UNUSED, + int flags ATTRIBUTE_UNUSED, bool *no_add_attrs) { if (TREE_CODE (*node) != FUNCTION_TYPE @@ -5154,7 +5154,7 @@ bfin_init_builtins (void) = build_function_type_list (integer_type_node, build_pointer_type (integer_type_node), NULL_TREE); - + /* Add the remaining MMX insns with somewhat more complicated types. */ def_builtin ("__builtin_bfin_csync", void_ftype_void, BFIN_BUILTIN_CSYNC); def_builtin ("__builtin_bfin_ssync", void_ftype_void, BFIN_BUILTIN_SSYNC); @@ -5746,7 +5746,7 @@ bfin_conditional_register_usage (void) #define TARGET_EXPAND_BUILTIN bfin_expand_builtin #undef TARGET_ASM_GLOBALIZE_LABEL -#define TARGET_ASM_GLOBALIZE_LABEL bfin_globalize_label +#define TARGET_ASM_GLOBALIZE_LABEL bfin_globalize_label #undef TARGET_ASM_FILE_START #define TARGET_ASM_FILE_START output_file_start diff --git a/gcc/config/bfin/bfin.h b/gcc/config/bfin/bfin.h index e957c31..ef0ba70 100644 --- a/gcc/config/bfin/bfin.h +++ b/gcc/config/bfin/bfin.h @@ -295,10 +295,10 @@ extern const char *bfin_library_id_string; /* Define this if the above stack space is to be considered part of the * space allocated by the caller. */ #define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE) 1 - + /* Define this if the maximum size of all the outgoing args is to be accumulated and pushed during the prologue. The amount can be - found in the variable crtl->outgoing_args_size. */ + found in the variable crtl->outgoing_args_size. */ #define ACCUMULATE_OUTGOING_ARGS 1 /*#define DATA_ALIGNMENT(TYPE, BASIC-ALIGN) for arrays.. */ @@ -876,11 +876,11 @@ typedef struct { #define DEFAULT_SIGNED_CHAR 1 /* FLOAT_TYPE_SIZE get poisoned, so add BFIN_ prefix. */ #define BFIN_FLOAT_TYPE_SIZE BITS_PER_WORD -#define SHORT_TYPE_SIZE 16 +#define SHORT_TYPE_SIZE 16 #define CHAR_TYPE_SIZE 8 #define INT_TYPE_SIZE 32 #define LONG_TYPE_SIZE 32 -#define LONG_LONG_TYPE_SIZE 64 +#define LONG_LONG_TYPE_SIZE 64 /* Note: Fix this to depend on target switch. -- lev */ @@ -943,7 +943,7 @@ typedef struct { #define JUMP_TABLES_IN_TEXT_SECTION flag_pic /* Define if operations between registers always perform the operation - on the full register even if a narrower mode is specified. + on the full register even if a narrower mode is specified. #define WORD_REGISTER_OPERATIONS 1 */ @@ -1095,7 +1095,7 @@ extern rtx bfin_cc_rtx, bfin_rets_rtx; #define SET_ASM_OP ".set " /* Debugger register number for a given compiler register number */ -#define DEBUGGER_REGNO(REGNO) (REGNO) +#define DEBUGGER_REGNO(REGNO) (REGNO) #define SIZE_ASM_OP "\t.size\t" diff --git a/gcc/config/c6x/c6x.cc b/gcc/config/c6x/c6x.cc index 4ea3a1e..20a1666 100644 --- a/gcc/config/c6x/c6x.cc +++ b/gcc/config/c6x/c6x.cc @@ -6398,7 +6398,7 @@ c6x_init_builtins (void) tree v2si_ftype_v2hi_v2hi = build_function_type_list (V2SI_type_node, V2HI_type_node, V2HI_type_node, NULL_TREE); - + def_builtin ("__builtin_c6x_sadd", int_ftype_int_int, C6X_BUILTIN_SADD); def_builtin ("__builtin_c6x_ssub", int_ftype_int_int, diff --git a/gcc/config/cris/cris.cc b/gcc/config/cris/cris.cc index 617fc0a..8173f85 100644 --- a/gcc/config/cris/cris.cc +++ b/gcc/config/cris/cris.cc @@ -2279,7 +2279,7 @@ cris_side_effect_mode_ok (enum rtx_code code, rtx *ops, /* Queue an .ident string in the queue of top-level asm statements. If the front-end is done, we must be being called from toplev.cc. In that case, do nothing. */ -void +void cris_asm_output_ident (const char *string) { if (symtab->state != PARSING) @@ -3597,7 +3597,7 @@ cris_promote_function_mode (const_tree type ATTRIBUTE_UNUSED, if (for_return == 1) return mode; return CRIS_PROMOTED_MODE (mode, *punsignedp, type); -} +} /* Atomic types require alignment to be at least their "natural" size. */ diff --git a/gcc/config/darwin-c.cc b/gcc/config/darwin-c.cc index aaec1c3..69f3d0a 100644 --- a/gcc/config/darwin-c.cc +++ b/gcc/config/darwin-c.cc @@ -733,7 +733,7 @@ darwin_cpp_builtins (cpp_reader *pfile) /* Since we do not (at 4.6) support ObjC gc for the NeXT runtime, the following will cause a syntax error if one tries to compile gc attributed - items. However, without this, NeXT system headers cannot be parsed + items. However, without this, NeXT system headers cannot be parsed properly (on systems >= darwin 9). */ if (flag_objc_gc) { @@ -805,24 +805,24 @@ darwin_cfstring_ref_p (const_tree strp) return false; tn = TYPE_NAME (strp); - if (tn) + if (tn) tn = DECL_NAME (tn); - return (tn + return (tn && IDENTIFIER_POINTER (tn) && startswith (IDENTIFIER_POINTER (tn), "CFStringRef")); } /* At present the behavior of this is undefined and it does nothing. */ static void -darwin_check_cfstring_format_arg (tree ARG_UNUSED (format_arg), +darwin_check_cfstring_format_arg (tree ARG_UNUSED (format_arg), tree ARG_UNUSED (args_list)) { } /* The extra format types we recognize. */ EXPORTED_CONST format_kind_info darwin_additional_format_types[] = { - { "CFString", NULL, NULL, NULL, NULL, - NULL, NULL, + { "CFString", NULL, NULL, NULL, NULL, + NULL, NULL, FMT_FLAG_ARG_CONVERT|FMT_FLAG_PARSE_ARG_CONVERT_EXTERNAL, 0, 0, 0, 0, 0, 0, NULL, NULL } diff --git a/gcc/config/darwin-driver.cc b/gcc/config/darwin-driver.cc index 546ca24..2aa0b0c 100644 --- a/gcc/config/darwin-driver.cc +++ b/gcc/config/darwin-driver.cc @@ -191,8 +191,8 @@ darwin_find_version_from_kernel (void) /* When running on a Darwin system and using that system's headers and libraries, default the -mmacosx-version-min flag to be the version - of the system on which the compiler is running. - + of the system on which the compiler is running. + When building cross or native cross compilers, default to the OSX version of the target (as provided by the most specific target header included in tm.h). This may be overidden by setting the flag explicitly @@ -287,7 +287,7 @@ darwin_driver_init (unsigned int *decoded_options_count, case OPT_arch: /* Support provision of a single -arch xxxx flag as a means of specifying the sub-target/multi-lib. Translate this into -m32/64 - as appropriate. */ + as appropriate. */ if (!strcmp ((*decoded_options)[i].arg, "i386")) seenX86 = true; else if (!strcmp ((*decoded_options)[i].arg, "x86_64")) @@ -307,7 +307,7 @@ darwin_driver_init (unsigned int *decoded_options_count, * sizeof (struct cl_decoded_option))); } --i; - --*decoded_options_count; + --*decoded_options_count; break; case OPT_m32: @@ -384,7 +384,7 @@ darwin_driver_init (unsigned int *decoded_options_count, " (%<-m32%> ignored)"); if (! seenM64) /* Add -m64 if the User didn't. */ appendM64 = true; - } + } #elif DARWIN_PPC if (seenX86 || seenX86_64) warning (0, "this compiler does not support x86" diff --git a/gcc/config/darwin-protos.h b/gcc/config/darwin-protos.h index b67e052..523d7db 100644 --- a/gcc/config/darwin-protos.h +++ b/gcc/config/darwin-protos.h @@ -59,7 +59,7 @@ extern void darwin_set_default_type_attributes (tree); extern int machopic_reloc_rw_mask (void); extern section *machopic_select_section (tree, int, unsigned HOST_WIDE_INT); -extern section *darwin_function_section (tree, enum node_frequency, bool, bool); +extern section *darwin_function_section (tree, enum node_frequency, bool, bool); extern section *darwin_tm_clone_table_section (void); extern void darwin_function_switched_text_sections (FILE *, tree, bool); @@ -105,11 +105,11 @@ extern void darwin_asm_declare_constant_name (FILE *, const char *, extern void darwin_output_aligned_bss (FILE *, tree, const char *, unsigned HOST_WIDE_INT, unsigned int); -extern void darwin_asm_output_aligned_decl_local (FILE *, tree, const char *, - unsigned HOST_WIDE_INT, +extern void darwin_asm_output_aligned_decl_local (FILE *, tree, const char *, + unsigned HOST_WIDE_INT, unsigned int); extern void darwin_asm_output_aligned_decl_common (FILE *, tree, const char *, - unsigned HOST_WIDE_INT, + unsigned HOST_WIDE_INT, unsigned int); extern bool darwin_binds_local_p (const_tree); diff --git a/gcc/config/darwin.h b/gcc/config/darwin.h index 0d8886c..d2a8061 100644 --- a/gcc/config/darwin.h +++ b/gcc/config/darwin.h @@ -852,7 +852,7 @@ ASM_OPTIONS ASM_MMACOSX_VERSION_MIN_SPEC #define TARGET_ASM_DECLARE_CONSTANT_NAME darwin_asm_declare_constant_name /* Wrap new method names in quotes so the assembler doesn't gag. - Make Objective-C internal symbols local and in doing this, we need + Make Objective-C internal symbols local and in doing this, we need to accommodate the name mangling done by c++ on file scope locals. */ int darwin_label_is_anonymous_local_objc_name (const char *name); @@ -1209,7 +1209,7 @@ void add_framework_path (char *); #undef GTM_SELF_SPECS #define GTM_SELF_SPECS "" -/* Darwin disables section anchors by default. +/* Darwin disables section anchors by default. They should be enabled per arch where support exists in that arch. */ #define TARGET_ASM_OUTPUT_ANCHOR NULL #define DARWIN_SECTION_ANCHORS 0 @@ -1240,7 +1240,7 @@ extern void darwin_driver_init (unsigned int *,struct cl_decoded_option **); #undef STACK_CHECK_STATIC_BUILTIN #define STACK_CHECK_STATIC_BUILTIN 1 -/* When building cross-compilers (and native crosses) we shall default to +/* When building cross-compilers (and native crosses) we shall default to providing an osx-version-min of this unless overridden by the User. 10.5 is the only version that fully supports all our archs so that's the fall-back default. */ diff --git a/gcc/config/elfos.h b/gcc/config/elfos.h index 1338815..ea56a5c 100644 --- a/gcc/config/elfos.h +++ b/gcc/config/elfos.h @@ -43,10 +43,10 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see #undef USER_LABEL_PREFIX #define USER_LABEL_PREFIX "" -/* The biggest alignment supported by ELF in bits. 32-bit ELF - supports section alignment up to (0x80000000 * 8), while - 64-bit ELF supports (0x8000000000000000 * 8). If this macro - is not defined, the default is the largest alignment supported +/* The biggest alignment supported by ELF in bits. 32-bit ELF + supports section alignment up to (0x80000000 * 8), while + 64-bit ELF supports (0x8000000000000000 * 8). If this macro + is not defined, the default is the largest alignment supported by 32-bit ELF and representable on a 32-bit host. Use this macro to limit the alignment which can be specified using the `__attribute__ ((aligned (N)))' construct. */ diff --git a/gcc/config/epiphany/epiphany.cc b/gcc/config/epiphany/epiphany.cc index 79254c2..56e7cf9 100644 --- a/gcc/config/epiphany/epiphany.cc +++ b/gcc/config/epiphany/epiphany.cc @@ -830,7 +830,7 @@ epiphany_rtx_costs (rtx x, machine_mode mode, int outer_code, return false; } - + case SET: { rtx src = SET_SRC (x); diff --git a/gcc/config/fr30/fr30.cc b/gcc/config/fr30/fr30.cc index cf93cba..f45e8fc 100644 --- a/gcc/config/fr30/fr30.cc +++ b/gcc/config/fr30/fr30.cc @@ -18,7 +18,7 @@ along with GCC; see the file COPYING3. If not see <http://www.gnu.org/licenses/>. */ -/*{{{ Includes */ +/*{{{ Includes */ #define IN_TARGET_CODE 1 @@ -45,13 +45,13 @@ #include "target-def.h" /*}}}*/ -/*{{{ Function Prologues & Epilogues */ +/*{{{ Function Prologues & Epilogues */ /* The FR30 stack looks like this: Before call After call FP ->| | | | - +-----------------------+ +-----------------------+ high + +-----------------------+ +-----------------------+ high | | | | memory | local variables, | | local variables, | | reg save area, etc. | | reg save area, etc. | @@ -63,32 +63,32 @@ SP ->| do not fit in regs | | | +-----------------------+ +-----------------------+ | args that used to be | \ - | in regs; only created | | pretend_size - AP-> | for vararg funcs | / - +-----------------------+ - | | \ + | in regs; only created | | pretend_size + AP-> | for vararg funcs | / + +-----------------------+ + | | \ | register save area | | | | | +-----------------------+ | reg_size - | return address | | + | return address | | +-----------------------+ | FP ->| previous frame ptr | / - +-----------------------+ - | | \ - | local variables | | var_size - | | / - +-----------------------+ - | | \ + +-----------------------+ + | | \ + | local variables | | var_size + | | / + +-----------------------+ + | | \ low | room for args to | | - memory | other funcs called | | args_size + memory | other funcs called | | args_size | from this one | | - SP ->| | / - +-----------------------+ - + SP ->| | / + +-----------------------+ + Note, AP is a fake hard register. It will be eliminated in favor of SP or FP as appropriate. - Note, Some or all of the stack sections above may be omitted if they + Note, Some or all of the stack sections above may be omitted if they are not needed. */ /* Structure to be filled in by fr30_compute_frame_size() with register @@ -211,7 +211,7 @@ fr30_can_eliminate (const int from ATTRIBUTE_UNUSED, const int to) } /* Returns the number of bytes offset between FROM_REG and TO_REG - for the current function. As a side effect it fills in the + for the current function. As a side effect it fills in the current_frame_info structure, if the data is available. */ unsigned int fr30_compute_frame_size (int from_reg, int to_reg) @@ -259,10 +259,10 @@ fr30_compute_frame_size (int from_reg, int to_reg) /* Calculate the required distance. */ return_value = 0; - + if (to_reg == STACK_POINTER_REGNUM) return_value += args_size + var_size; - + if (from_reg == ARG_POINTER_REGNUM) return_value += reg_size; @@ -292,7 +292,7 @@ fr30_expand_prologue (void) if (current_frame_info.pretend_size) { int regs_to_save = current_frame_info.pretend_size / UNITS_PER_WORD; - + /* Push argument registers into the pretend arg area. */ for (regno = FIRST_ARG_REGNUM + FR30_NUM_ARG_REGS; regno --, regs_to_save --;) { @@ -317,7 +317,7 @@ fr30_expand_prologue (void) /* Save return address if necessary. */ if (current_frame_info.save_rp) { - insn = emit_insn (gen_movsi_push (gen_rtx_REG (Pmode, + insn = emit_insn (gen_movsi_push (gen_rtx_REG (Pmode, RETURN_POINTER_REGNUM))); RTX_FRAME_RELATED_P (insn) = 1; } @@ -329,12 +329,12 @@ fr30_expand_prologue (void) { int enter_size = current_frame_info.frame_size + UNITS_PER_WORD; rtx pattern; - + insn = emit_insn (gen_enter_func (GEN_INT (enter_size))); RTX_FRAME_RELATED_P (insn) = 1; - + pattern = PATTERN (insn); - + /* Also mark all 3 subexpressions as RTX_FRAME_RELATED_P. */ if (GET_CODE (pattern) == PARALLEL) { @@ -342,7 +342,7 @@ fr30_expand_prologue (void) for (x = XVECLEN (pattern, 0); x--;) { rtx part = XVECEXP (pattern, 0, x); - + /* One of the insns in the ENTER pattern updates the frame pointer. If we do not actually need the frame pointer in this function then this is a side effect @@ -410,7 +410,7 @@ fr30_expand_epilogue (void) /* Perform the inversion operations of the prologue. */ gcc_assert (current_frame_info.initialised); - + /* Pop local variables and arguments off the stack. If frame_pointer_needed is TRUE then the frame pointer register has actually been used as a frame pointer, and we can recover @@ -433,18 +433,18 @@ fr30_expand_epilogue (void) emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, tmp)); } } - + if (current_frame_info.save_fp) emit_insn (gen_movsi_pop (frame_pointer_rtx)); - + /* Pop all the registers that were pushed. */ if (current_frame_info.save_rp) emit_insn (gen_movsi_pop (gen_rtx_REG (Pmode, RETURN_POINTER_REGNUM))); - + for (regno = 0; regno < STACK_POINTER_REGNUM; regno ++) if (current_frame_info.gmask & (1 << regno)) emit_insn (gen_movsi_pop (gen_rtx_REG (Pmode, regno))); - + if (current_frame_info.pretend_size) emit_insn (gen_add_to_stack (GEN_INT (current_frame_info.pretend_size))); @@ -494,7 +494,7 @@ fr30_setup_incoming_varargs (cumulative_args_t arg_regs_used_so_far_v, } /*}}}*/ -/*{{{ Printing operands */ +/*{{{ Printing operands */ /* Print a memory address as an operand to reference that memory location. */ @@ -506,7 +506,7 @@ fr30_print_operand_address (FILE *stream, rtx address) case SYMBOL_REF: output_addr_const (stream, address); break; - + default: fprintf (stderr, "code = %x\n", GET_CODE (address)); debug_rtx (address); @@ -521,7 +521,7 @@ void fr30_print_operand (FILE *file, rtx x, int code) { rtx x0; - + switch (code) { case '#': @@ -529,7 +529,7 @@ fr30_print_operand (FILE *file, rtx x, int code) if (dbr_sequence_length () != 0) fputs (":D", file); return; - + case 'p': /* Compute the register name of the second register in a hi/lo register pair. */ @@ -538,7 +538,7 @@ fr30_print_operand (FILE *file, rtx x, int code) else fprintf (file, "r%d", REGNO (x) + 1); return; - + case 'b': /* Convert GCC's comparison operators into FR30 comparison codes. */ switch (GET_CODE (x)) @@ -558,7 +558,7 @@ fr30_print_operand (FILE *file, rtx x, int code) break; } return; - + case 'B': /* Convert GCC's comparison operators into the complimentary FR30 comparison codes. */ @@ -587,7 +587,7 @@ fr30_print_operand (FILE *file, rtx x, int code) else { HOST_WIDE_INT val; - + val = INTVAL (x); val &= 0xff; @@ -595,7 +595,7 @@ fr30_print_operand (FILE *file, rtx x, int code) fprintf (file, HOST_WIDE_INT_PRINT_DEC, val); } return; - + case 'x': if (GET_CODE (x) != CONST_INT || INTVAL (x) < 16 @@ -617,11 +617,11 @@ fr30_print_operand (FILE *file, rtx x, int code) fputs (str, file); } return; - + case 0: /* Handled below. */ break; - + default: fprintf (stderr, "unknown code = %x\n", code); output_operand_lossage ("fr30_print_operand: unknown code"); @@ -636,7 +636,7 @@ fr30_print_operand (FILE *file, rtx x, int code) case MEM: x0 = XEXP (x,0); - + switch (GET_CODE (x0)) { case REG: @@ -677,11 +677,11 @@ fr30_print_operand (FILE *file, rtx x, int code) fprintf (file, "@(r15, #" HOST_WIDE_INT_PRINT_DEC ")", val); } break; - + case SYMBOL_REF: output_address (VOIDmode, x0); break; - + default: fprintf (stderr, "bad MEM code = %x\n", GET_CODE (x0)); debug_rtx (x); @@ -689,7 +689,7 @@ fr30_print_operand (FILE *file, rtx x, int code) break; } break; - + case CONST_DOUBLE : /* We handle SFmode constants here as output_addr_const doesn't. */ if (GET_MODE (x) == SFmode) @@ -740,7 +740,7 @@ fr30_function_value_regno_p (const unsigned int regno) return (regno == RETURN_VALUE_REGNUM); } -/*{{{ Function arguments */ +/*{{{ Function arguments */ /* Return true if we should pass an argument on the stack rather than in registers. */ @@ -787,7 +787,7 @@ fr30_arg_partial_bytes (cumulative_args_t cum_v, const function_arg_info &arg) register, partial stack space. */ if (*cum + fr30_num_arg_regs (arg) <= FR30_NUM_ARG_REGS) return 0; - + return (FR30_NUM_ARG_REGS - *cum) * UNITS_PER_WORD; } @@ -814,7 +814,7 @@ fr30_function_arg_advance (cumulative_args_t cum, } /*}}}*/ -/*{{{ Operand predicates */ +/*{{{ Operand predicates */ #ifndef Mmode #define Mmode machine_mode @@ -828,30 +828,30 @@ fr30_check_multiple_regs (rtx *operands, int num_operands, int descending) if (descending) { unsigned int prev_regno = 0; - + while (num_operands --) { if (GET_CODE (operands [num_operands]) != REG) return 0; - + if (REGNO (operands [num_operands]) < prev_regno) return 0; - + prev_regno = REGNO (operands [num_operands]); } } else { unsigned int prev_regno = CONDITION_CODE_REGNUM; - + while (num_operands --) { if (GET_CODE (operands [num_operands]) != REG) return 0; - + if (REGNO (operands [num_operands]) > prev_regno) return 0; - + prev_regno = REGNO (operands [num_operands]); } } @@ -895,13 +895,13 @@ fr30_move_double (rtx * operands) if (src_code == REG) { int reverse = (REGNO (dest) == REGNO (src) + 1); - + /* We normally copy the low-numbered register first. However, if the first register of operand 0 is the same as the second register of operand 1, we must copy in the opposite order. */ emit_insn (gen_rtx_SET (operand_subword (dest, reverse, TRUE, mode), operand_subword (src, reverse, TRUE, mode))); - + emit_insn (gen_rtx_SET (operand_subword (dest, !reverse, TRUE, mode), operand_subword (src, !reverse, TRUE, mode))); @@ -912,9 +912,9 @@ fr30_move_double (rtx * operands) rtx dest0 = operand_subword (dest, 0, TRUE, mode); rtx dest1 = operand_subword (dest, 1, TRUE, mode); rtx new_mem; - + gcc_assert (GET_CODE (addr) == REG); - + /* Copy the address before clobbering it. See PR 34174. */ emit_insn (gen_rtx_SET (dest1, addr)); emit_insn (gen_rtx_SET (dest0, adjust_address (src, SImode, 0))); @@ -923,7 +923,7 @@ fr30_move_double (rtx * operands) new_mem = gen_rtx_MEM (SImode, dest1); MEM_COPY_ATTRIBUTES (new_mem, src); - + emit_insn (gen_rtx_SET (dest1, new_mem)); } else if (src_code == CONST_INT || src_code == CONST_DOUBLE) @@ -932,7 +932,7 @@ fr30_move_double (rtx * operands) split_double (src, &words[0], &words[1]); emit_insn (gen_rtx_SET (operand_subword (dest, 0, TRUE, mode), words[0])); - + emit_insn (gen_rtx_SET (operand_subword (dest, 1, TRUE, mode), words[1])); } @@ -1006,7 +1006,7 @@ fr30_frame_pointer_required (void) target are 32 bit aligned within the trampoline. That allows us to initialize those locations with simple SImode stores. The alternative would be to use HImode stores. */ - + static void fr30_asm_trampoline_template (FILE *f) { diff --git a/gcc/config/fr30/fr30.h b/gcc/config/fr30/fr30.h index 19020fb..6d071a1 100644 --- a/gcc/config/fr30/fr30.h +++ b/gcc/config/fr30/fr30.h @@ -1,6 +1,6 @@ -/*{{{ Comment. */ +/*{{{ Comment. */ -/* Definitions of FR30 target. +/* Definitions of FR30 target. Copyright (C) 1998-2024 Free Software Foundation, Inc. Contributed by Cygnus Solutions. @@ -21,7 +21,7 @@ along with GCC; see the file COPYING3. If not see <http://www.gnu.org/licenses/>. */ /*}}}*/ -/*{{{ Run-time target specifications. */ +/*{{{ Run-time target specifications. */ #undef ASM_SPEC #define ASM_SPEC "" @@ -56,7 +56,7 @@ along with GCC; see the file COPYING3. If not see %{static:-Bstatic} %{shared:-shared} %{symbolic:-Bsymbolic}" /*}}}*/ -/*{{{ Storage Layout. */ +/*{{{ Storage Layout. */ #define BITS_BIG_ENDIAN 1 @@ -93,7 +93,7 @@ along with GCC; see the file COPYING3. If not see #define PCC_BITFIELD_TYPE_MATTERS 1 /*}}}*/ -/*{{{ Layout of Source Language Data Types. */ +/*{{{ Layout of Source Language Data Types. */ #define SHORT_TYPE_SIZE 16 #define INT_TYPE_SIZE 32 @@ -115,7 +115,7 @@ along with GCC; see the file COPYING3. If not see #define WCHAR_TYPE_SIZE BITS_PER_WORD /*}}}*/ -/*{{{ REGISTER BASICS. */ +/*{{{ REGISTER BASICS. */ /* Number of hardware registers known to the compiler. They receive numbers 0 through `FIRST_PSEUDO_REGISTER-1'; thus, the first pseudo register's number @@ -139,7 +139,7 @@ along with GCC; see the file COPYING3. If not see /* A call-used register that can be used during the function prologue. */ #define PROLOGUE_TMP_REGNUM COMPILER_SCRATCH_REGISTER - + /* Register numbers used for passing a function's static chain pointer. If register windows are used, the register number as seen by the called function is `STATIC_CHAIN_INCOMING_REGNUM', while the register number as @@ -161,7 +161,7 @@ along with GCC; see the file COPYING3. If not see determines which register this is. On other machines, you can choose any register you wish for this purpose. */ #define FRAME_POINTER_REGNUM 14 - + /* The register number of the stack pointer register, which must also be a fixed register according to `FIXED_REGISTERS'. On most machines, the hardware determines which register this is. */ @@ -231,7 +231,7 @@ along with GCC; see the file COPYING3. If not see } /*}}}*/ -/*{{{ Register Classes. */ +/*{{{ Register Classes. */ /* An enumeral type that must be defined with all the register class names as enumeral values. `NO_REGS' must be first. `ALL_REGS' must be the last @@ -332,7 +332,7 @@ enum reg_class #define CLASS_MAX_NREGS(CLASS, MODE) targetm.hard_regno_nregs (0, MODE) /*}}}*/ -/*{{{ Basic Stack Layout. */ +/*{{{ Basic Stack Layout. */ /* Define this macro if pushing a word onto the stack moves the stack pointer to a smaller address. */ @@ -367,7 +367,7 @@ enum reg_class #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (SImode, RETURN_POINTER_REGNUM) /*}}}*/ -/*{{{ Register That Address the Stack Frame. */ +/*{{{ Register That Address the Stack Frame. */ /* The register number of the arg pointer register, which is used to access the function's argument list. On some machines, this is the same as the frame @@ -379,7 +379,7 @@ enum reg_class #define ARG_POINTER_REGNUM 20 /*}}}*/ -/*{{{ Eliminating the Frame Pointer and the Arg Pointer. */ +/*{{{ Eliminating the Frame Pointer and the Arg Pointer. */ /* If defined, this macro specifies a table of register pairs used to eliminate unneeded registers that point into the stack frame. If it is not defined, @@ -417,7 +417,7 @@ enum reg_class (OFFSET) = fr30_compute_frame_size (FROM, TO) /*}}}*/ -/*{{{ Passing Function Arguments on the Stack. */ +/*{{{ Passing Function Arguments on the Stack. */ /* If defined, the maximum amount of space required for outgoing arguments will be computed and placed into the variable @@ -430,10 +430,10 @@ enum reg_class #define ACCUMULATE_OUTGOING_ARGS 1 /*}}}*/ -/*{{{ Function Arguments in Registers. */ +/*{{{ Function Arguments in Registers. */ /* The number of register assigned to holding function arguments. */ - + #define FR30_NUM_ARG_REGS 4 /* A C type for declaring a variable that is used as the first argument of @@ -478,7 +478,7 @@ enum reg_class ((REGNO) >= FIRST_ARG_REGNUM && ((REGNO) < FIRST_ARG_REGNUM + FR30_NUM_ARG_REGS)) /*}}}*/ -/*{{{ How Large Values are Returned. */ +/*{{{ How Large Values are Returned. */ /* Define this macro to be 1 if all structure and union return values must be in memory. Since this results in slower code, this should be defined only @@ -490,7 +490,7 @@ enum reg_class #define DEFAULT_PCC_STRUCT_RETURN 1 /*}}}*/ -/*{{{ Generating Code for Profiling. */ +/*{{{ Generating Code for Profiling. */ /* A C statement or compound statement to output to FILE some assembler code to call the profiling subroutine `mcount'. Before calling, the assembler code @@ -512,7 +512,7 @@ enum reg_class } /*}}}*/ -/*{{{ Trampolines for Nested Functions. */ +/*{{{ Trampolines for Nested Functions. */ /* A C expression for the size in bytes of the trampoline, as an integer. */ #define TRAMPOLINE_SIZE 18 @@ -523,7 +523,7 @@ enum reg_class #define TRAMPOLINE_ALIGNMENT 32 /*}}}*/ -/*{{{ Addressing Modes. */ +/*{{{ Addressing Modes. */ /* A number, the maximum number of registers that can appear in a valid memory address. Note that it is up to you to specify a value equal to the maximum @@ -536,15 +536,15 @@ enum reg_class /* On the FR30 we only have one real addressing mode - an address in a register. There are three special cases however: - + * indexed addressing using small positive offsets from the stack pointer - + * indexed addressing using small signed offsets from the frame pointer * register plus register addressing using R13 as the base register. At the moment we only support the first two of these special cases. */ - + #ifdef REG_OK_STRICT #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, LABEL) \ do \ @@ -617,7 +617,7 @@ enum reg_class #define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_BASE_P (X) /*}}}*/ -/*{{{ Describing Relative Costs of Operations */ +/*{{{ Describing Relative Costs of Operations */ /* Define this macro as a C expression which is nonzero if accessing less than a word of memory (i.e. a `char' or a `short') is no faster than accessing a @@ -633,7 +633,7 @@ enum reg_class #define SLOW_BYTE_ACCESS 1 /*}}}*/ -/*{{{ Dividing the output into sections. */ +/*{{{ Dividing the output into sections. */ /* A C expression whose value is a string containing the assembler operation that should precede instructions and read-only data. Normally `".text"' is @@ -668,13 +668,13 @@ enum reg_class #define ASM_APP_OFF "#NO_APP\n" /*}}}*/ -/*{{{ Output and Generation of Labels. */ +/*{{{ Output and Generation of Labels. */ /* Globalizing directive for a label. */ #define GLOBAL_ASM_OP "\t.globl " /*}}}*/ -/*{{{ Output of Assembler Instructions. */ +/*{{{ Output of Assembler Instructions. */ /* A C compound statement to output to stdio stream STREAM the assembler syntax for an instruction operand X. X is an RTL expression. @@ -713,7 +713,7 @@ enum reg_class #define IMMEDIATE_PREFIX "" /*}}}*/ -/*{{{ Output of Dispatch Tables. */ +/*{{{ Output of Dispatch Tables. */ /* This macro should be provided on machines where the addresses in a dispatch table are relative to the table's own address. @@ -741,7 +741,7 @@ fprintf (STREAM, "\t.word .L%d-.L%d\n", VALUE, REL) fprintf (STREAM, "\t.word .L%d\n", VALUE) /*}}}*/ -/*{{{ Assembler Commands for Alignment. */ +/*{{{ Assembler Commands for Alignment. */ /* A C statement to output to the stdio stream STREAM an assembler command to advance the location counter to a multiple of 2 to the POWER bytes. POWER @@ -750,7 +750,7 @@ fprintf (STREAM, "\t.word .L%d\n", VALUE) fprintf ((STREAM), "\t.p2align %d\n", (POWER)) /*}}}*/ -/*{{{ Miscellaneous Parameters. */ +/*{{{ Miscellaneous Parameters. */ /* An alias for a machine mode name. This is the machine mode that elements of a jump-table should have. */ diff --git a/gcc/config/freebsd-spec.h b/gcc/config/freebsd-spec.h index f43056b..42ee998 100644 --- a/gcc/config/freebsd-spec.h +++ b/gcc/config/freebsd-spec.h @@ -22,10 +22,10 @@ a copy of the GCC Runtime Library Exception along with this program; see the files COPYING3 and COPYING.RUNTIME respectively. If not, see <http://www.gnu.org/licenses/>. */ -/* Common FreeBSD configuration. +/* Common FreeBSD configuration. All FreeBSD architectures should include this file, which will specify their commonalities. - Adapted from gcc/config/freebsd.h by + Adapted from gcc/config/freebsd.h by David O'Brien <obrien@FreeBSD.org> Loren J. Rittle <ljrittle@acm.org>. */ @@ -49,7 +49,7 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see /* Define the default FreeBSD-specific per-CPU hook code. */ #define FBSD_TARGET_CPU_CPP_BUILTINS() do {} while (0) -/* Provide a CPP_SPEC appropriate for FreeBSD. We just deal with the GCC +/* Provide a CPP_SPEC appropriate for FreeBSD. We just deal with the GCC option `-posix', and PIC issues. */ #define FBSD_CPP_SPEC " \ @@ -58,10 +58,10 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see %{posix:-D_POSIX_SOURCE}" /* Provide a STARTFILE_SPEC appropriate for FreeBSD. Here we add - the magical crtbegin.o file (see crtstuff.c) which provides part - of the support for getting C++ file-scope static object constructed + the magical crtbegin.o file (see crtstuff.c) which provides part + of the support for getting C++ file-scope static object constructed before entering `main'. */ - + #define FBSD_STARTFILE_SPEC \ "%{!shared: \ %{pg:gcrt1.o%s} %{!pg:%{p:gcrt1.o%s} \ @@ -71,9 +71,9 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see crti.o%s %{static:crtbeginT.o%s;shared|pie:crtbeginS.o%s;:crtbegin.o%s}" /* Provide a ENDFILE_SPEC appropriate for FreeBSD. Here we tack on - the magical crtend.o file (see crtstuff.c) which provides part of - the support for getting C++ file-scope static object constructed - before entering `main', followed by a normal "finalizer" file, + the magical crtend.o file (see crtstuff.c) which provides part of + the support for getting C++ file-scope static object constructed + before entering `main', followed by a normal "finalizer" file, `crtn.o'. */ #define FBSD_ENDFILE_SPEC \ diff --git a/gcc/config/freebsd.h b/gcc/config/freebsd.h index 7add672..2643348 100644 --- a/gcc/config/freebsd.h +++ b/gcc/config/freebsd.h @@ -17,11 +17,11 @@ You should have received a copy of the GNU General Public License along with GCC; see the file COPYING3. If not see <http://www.gnu.org/licenses/>. */ -/* Common FreeBSD configuration. +/* Common FreeBSD configuration. All FreeBSD architectures should include this file, which will specify their commonalities. - Adapted from gcc/config/i386/freebsd-elf.h by - David O'Brien <obrien@FreeBSD.org>. + Adapted from gcc/config/i386/freebsd-elf.h by + David O'Brien <obrien@FreeBSD.org>. Further work by David O'Brien <obrien@FreeBSD.org> and Loren J. Rittle <ljrittle@acm.org>. */ diff --git a/gcc/config/frv/frv.cc b/gcc/config/frv/frv.cc index ac6fda6..216ad5f 100644 --- a/gcc/config/frv/frv.cc +++ b/gcc/config/frv/frv.cc @@ -2484,7 +2484,7 @@ frv_print_operand_address (FILE * stream, machine_mode /* mode */, rtx x) See gcc/testsuite/gcc.dg/asm-4.c for an example. */ frv_print_operand_memory_reference (stream, x, 0); return; - + default: break; } @@ -6311,7 +6311,7 @@ frv_secondary_reload_class (enum reg_class rclass, /* This hook exists to catch the case where secondary_reload_class() is called from init_reg_autoinc() in regclass.c - before the reload optabs have been initialised. */ - + static reg_class_t frv_secondary_reload (bool in_p, rtx x, reg_class_t reload_class_i, machine_mode reload_mode, @@ -6682,7 +6682,7 @@ frv_register_move_cost (machine_mode mode ATTRIBUTE_UNUSED, default: break; - case QUAD_REGS: + case QUAD_REGS: case GPR_REGS: case GR8_REGS: case GR9_REGS: diff --git a/gcc/config/gcn/gcn-run.cc b/gcc/config/gcn/gcn-run.cc index 2f3ed2d..64d29b3 100644 --- a/gcc/config/gcn/gcn-run.cc +++ b/gcc/config/gcn/gcn-run.cc @@ -426,7 +426,7 @@ load_image (const char *filename) /* Locate the "_init_array" function, and read the kernel's properties. */ hsa_executable_symbol_t symbol; - XHSA (hsa_fns.hsa_executable_get_symbol_fn (executable, NULL, + XHSA (hsa_fns.hsa_executable_get_symbol_fn (executable, NULL, "_init_array.kd", device, 0, &symbol), "Find '_init_array' function"); diff --git a/gcc/config/gcn/gcn-tree.cc b/gcc/config/gcn/gcn-tree.cc index 6a7485a..ad674c3 100644 --- a/gcc/config/gcn/gcn-tree.cc +++ b/gcc/config/gcn/gcn-tree.cc @@ -1,17 +1,17 @@ /* Copyright (C) 2017-2024 Free Software Foundation, Inc. This file is part of GCC. - + GCC is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 3, or (at your option) any later version. - + GCC is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. - + You should have received a copy of the GNU General Public License along with GCC; see the file COPYING3. If not see <http://www.gnu.org/licenses/>. */ @@ -184,7 +184,7 @@ gcn_lockless_update (location_t loc, gimple_stmt_iterator *gsi, } /* Helper function for gcn_reduction_update. - + Insert code to lockfully update *PTR with *PTR OP VAR just before GSI. This is necessary for types larger than 64 bits, where there is no cmp&swap instruction to implement a lockless scheme. We use @@ -488,7 +488,7 @@ gcn_goacc_reduction_teardown (gcall *call) } /* Implement TARGET_GOACC_REDUCTION. - + Expand calls to the GOACC REDUCTION internal function, into a sequence of gimple instructions. */ diff --git a/gcc/config/gcn/gcn.cc b/gcc/config/gcn/gcn.cc index 736ebeb..d078392 100644 --- a/gcc/config/gcn/gcn.cc +++ b/gcc/config/gcn/gcn.cc @@ -73,7 +73,7 @@ enum gcn_isa gcn_isa = ISA_GCN5; /* Default to GCN5. */ /* Reserve this much space for LDS (for propagating variables from worker-single mode to worker-partitioned mode), per workgroup. Global analysis could calculate an exact bound, but we don't do that yet. - + We want to permit full occupancy, so size accordingly. */ /* Use this as a default, but allow it to grow if the user requests a large @@ -127,7 +127,7 @@ gcn_init_machine_status (void) } /* Implement TARGET_OPTION_OVERRIDE. - + Override option settings where defaults are variable, or we have specific needs to consider. */ @@ -246,7 +246,7 @@ static const long default_requested_args /* Extract parameter settings from __attribute__((amdgpu_hsa_kernel ())). This function also sets the default values for some arguments. - + Return true on success, with ARGS populated. */ static bool @@ -343,7 +343,7 @@ gcn_parse_amdgpu_hsa_kernel_attribute (struct gcn_kernel_args *args, } /* Referenced by TARGET_ATTRIBUTE_TABLE. - + Validates target specific attributes. */ static tree @@ -373,7 +373,7 @@ gcn_handle_amdgpu_hsa_kernel_attribute (tree *node, tree name, } /* Implement TARGET_ATTRIBUTE_TABLE. - + Create target-specific __attribute__ types. */ TARGET_GNU_ATTRIBUTES (gcn_attribute_table, { @@ -491,7 +491,7 @@ VnMODE (int n, machine_mode mode) } /* Implement TARGET_CLASS_MAX_NREGS. - + Return the number of hard registers needed to hold a value of MODE in a register of class RCLASS. */ @@ -526,7 +526,7 @@ gcn_class_max_nregs (reg_class_t rclass, machine_mode mode) } /* Implement TARGET_HARD_REGNO_NREGS. - + Return the number of hard registers needed to hold a value of MODE in REGNO. */ @@ -537,7 +537,7 @@ gcn_hard_regno_nregs (unsigned int regno, machine_mode mode) } /* Implement TARGET_HARD_REGNO_MODE_OK. - + Return true if REGNO can hold value in MODE. */ bool @@ -618,7 +618,7 @@ gcn_hard_regno_mode_ok (unsigned int regno, machine_mode mode) } /* Implement REGNO_REG_CLASS via gcn.h. - + Return smallest class containing REGNO. */ enum reg_class @@ -653,7 +653,7 @@ gcn_regno_reg_class (int regno) } /* Implement TARGET_CAN_CHANGE_MODE_CLASS. - + GCC assumes that lowpart contains first part of value as stored in memory. This is not the case for vector registers. */ @@ -685,7 +685,7 @@ gcn_can_change_mode_class (machine_mode from, machine_mode to, } /* Implement TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P. - + When this hook returns true for MODE, the compiler allows registers explicitly used in the rtl to be used as spill registers but prevents the compiler from extending the lifetime of these @@ -699,7 +699,7 @@ gcn_small_register_classes_for_mode_p (machine_mode mode) } /* Implement TARGET_CLASS_LIKELY_SPILLED_P. - + Returns true if pseudos that have been assigned to registers of class RCLASS would likely be spilled because registers of RCLASS are needed for spill registers. */ @@ -712,7 +712,7 @@ gcn_class_likely_spilled_p (reg_class_t rclass) } /* Implement TARGET_MODES_TIEABLE_P. - + Returns true if a value of MODE1 is accessible in MODE2 without copying. */ @@ -734,7 +734,7 @@ gcn_modes_tieable_p (machine_mode mode1, machine_mode mode2) } /* Implement TARGET_TRULY_NOOP_TRUNCATION. - + Returns true if it is safe to “convert” a value of INPREC bits to one of OUTPREC bits (where OUTPREC is smaller than INPREC) by merely operating on it as if it had only OUTPREC bits. */ @@ -821,7 +821,7 @@ gcn_can_split_p (machine_mode, rtx op) } /* Implement TARGET_SPILL_CLASS. - + Return class of registers which could be used for pseudo of MODE and of class RCLASS for spilling instead of memory. Return NO_REGS if it is not possible or non-profitable. */ @@ -837,7 +837,7 @@ gcn_spill_class (reg_class_t c, machine_mode /*mode */ ) } /* Implement TARGET_IRA_CHANGE_PSEUDO_ALLOCNO_CLASS. - + Change allocno class for given pseudo from allocno and best class calculated by IRA. */ @@ -1132,7 +1132,7 @@ gcn_constant64_p (rtx x) } /* Implement TARGET_LEGITIMATE_CONSTANT_P. - + Returns true if X is a legitimate constant for a MODE immediate operand. */ bool @@ -1225,7 +1225,7 @@ gcn_gen_undef (machine_mode mode) GEN_VNM - create accessor functions for all sizes of all modes GEN_VN_NOEXEC - for insns without "_exec" variants GEN_VNM_NOEXEC - likewise - + E.g. add<mode>3 GEN_VNM (add, 3, A(rtx dest, rtx s1, rtx s2), A(dest, s1, s2) @@ -1606,7 +1606,7 @@ gcn_global_address_p (rtx addr) } /* Implement TARGET_ADDR_SPACE_LEGITIMATE_ADDRESS_P. - + Recognizes RTL expressions that are valid memory addresses for an instruction. The MODE argument is the machine mode for the MEM expression that wants to use this address. @@ -1786,7 +1786,7 @@ gcn_addr_space_legitimate_address_p (machine_mode mode, rtx x, bool strict, } /* Implement TARGET_ADDR_SPACE_POINTER_MODE. - + Return the appropriate mode for a named address pointer. */ static scalar_int_mode @@ -1809,7 +1809,7 @@ gcn_addr_space_pointer_mode (addr_space_t addrspace) } /* Implement TARGET_ADDR_SPACE_ADDRESS_MODE. - + Return the appropriate mode for a named address space address. */ static scalar_int_mode @@ -1819,7 +1819,7 @@ gcn_addr_space_address_mode (addr_space_t addrspace) } /* Implement TARGET_ADDR_SPACE_SUBSET_P. - + Determine if one named address space is a subset of another. */ static bool @@ -1897,7 +1897,7 @@ gcn_addr_space_debug (addr_space_t as) /* Implement REGNO_MODE_CODE_OK_FOR_BASE_P via gcn.h - + Retun true if REGNO is OK for memory adressing. */ bool @@ -1930,7 +1930,7 @@ gcn_regno_mode_code_ok_for_base_p (int regno, } /* Implement MODE_CODE_BASE_REG_CLASS via gcn.h. - + Return a suitable register class for memory addressing. */ reg_class @@ -1961,7 +1961,7 @@ gcn_mode_code_base_reg_class (machine_mode mode, addr_space_t as, int oc, } /* Implement REGNO_OK_FOR_INDEX_P via gcn.h. - + Return true if REGNO is OK for index of memory addressing. */ bool @@ -2629,7 +2629,7 @@ gcn_valid_move_p (machine_mode mode, rtx dest, rtx src) /* {{{ Functions and ABI. */ /* Implement TARGET_FUNCTION_VALUE. - + Define how to find the value returned by a function. The register location is always the same, but the mode depends on VALTYPE. */ @@ -2648,7 +2648,7 @@ gcn_function_value (const_tree valtype, const_tree, bool) } /* Implement TARGET_FUNCTION_VALUE_REGNO_P. - + Return true if N is a possible register number for the function return value. */ @@ -2694,7 +2694,7 @@ gcn_strict_argument_naming (cumulative_args_t cum_v) } /* Implement TARGET_PRETEND_OUTGOING_VARARGS_NAMED. - + See comment on gcn_strict_argument_naming. */ static bool @@ -2704,7 +2704,7 @@ gcn_pretend_outgoing_varargs_named (cumulative_args_t cum_v) } /* Implement TARGET_FUNCTION_ARG. - + Return an RTX indicating whether a function argument is passed in a register and if so, which register. */ @@ -2766,7 +2766,7 @@ gcn_function_arg (cumulative_args_t cum_v, const function_arg_info &arg) } /* Implement TARGET_FUNCTION_ARG_ADVANCE. - + Updates the summarizer variable pointed to by CUM_V to advance past an argument in the argument list. */ @@ -2804,7 +2804,7 @@ gcn_function_arg_advance (cumulative_args_t cum_v, } /* Implement TARGET_ARG_PARTIAL_BYTES. - + Returns the number of bytes at the beginning of an argument that must be put in registers. The value must be zero for arguments that are passed entirely in registers or that are entirely pushed on the stack. */ @@ -2856,7 +2856,7 @@ gcn_detect_incoming_pointer_arg (tree fndecl) } /* Implement INIT_CUMULATIVE_ARGS, via gcn.h. - + Initialize a variable CUM of type CUMULATIVE_ARGS for a call to a function whose data type is FNTYPE. For a library call, FNTYPE is 0. */ @@ -2933,7 +2933,7 @@ gcn_return_in_memory (const_tree type, const_tree ARG_UNUSED (fntype)) } /* Implement TARGET_PROMOTE_FUNCTION_MODE. - + Return the mode to use for outgoing function arguments. */ machine_mode @@ -2949,7 +2949,7 @@ gcn_promote_function_mode (const_tree ARG_UNUSED (type), machine_mode mode, } /* Implement TARGET_GIMPLIFY_VA_ARG_EXPR. - + Derived from hppa_gimplify_va_arg_expr. The generic routine doesn't handle ARGS_GROW_DOWNWARDS. */ @@ -3054,7 +3054,7 @@ gcn_compute_frame_offsets (void) /* Insert code into the prologue or epilogue to store or load any callee-save register to/from the stack. - + Helper function for gcn_expand_prologue and gcn_expand_epilogue. */ static void @@ -3611,10 +3611,10 @@ gcn_frame_pointer_rqd (void) } /* Implement TARGET_CAN_ELIMINATE. - + Return true if the compiler is allowed to try to replace register number FROM_REG with register number TO_REG. - + FIXME: is the default "true" not enough? Should this be a negative set? */ bool @@ -3625,7 +3625,7 @@ gcn_can_eliminate_p (int /*from_reg */ , int to_reg) } /* Implement INITIAL_ELIMINATION_OFFSET. - + Returns the initial difference between the specified pair of registers, in terms of stack position. */ @@ -3692,7 +3692,7 @@ gcn_hard_regno_rename_ok (unsigned int from_reg, unsigned int to_reg) } /* Implement HARD_REGNO_CALLER_SAVE_MODE. - + Which mode is required for saving NREGS of a pseudo-register in call-clobbered hard register REGNO. */ @@ -3801,7 +3801,7 @@ gcn_expand_divmod_libfunc (rtx libfunc, machine_mode mode, rtx op0, rtx op1, /* {{{ Miscellaneous. */ /* Implement TARGET_CANNOT_COPY_INSN_P. - + Return true if INSN must not be duplicated. */ static bool @@ -3893,7 +3893,7 @@ gcn_emutls_var_init (tree, tree decl, tree) /* {{{ Costs. */ /* Implement TARGET_RTX_COSTS. - + Compute a (partial) cost for rtx X. Return true if the complete cost has been computed, and false if subexpressions should be scanned. In either case, *TOTAL contains the cost result. */ @@ -3930,7 +3930,7 @@ gcn_rtx_costs (rtx x, machine_mode, int, int, int *total, bool) } /* Implement TARGET_MEMORY_MOVE_COST. - + Return the cost of moving data of mode M between a register and memory. A value of 2 is the default; this cost is relative to those in `REGISTER_MOVE_COST'. @@ -3992,7 +3992,7 @@ gcn_memory_move_cost (machine_mode mode, reg_class_t regclass, bool in) } /* Implement TARGET_REGISTER_MOVE_COST. - + Return the cost of moving data from a register in class CLASS1 to one in class CLASS2. Base value is 2. */ @@ -4115,7 +4115,7 @@ struct gcn_builtin_description gcn_builtins[] = { static GTY(()) tree gcn_builtin_decls[GCN_BUILTIN_MAX]; /* Implement TARGET_BUILTIN_DECL. - + Return the GCN builtin for CODE. */ tree @@ -4167,7 +4167,7 @@ gcn_init_builtin_types (void) } /* Implement TARGET_INIT_BUILTINS. - + Set up all builtin functions for this target. */ static void @@ -4455,7 +4455,7 @@ gcn_init_libfuncs (void) /* Expand the CMP_SWAP GCN builtins. We have our own versions that do not require taking the address of any object, other than the memory cell being operated on. - + Helper function for gcn_expand_builtin_1. */ static rtx @@ -4959,7 +4959,7 @@ gcn_expand_builtin_binop (tree exp, rtx target, rtx /*subtarget */ , } /* Implement TARGET_EXPAND_BUILTIN. - + Expand an expression EXP that calls a built-in function, with result going to TARGET if that's convenient (and in mode MODE if that's convenient). SUBTARGET may be used as the target for computing one of EXP's operands. @@ -4999,7 +4999,7 @@ gcn_vectorize_get_mask_mode (machine_mode) /* Return an RTX that references a vector with the i-th lane containing PERM[i]*4. - + Helper function for gcn_vectorize_vec_perm_const. */ static rtx @@ -5036,9 +5036,9 @@ gcn_make_vec_perm_address (unsigned int *perm, int nelt) } /* Implement TARGET_VECTORIZE_VEC_PERM_CONST. - + Return true if permutation with SEL is possible. - + If DST/SRC0/SRC1 are non-null, emit the instructions to perform the permutations. */ @@ -5129,7 +5129,7 @@ gcn_vectorize_vec_perm_const (machine_mode vmode, machine_mode op_mode, } /* Implements TARGET_VECTOR_MODE_SUPPORTED_P. - + Return nonzero if vector MODE is supported with at least move instructions. */ @@ -6123,7 +6123,7 @@ gcn_md_reorg (void) CLEAR_REG_SET (&live); /* "Manually Inserted Wait States (NOPs)." - + GCN hardware detects most kinds of register dependencies, but there are some exceptions documented in the ISA manual. This pass detects the missed cases, and inserts the documented number of NOPs @@ -6434,7 +6434,7 @@ gcn_fork_join (gcall *call, const int dims[], bool is_fork) /* Implement ??????? FIXME make this a real hook. - + Adjust FNDECL such that options inherited from the host compiler are made appropriate for the accelerator compiler. */ @@ -6497,7 +6497,7 @@ gcn_shared_mem_layout (unsigned HOST_WIDE_INT *lo, /* {{{ ASM Output. */ /* Implement TARGET_ASM_FILE_START. - + Print assembler file header text. */ static void @@ -6518,9 +6518,9 @@ output_file_start (void) } /* Implement ASM_DECLARE_FUNCTION_NAME via gcn-hsa.h. - + Print the initial definition of a function name. - + For GCN kernel entry points this includes all the HSA meta-data, special alignment constraints that don't apply to regular functions, and magic comments that pass information to mkoffload. */ @@ -6737,7 +6737,7 @@ gcn_asm_select_section (tree exp, int reloc, unsigned HOST_WIDE_INT align) } /* Implement TARGET_ASM_FUNCTION_PROLOGUE. - + Emits custom text into the assembler file at the head of each function. */ static void @@ -6901,7 +6901,7 @@ gcn_asm_output_symbol_ref (FILE *file, rtx x) } /* Implement TARGET_CONSTANT_ALIGNMENT. - + Returns the alignment in bits of a constant that is being placed in memory. CONSTANT is the constant and BASIC_ALIGN is the alignment that the object would ordinarily have. */ @@ -7695,7 +7695,7 @@ print_operand (FILE *file, rtx x, int code) } /* Implement DEBUGGER_REGNO macro. - + Return the DWARF register number that corresponds to the GCC internal REGNO. */ @@ -7734,7 +7734,7 @@ gcn_dwarf_register_number (unsigned int regno) } /* Implement TARGET_DWARF_REGISTER_SPAN. - + DImode and Vector DImode require additional registers. */ static rtx diff --git a/gcc/config/h8300/h8300.cc b/gcc/config/h8300/h8300.cc index 7ab26f2..17c6e91 100644 --- a/gcc/config/h8300/h8300.cc +++ b/gcc/config/h8300/h8300.cc @@ -317,7 +317,7 @@ h8300_option_override (void) "%<-msx%> - option ignored"); } -#ifdef H8300_LINUX +#ifdef H8300_LINUX if ((TARGET_NORMAL_MODE)) { error ("%<-mn%> is not supported for linux targets"); @@ -811,7 +811,7 @@ h8300_expand_prologue (void) if (h8300_monitor_function_p (current_function_decl)) /* The monitor function act as normal functions, which means it - can accept parameters and return values. In addition to this, + can accept parameters and return values. In addition to this, interrupts are masked in prologue and return with "rte" in epilogue. */ emit_insn (gen_monitor_prologue ()); @@ -1484,7 +1484,7 @@ h8300_print_operand (FILE *file, rtx x, int code) if ((exact_log2 ((bitint >> 8) & 0xff)) == -1) bitint = exact_log2 (bitint & 0xff); else - bitint = exact_log2 ((bitint >> 8) & 0xff); + bitint = exact_log2 ((bitint >> 8) & 0xff); gcc_assert (bitint >= 0); fprintf (file, "#%d", bitint); break; @@ -1493,7 +1493,7 @@ h8300_print_operand (FILE *file, rtx x, int code) if ((exact_log2 ((bitint >> 8) & 0xff)) == -1 ) bitint = exact_log2 (bitint & 0xff); else - bitint = (exact_log2 ((bitint >> 8) & 0xff)); + bitint = (exact_log2 ((bitint >> 8) & 0xff)); gcc_assert (bitint >= 0); fprintf (file, "#%d", bitint); break; @@ -2358,7 +2358,7 @@ h8300_bitfield_length (rtx op, rtx op2) if (GET_CODE (op) == REG) op = op2; gcc_assert (GET_CODE (op) != REG); - + size = GET_MODE_SIZE (GET_MODE (op)); operand_length = h8300_classify_operand (op, size, &opclass); @@ -2521,7 +2521,7 @@ h8300_insn_length_from_table (rtx_insn *insn, rtx * operands) case LENGTH_TABLE_BITFIELD: return h8300_bitfield_length (operands[0], operands[1]); - + case LENGTH_TABLE_BITBRANCH: return h8300_bitfield_length (operands[1], operands[2]) - 2; @@ -4100,7 +4100,7 @@ output_a_shift (rtx operands[4], rtx_code code) /* This case must be taken care of by one of the two splitters that convert a variable shift into a loop. */ gcc_assert (GET_CODE (operands[2]) == CONST_INT); - + n = INTVAL (operands[2]); /* If the count is negative, make it 0. */ @@ -4113,7 +4113,7 @@ output_a_shift (rtx operands[4], rtx_code code) n = GET_MODE_BITSIZE (mode); get_shift_alg (shift_type, shift_mode, n, &info); - + switch (info.alg) { case SHIFT_SPECIAL: @@ -4134,7 +4134,7 @@ output_a_shift (rtx operands[4], rtx_code code) for (; n > 0; n--) output_asm_insn (info.shift1, operands); return ""; - + case SHIFT_ROT_AND: { int m = GET_MODE_BITSIZE (mode) - n; @@ -4146,18 +4146,18 @@ output_a_shift (rtx operands[4], rtx_code code) /* Not all possibilities of rotate are supported. They shouldn't be generated, but let's watch for 'em. */ gcc_assert (info.shift1); - + /* Emit two bit rotates first. */ if (info.shift2 != NULL) { for (; m > 1; m -= 2) output_asm_insn (info.shift2, operands); } - + /* Now single bit rotates for any residual. */ for (; m > 0; m--) output_asm_insn (info.shift1, operands); - + /* Now mask off the high bits. */ switch (mode) { @@ -4201,7 +4201,7 @@ output_a_shift (rtx operands[4], rtx_code code) fprintf (asm_out_file, "\tbne .Llt%d\n", loopend_lab); } return ""; - + default: gcc_unreachable (); } @@ -4381,7 +4381,7 @@ compute_a_shift_cc (rtx operands[3], rtx_code code) enum shift_mode shift_mode; struct shift_info info; int n; - + switch (mode) { case E_QImode: @@ -4415,7 +4415,7 @@ compute_a_shift_cc (rtx operands[3], rtx_code code) /* This case must be taken care of by one of the two splitters that convert a variable shift into a loop. */ gcc_assert (GET_CODE (operands[2]) == CONST_INT); - + n = INTVAL (operands[2]); /* If the count is negative, make it 0. */ @@ -4426,9 +4426,9 @@ compute_a_shift_cc (rtx operands[3], rtx_code code) do the intuitive thing. */ else if ((unsigned int) n > GET_MODE_BITSIZE (mode)) n = GET_MODE_BITSIZE (mode); - + get_shift_alg (shift_type, shift_mode, n, &info); - + switch (info.alg) { case SHIFT_SPECIAL: @@ -4441,11 +4441,11 @@ compute_a_shift_cc (rtx operands[3], rtx_code code) case SHIFT_INLINE: return (info.cc_inline == OLD_CC_SET_ZN || info.cc_inline == OLD_CC_SET_ZNV); - + case SHIFT_ROT_AND: /* This case always ends with an and instruction. */ return true; - + case SHIFT_LOOP: /* A loop to shift by a "large" constant value. If we have shift-by-2 insns, use them. */ @@ -4454,10 +4454,10 @@ compute_a_shift_cc (rtx operands[3], rtx_code code) if (n % 2) return (info.cc_inline == OLD_CC_SET_ZN || info.cc_inline == OLD_CC_SET_ZNV); - + } return false; - + default: gcc_unreachable (); } diff --git a/gcc/config/host-darwin.h b/gcc/config/host-darwin.h index ecf454e..23752c4 100644 --- a/gcc/config/host-darwin.h +++ b/gcc/config/host-darwin.h @@ -18,7 +18,7 @@ <http://www.gnu.org/licenses/>. */ extern void * darwin_gt_pch_get_address (size_t sz, int fd); -extern int darwin_gt_pch_use_address (void *&addr, size_t sz, int fd, +extern int darwin_gt_pch_use_address (void *&addr, size_t sz, int fd, size_t off); #undef HOST_HOOKS_GT_PCH_GET_ADDRESS diff --git a/gcc/config/host-linux.cc b/gcc/config/host-linux.cc index 1cec56e..c1214b3 100644 --- a/gcc/config/host-linux.cc +++ b/gcc/config/host-linux.cc @@ -105,7 +105,7 @@ #endif /* Determine a location where we might be able to reliably allocate SIZE - bytes. FD is the PCH file, though we should return with the file + bytes. FD is the PCH file, though we should return with the file unmapped. */ static void * diff --git a/gcc/config/host-netbsd.cc b/gcc/config/host-netbsd.cc index 690c636..59df05a 100644 --- a/gcc/config/host-netbsd.cc +++ b/gcc/config/host-netbsd.cc @@ -62,7 +62,7 @@ netbsd_gt_pch_get_address (size_t size, int fd) return addr; } -/* Map SIZE bytes of FD+OFFSET at BASE. Return 1 if we succeeded at +/* Map SIZE bytes of FD+OFFSET at BASE. Return 1 if we succeeded at mapping the data at BASE, -1 if we couldn't. */ static int diff --git a/gcc/config/host-openbsd.cc b/gcc/config/host-openbsd.cc index 8a3e75d..9d6c927 100644 --- a/gcc/config/host-openbsd.cc +++ b/gcc/config/host-openbsd.cc @@ -62,7 +62,7 @@ openbsd_gt_pch_get_address (size_t size, int fd) return addr; } -/* Map SIZE bytes of FD+OFFSET at BASE. Return 1 if we succeeded at +/* Map SIZE bytes of FD+OFFSET at BASE. Return 1 if we succeeded at mapping the data at BASE, -1 if we couldn't. */ static int diff --git a/gcc/config/host-solaris.cc b/gcc/config/host-solaris.cc index f8afed7..0e0325b 100644 --- a/gcc/config/host-solaris.cc +++ b/gcc/config/host-solaris.cc @@ -39,7 +39,7 @@ mmap_fixed (void *addr, size_t len, int prot, int flags, int fd, off_t off) void *base; base = mmap ((caddr_t) addr, len, prot, flags, fd, off); - + if (base != addr) { size_t page_size = getpagesize(); @@ -101,7 +101,7 @@ sol_gt_pch_get_address (size_t size, int fd) return addr; } -/* Map SIZE bytes of FD+OFFSET at BASE. Return 1 if we succeeded at +/* Map SIZE bytes of FD+OFFSET at BASE. Return 1 if we succeeded at mapping the data at BASE, -1 if we couldn't. */ static int diff --git a/gcc/config/i386/avx10_2-512convertintrin.h b/gcc/config/i386/avx10_2-512convertintrin.h index dfbdfc3..178b5ff 100644 --- a/gcc/config/i386/avx10_2-512convertintrin.h +++ b/gcc/config/i386/avx10_2-512convertintrin.h @@ -276,7 +276,7 @@ _mm512_cvtne2ph_pbf8 (__m512h __A, __m512h __B) extern __inline__ __m512i __attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) -_mm512_mask_cvtne2ph_pbf8 (__m512i __W, __mmask64 __U, +_mm512_mask_cvtne2ph_pbf8 (__m512i __W, __mmask64 __U, __m512h __A, __m512h __B) { return (__m512i) __builtin_ia32_vcvtne2ph2bf8512_mask ((__v32hf) __A, @@ -375,7 +375,7 @@ _mm512_cvtnes2ph_phf8 (__m512h __A, __m512h __B) extern __inline__ __m512i __attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) -_mm512_mask_cvtnes2ph_phf8 (__m512i __W, __mmask64 __U, +_mm512_mask_cvtnes2ph_phf8 (__m512i __W, __mmask64 __U, __m512h __A, __m512h __B) { return (__m512i) __builtin_ia32_vcvtne2ph2hf8s512_mask ((__v32hf) __A, diff --git a/gcc/config/i386/avx10_2bf16intrin.h b/gcc/config/i386/avx10_2bf16intrin.h index f36fb8e..012c704 100644 --- a/gcc/config/i386/avx10_2bf16intrin.h +++ b/gcc/config/i386/avx10_2bf16intrin.h @@ -1270,14 +1270,14 @@ _mm_cmp_pbh_mask (__m128bh __A, __m128bh __B, const int __imm) #else #define _mm256_mask_cmp_pbh_mask(A, B, C, D) \ ((__mmask16) __builtin_ia32_cmppbf16256_mask ((B), (C), (D), (A))) - + #define _mm256_cmp_pbh_mask(A, B, C) \ ((__mmask16) __builtin_ia32_cmppbf16256_mask ((A), (B), (C), \ (__mmask16) (-1))) #define _mm_mask_cmp_pbh_mask(A, B, C, D) \ ((__mmask8) __builtin_ia32_cmppbf16128_mask ((B), (C), (D), (A))) - + #define _mm_cmp_pbh_mask(A, B, C) \ ((__mmask8) __builtin_ia32_cmppbf16128_mask ((A), (B), (C), \ (__mmask8) (-1))) diff --git a/gcc/config/i386/avx10_2convertintrin.h b/gcc/config/i386/avx10_2convertintrin.h index 8d2c1a5..08e34d5 100644 --- a/gcc/config/i386/avx10_2convertintrin.h +++ b/gcc/config/i386/avx10_2convertintrin.h @@ -429,7 +429,7 @@ _mm_cvtne2ph_pbf8 (__m128h __A, __m128h __B) extern __inline__ __m128i __attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) -_mm_mask_cvtne2ph_pbf8 (__m128i __W, __mmask16 __U, +_mm_mask_cvtne2ph_pbf8 (__m128i __W, __mmask16 __U, __m128h __A, __m128h __B) { return (__m128i) __builtin_ia32_vcvtne2ph2bf8128_mask ((__v8hf) __A, @@ -462,7 +462,7 @@ _mm256_cvtne2ph_pbf8 (__m256h __A, __m256h __B) extern __inline__ __m256i __attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) -_mm256_mask_cvtne2ph_pbf8 (__m256i __W, __mmask32 __U, +_mm256_mask_cvtne2ph_pbf8 (__m256i __W, __mmask32 __U, __m256h __A, __m256h __B) { return (__m256i) __builtin_ia32_vcvtne2ph2bf8256_mask ((__v16hf) __A, @@ -495,7 +495,7 @@ _mm_cvtnes2ph_pbf8 (__m128h __A, __m128h __B) extern __inline__ __m128i __attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) -_mm_mask_cvtnes2ph_pbf8 (__m128i __W, __mmask16 __U, +_mm_mask_cvtnes2ph_pbf8 (__m128i __W, __mmask16 __U, __m128h __A, __m128h __B) { return (__m128i) __builtin_ia32_vcvtne2ph2bf8s128_mask ((__v8hf) __A, diff --git a/gcc/config/i386/avx512dqintrin.h b/gcc/config/i386/avx512dqintrin.h index d9890c6..a4ab501 100644 --- a/gcc/config/i386/avx512dqintrin.h +++ b/gcc/config/i386/avx512dqintrin.h @@ -120,7 +120,7 @@ _cvtmask8_u32 (__mmask8 __A) { return (unsigned int) __builtin_ia32_kmovb ((__mmask8 ) __A); } - + extern __inline __mmask8 __attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) _cvtu32_mask8 (unsigned int __A) diff --git a/gcc/config/i386/biarch64.h b/gcc/config/i386/biarch64.h index e7c14bc..7cbfb2a 100644 --- a/gcc/config/i386/biarch64.h +++ b/gcc/config/i386/biarch64.h @@ -1,6 +1,6 @@ /* Make configure files to produce biarch compiler defaulting to 64bit mode. This file must be included very first, while the OS specific file later - to overwrite otherwise wrong defaults. + to overwrite otherwise wrong defaults. Copyright (C) 2001-2024 Free Software Foundation, Inc. Contributed by Bo Thorsen <bo@suse.de>. diff --git a/gcc/config/i386/cpuid.h b/gcc/config/i386/cpuid.h index 1e8060e..a75ba2b 100644 --- a/gcc/config/i386/cpuid.h +++ b/gcc/config/i386/cpuid.h @@ -5,16 +5,16 @@ * under the terms of the GNU General Public License as published by the * Free Software Foundation; either version 3, or (at your option) any * later version. - * + * * This file is distributed in the hope that it will be useful, but * WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU * General Public License for more details. - * + * * Under Section 7 of GPL version 3, you are granted additional * permissions described in the GCC Runtime Library Exception, version * 3.1, as published by the Free Software Foundation. - * + * * You should have received a copy of the GNU General Public License and * a copy of the GCC Runtime Library Exception along with this program; * see the files COPYING3 and COPYING.RUNTIME respectively. If not, see diff --git a/gcc/config/i386/cygming.h b/gcc/config/i386/cygming.h index 9c8c7e3..bd1259f 100644 --- a/gcc/config/i386/cygming.h +++ b/gcc/config/i386/cygming.h @@ -192,7 +192,7 @@ along with GCC; see the file COPYING3. If not see in_section = NULL) /* Older versions of gas don't handle 'r' as data. - Explicitly set data flag with 'd'. */ + Explicitly set data flag with 'd'. */ #define READONLY_DATA_SECTION_ASM_OP "\t.section .rdata,\"dr\"" /* Don't allow flag_pic to propagate since gas may produce invalid code diff --git a/gcc/config/i386/cygwin.h b/gcc/config/i386/cygwin.h index 63de10c..795d3a5 100644 --- a/gcc/config/i386/cygwin.h +++ b/gcc/config/i386/cygwin.h @@ -137,7 +137,7 @@ along with GCC; see the file COPYING3. If not see do not use them unnecessarily in gthr-posix.h. */ #define GTHREAD_USE_WEAK 0 -/* Every program on cygwin links against cygwin1.dll which contains +/* Every program on cygwin links against cygwin1.dll which contains the pthread routines. There is no need to explicitly link them and the -pthread flag is accepted only for compatibility. */ #undef GOMP_SELF_SPECS diff --git a/gcc/config/i386/djgpp.h b/gcc/config/i386/djgpp.h index 1b5dfb7..e8c3934 100644 --- a/gcc/config/i386/djgpp.h +++ b/gcc/config/i386/djgpp.h @@ -98,7 +98,7 @@ along with GCC; see the file COPYING3. If not see while (0) #endif -/* This is how to tell assembler that a symbol is weak */ +/* This is how to tell assembler that a symbol is weak */ #undef ASM_WEAKEN_LABEL #define ASM_WEAKEN_LABEL(FILE,NAME) \ do { fputs ("\t.weak\t", FILE); assemble_name (FILE, NAME); \ diff --git a/gcc/config/i386/driver-i386.cc b/gcc/config/i386/driver-i386.cc index 26f094c..f0ce017 100644 --- a/gcc/config/i386/driver-i386.cc +++ b/gcc/config/i386/driver-i386.cc @@ -253,7 +253,7 @@ decode_caches_intel (unsigned reg, bool xeon_mp, /* Detect cache parameters using CPUID function 2. */ static void -detect_caches_cpuid2 (bool xeon_mp, +detect_caches_cpuid2 (bool xeon_mp, struct cache_desc *level1, struct cache_desc *level2) { unsigned regs[4]; @@ -296,7 +296,7 @@ detect_caches_cpuid4 (struct cache_desc *level1, struct cache_desc *level2, int count; for (count = 0;; count++) - { + { __cpuid_count(4, count, eax, ebx, ecx, edx); switch (eax & 0x1f) { @@ -689,7 +689,7 @@ const char *host_detect_local_cpu (int argc, const char **argv) cpu = "haswell"; /* Assume Sandy Bridge. */ else - cpu = "sandybridge"; + cpu = "sandybridge"; } else if (has_feature (FEATURE_SSE4_2)) { diff --git a/gcc/config/i386/freebsd.h b/gcc/config/i386/freebsd.h index 583c752..2965048 100644 --- a/gcc/config/i386/freebsd.h +++ b/gcc/config/i386/freebsd.h @@ -48,17 +48,17 @@ along with GCC; see the file COPYING3. If not see #undef SIZE_TYPE #define SIZE_TYPE (TARGET_64BIT ? "long unsigned int" : "unsigned int") - + #undef PTRDIFF_TYPE #define PTRDIFF_TYPE (TARGET_64BIT ? "long int" : "int") - + #undef WCHAR_TYPE_SIZE #define WCHAR_TYPE_SIZE (TARGET_64BIT ? 32 : BITS_PER_WORD) #undef SUBTARGET_EXTRA_SPECS /* i386.h bogusly defines it. */ #define SUBTARGET_EXTRA_SPECS \ { "fbsd_dynamic_linker", FBSD_DYNAMIC_LINKER } - + /* Use the STARTFILE_SPEC from config/freebsd-spec.h. */ #undef STARTFILE_SPEC diff --git a/gcc/config/i386/gas.h b/gcc/config/i386/gas.h index ae77e27..fbf1686 100644 --- a/gcc/config/i386/gas.h +++ b/gcc/config/i386/gas.h @@ -50,7 +50,7 @@ along with GCC; see the file COPYING3. If not see doubt or guess work, and since this file is used for both a.out and other file formats, we use one of them. */ -#ifdef HAVE_GAS_BALIGN_AND_P2ALIGN +#ifdef HAVE_GAS_BALIGN_AND_P2ALIGN #undef ASM_OUTPUT_ALIGN #define ASM_OUTPUT_ALIGN(FILE,LOG) \ if ((LOG)!=0) fprintf ((FILE), "\t.balign %d\n", 1 << (LOG)) diff --git a/gcc/config/i386/gmm_malloc.h b/gcc/config/i386/gmm_malloc.h index 7e2ff62..6d4f30c 100644 --- a/gcc/config/i386/gmm_malloc.h +++ b/gcc/config/i386/gmm_malloc.h @@ -29,7 +29,7 @@ #include <errno.h> #endif -static __inline__ void * +static __inline__ void * _mm_malloc (size_t __size, size_t __align) { void * __malloc_ptr; @@ -50,7 +50,7 @@ _mm_malloc (size_t __size, size_t __align) /* Assume malloc'd pointer is aligned at least to sizeof (void*). If necessary, add another sizeof (void*) to store the value returned by malloc. Effectively this enforces a minimum alignment - of sizeof double. */ + of sizeof double. */ if (__align < 2 * sizeof (void *)) __align = 2 * sizeof (void *); @@ -62,7 +62,7 @@ _mm_malloc (size_t __size, size_t __align) __aligned_ptr = (void *) (((size_t) __malloc_ptr + __align) & ~((size_t) (__align) - 1)); - /* Store the original pointer just before p. */ + /* Store the original pointer just before p. */ ((void **) __aligned_ptr)[-1] = __malloc_ptr; return __aligned_ptr; diff --git a/gcc/config/i386/gnu-user.h b/gcc/config/i386/gnu-user.h index da6f64b..a7673eb 100644 --- a/gcc/config/i386/gnu-user.h +++ b/gcc/config/i386/gnu-user.h @@ -41,16 +41,16 @@ along with GCC; see the file COPYING3. If not see #undef SIZE_TYPE #define SIZE_TYPE "unsigned int" - + #undef PTRDIFF_TYPE #define PTRDIFF_TYPE "int" - + #undef WCHAR_TYPE #define WCHAR_TYPE "long int" - + #undef WCHAR_TYPE_SIZE #define WCHAR_TYPE_SIZE BITS_PER_WORD - + /* Provide a LINK_SPEC appropriate for GNU userspace. Here we provide support for the special GCC options -static and -shared, which allow us to link things in one of these three modes by applying the appropriate diff --git a/gcc/config/i386/host-cygwin.cc b/gcc/config/i386/host-cygwin.cc index c72999c..a693d5b 100644 --- a/gcc/config/i386/host-cygwin.cc +++ b/gcc/config/i386/host-cygwin.cc @@ -59,7 +59,7 @@ cygwin_gt_pch_get_address (size_t sz, int fd) /* Cygwin requires that the underlying file be at least as large as the requested mapping. */ if ((size_t) p < sz) - { + { if (ftruncate (fd, sz) == -1) fatal_error (input_location, "cannot extend PCH file: %m"); } diff --git a/gcc/config/i386/host-mingw32.cc b/gcc/config/i386/host-mingw32.cc index 4256398..b010be7 100644 --- a/gcc/config/i386/host-mingw32.cc +++ b/gcc/config/i386/host-mingw32.cc @@ -47,7 +47,7 @@ static inline void w32_error(const char*, const char*, int, const char*); /* Granularity for reserving address space. */ static size_t va_granularity = 0x10000; -/* Print out the GetLastError() translation. */ +/* Print out the GetLastError() translation. */ static inline void w32_error (const char* function, const char* file, int line, const char* my_msg) @@ -93,7 +93,7 @@ mingw32_gt_pch_get_address (size_t size, int) for NT system dlls is in 0x70000000 to 0x78000000 range. If we allocate at bottom we need to reserve the address as early as possible and at the same point in each invocation. */ - + res = VirtualAlloc (NULL, size, MEM_RESERVE | MEM_TOP_DOWN, PAGE_NOACCESS); @@ -103,11 +103,11 @@ mingw32_gt_pch_get_address (size_t size, int) /* We do not need the address space for now, so free it. */ VirtualFree (res, 0, MEM_RELEASE); - return res; + return res; } /* ADDR is an address returned by gt_pch_get_address. Attempt to allocate - SIZE bytes at the same address and load it with the data from FD at + SIZE bytes at the same address and load it with the data from FD at OFFSET. Return -1 if we couldn't allocate memory at ADDR, return 0 if the memory is allocated but the data not loaded, return 1 if done. */ @@ -117,10 +117,10 @@ mingw32_gt_pch_use_address (void *&addr, size_t size, int fd, { void * mmap_addr; HANDLE mmap_handle; - + /* Apparently, MS Vista puts unnamed file mapping objects into Global namespace when running an application in a Terminal Server - session. This causes failure since, by default, applications + session. This causes failure since, by default, applications don't get SeCreateGlobalPrivilege. We don't need global memory sharing so explicitly put object into Local namespace. @@ -140,10 +140,10 @@ mingw32_gt_pch_use_address (void *&addr, size_t size, int fd, version_info.dwOSVersionInfoSize = sizeof (version_info); if (size == 0) - return 0; + return 0; /* Offset must be also be a multiple of allocation granularity for - this to work. We can't change the offset. */ + this to work. We can't change the offset. */ if ((offset & (va_granularity - 1)) != 0) return -1; @@ -166,7 +166,7 @@ mingw32_gt_pch_use_address (void *&addr, size_t size, int fd, if (mmap_handle == NULL) { w32_error (__FUNCTION__, __FILE__, __LINE__, "CreateFileMapping"); - return -1; + return -1; } /* Retry five times, as here might occure a race with multiple gcc's @@ -180,7 +180,7 @@ mingw32_gt_pch_use_address (void *&addr, size_t size, int fd, if (r != 4) Sleep (500); } - + if (mmap_addr != addr) { w32_error (__FUNCTION__, __FILE__, __LINE__, "MapViewOfFileEx"); diff --git a/gcc/config/i386/i386-builtins.cc b/gcc/config/i386/i386-builtins.cc index a778f04..e12e758 100644 --- a/gcc/config/i386/i386-builtins.cc +++ b/gcc/config/i386/i386-builtins.cc @@ -1850,7 +1850,7 @@ get_builtin_code_for_version (tree decl, tree *predicate_list) target_node = ix86_valid_target_attribute_tree (decl, attrs, &global_options, &global_options_set, 0); - + gcc_assert (target_node); if (target_node == error_mark_node) return 0; @@ -1933,14 +1933,14 @@ get_builtin_code_for_version (tree decl, tree *predicate_list) cl_target_option_restore (&global_options, &global_options_set, &cur_target); - + if (predicate_list && arg_str == NULL) { error_at (DECL_SOURCE_LOCATION (decl), "no dispatcher found for the versioning attributes"); return 0; } - + if (predicate_list) { predicate_decl = ix86_builtins [(int) builtin_fn]; @@ -2008,7 +2008,7 @@ get_builtin_code_for_version (tree decl, tree *predicate_list) *predicate_list = predicate_chain; } - return priority; + return priority; } /* This builds the processor_model struct type defined in diff --git a/gcc/config/i386/i386-expand.cc b/gcc/config/i386/i386-expand.cc index a5094b5..36011cc 100644 --- a/gcc/config/i386/i386-expand.cc +++ b/gcc/config/i386/i386-expand.cc @@ -1010,7 +1010,7 @@ ix86_expand_vector_move_misalign (machine_mode mode, rtx operands[]) t = gen_reg_rtx (V4SFmode); else t = op0; - + if (TARGET_SSE_PARTIAL_REG_DEPENDENCY) emit_move_insn (t, CONST0_RTX (V4SFmode)); else @@ -1685,7 +1685,7 @@ ix86_emit_binop (enum rtx_code code, machine_mode mode, op = gen_rtx_SET (dst, gen_rtx_fmt_ee (code, mode, dst, src)); clob = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, FLAGS_REG)); - + emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, op, clob))); } @@ -5758,7 +5758,7 @@ ix86_expand_vec_perm (rtx operands[]) if (TARGET_XOP) { - /* The XOP VPPERM insn supports three inputs. By ignoring the + /* The XOP VPPERM insn supports three inputs. By ignoring the one_operand_shuffle special case, we avoid creating another set of constant vectors in memory. */ one_operand_shuffle = false; @@ -7586,7 +7586,7 @@ ix86_expand_v1ti_ashiftrt (rtx operands[]) rtx tmp7 = force_reg (V1TImode, gen_lowpart (V1TImode, tmp3)); rtx tmp8 = gen_reg_rtx (V1TImode); emit_insn (gen_sse2_ashlv1ti3 (tmp8, tmp7, GEN_INT (64))); - + rtx tmp9 = force_reg (V2DImode, gen_lowpart (V2DImode, tmp3)); rtx tmp10 = gen_reg_rtx (V2DImode); emit_insn (gen_ashlv2di3 (tmp10, tmp9, GEN_INT (128 - bits))); @@ -8582,7 +8582,7 @@ expand_small_cpymem_or_setmem (rtx destmem, rtx srcmem, DONE_LABEL is a label after the whole copying sequence. The label is created on demand if *DONE_LABEL is NULL. MIN_SIZE is minimal size of block copied. This value gets adjusted for new - bounds after the initial copies. + bounds after the initial copies. DESTMEM/SRCMEM are memory expressions pointing to the copies block, DESTPTR/SRCPTR are pointers to the block. DYNAMIC_CHECK indicate whether @@ -8891,7 +8891,7 @@ expand_set_or_cpymem_constant_prologue (rtx dst, rtx *srcp, rtx destreg, return dst; } -/* Return true if ALG can be used in current context. +/* Return true if ALG can be used in current context. Assume we expand memset if MEMSET is true. */ static bool alg_usable_p (enum stringop_alg alg, bool memset, bool have_as) @@ -9257,7 +9257,7 @@ ix86_copy_addr_to_reg (rtx addr) with specified algorithm. 4) Epilogue: code copying tail of the block that is too small to be - handled by main body (or up to size guarded by prologue guard). + handled by main body (or up to size guarded by prologue guard). Misaligned move sequence @@ -9475,7 +9475,7 @@ ix86_expand_set_or_cpymem (rtx dst, rtx src, rtx count_exp, rtx val_exp, /* Do the cheap promotion to allow better CSE across the main loop and epilogue (ie one load of the big constant in the - front of all code. + front of all code. For now the misaligned move sequences do not have fast path without broadcasting. */ if (issetmem && ((CONST_INT_P (val_exp) || misaligned_prologue_used))) @@ -13793,7 +13793,7 @@ ix86_expand_builtin (tree exp, rtx target, rtx subtarget, if (!REG_P (op2)) op2 = copy_to_mode_reg (SImode, op2); - emit_insn (fcode == IX86_BUILTIN_MONITOR + emit_insn (fcode == IX86_BUILTIN_MONITOR ? gen_sse3_monitor (Pmode, op0, op1, op2) : gen_monitorx (Pmode, op0, op1, op2)); return 0; @@ -16096,7 +16096,7 @@ static const ix86_vec_bcast_map_simode_t ix86_vec_bcast_map_simode[] = { }; /* Comparator for bsearch on ix86_vec_bcast_map. */ -static int +static int ix86_vec_bcast_map_simode_cmp (const void *key, const void *entry) { return (*(const unsigned int*)key) @@ -25312,7 +25312,7 @@ ix86_expand_sse2_mulvxdi3 (rtx op0, rtx op1, rtx op2) /* Multiply lower parts and add all */ t5 = gen_reg_rtx (V2DImode); - emit_insn (gen_vec_widen_umult_even_v4si (t5, + emit_insn (gen_vec_widen_umult_even_v4si (t5, gen_lowpart (V4SImode, op1), gen_lowpart (V4SImode, op2))); force_expand_binop (mode, add_optab, t5, t4, op0, 1, OPTAB_DIRECT); @@ -25507,7 +25507,7 @@ ix86_expand_pextr (rtx *operands) return false; dst = SUBREG_REG (dst); } - + if (SUBREG_P (src)) { pos += SUBREG_BYTE (src) * BITS_PER_UNIT; @@ -26122,7 +26122,7 @@ ix86_gen_bcst_mem (machine_mode mode, rtx x) && !CONST_DOUBLE_P (cst) && !CONST_FIXED_P (cst)) return NULL_RTX; - + int n_elts = GET_MODE_NUNITS (mode); if (CONST_VECTOR_NUNITS (x) != n_elts) return NULL_RTX; @@ -26290,7 +26290,7 @@ do_mem_operand: /* Return TRUE if OP (in mode MODE) is the leaf of a ternary logic expression, such as a register or a memory reference. */ - + bool ix86_ternlog_leaf_p (rtx op, machine_mode mode) { @@ -26479,7 +26479,7 @@ ix86_expand_ternlog (machine_mode mode, rtx op0, rtx op1, rtx op2, int idx, return target; } break; - + case 0x22: /* ~b&c */ if ((!op0 || !side_effects_p (op0)) && op1 && register_operand (op1, mode) @@ -26552,7 +26552,7 @@ ix86_expand_ternlog (machine_mode mode, rtx op0, rtx op1, rtx op2, int idx, return target; } break; - + case 0x5a: /* a^c */ if (op0 && ix86_ternlog_leaf_p (op0, mode) && op2 && ix86_ternlog_leaf_p (op2, mode) diff --git a/gcc/config/i386/i386-features.cc b/gcc/config/i386/i386-features.cc index 16b1e6c..e2e8521 100644 --- a/gcc/config/i386/i386-features.cc +++ b/gcc/config/i386/i386-features.cc @@ -351,7 +351,7 @@ scalar_chain::mark_dual_mode_def (df_ref def) return; n_sse_to_integer++; } - + if (dump_file) fprintf (dump_file, " Mark r%d def in insn %d as requiring both modes in chain #%d\n", @@ -3658,7 +3658,7 @@ ix86_compare_version_priority (tree decl1, tree decl2) /* V1 and V2 point to function versions with different priorities based on the target ISA. This function compares their priorities. */ - + static int feature_compare (const void *v1, const void *v2) { @@ -3707,7 +3707,7 @@ add_condition_to_bb (tree function_decl, tree version_decl, convert_expr = build1 (CONVERT_EXPR, ptr_type_node, build_fold_addr_expr (version_decl)); result_var = create_tmp_var (ptr_type_node); - convert_stmt = gimple_build_assign (result_var, convert_expr); + convert_stmt = gimple_build_assign (result_var, convert_expr); return_stmt = gimple_build_return (result_var); if (predicate_chain == NULL_TREE) @@ -3734,7 +3734,7 @@ add_condition_to_bb (tree function_decl, tree version_decl, gimple_seq_add_stmt (&gseq, call_cond_stmt); predicate_chain = TREE_CHAIN (predicate_chain); - + if (and_expr_var == NULL) and_expr_var = cond_var; else @@ -3775,7 +3775,7 @@ add_condition_to_bb (tree function_decl, tree version_decl, gimple_set_bb (return_stmt, bb2); bb3 = e23->dest; - make_edge (bb1, bb3, EDGE_FALSE_VALUE); + make_edge (bb1, bb3, EDGE_FALSE_VALUE); remove_edge (e23); make_edge (bb2, EXIT_BLOCK_PTR_FOR_FN (cfun), 0); @@ -3936,7 +3936,7 @@ ix86_mangle_function_version_assembler_name (tree decl, tree id) return ret; } -tree +tree ix86_mangle_decl_assembler_name (tree decl, tree id) { /* For function version, add the target suffix to the assembler name. */ @@ -3966,7 +3966,7 @@ ix86_get_function_versions_dispatcher (void *decl) tree dispatch_decl = NULL; struct cgraph_function_version_info *default_version_info = NULL; - + gcc_assert (fn != NULL && DECL_FUNCTION_VERSIONED (fn)); node = cgraph_node::get (fn); @@ -3974,7 +3974,7 @@ ix86_get_function_versions_dispatcher (void *decl) node_v = node->function_version (); gcc_assert (node_v != NULL); - + if (node_v->dispatcher_resolver != NULL) return node_v->dispatcher_resolver; @@ -4130,7 +4130,7 @@ make_resolver_func (const tree default_decl, provide the code to dispatch the right function at run-time. NODE points to the dispatcher decl whose body will be created. */ -tree +tree ix86_generate_version_dispatcher_body (void *node_p) { tree resolver_decl; diff --git a/gcc/config/i386/i386-options.cc b/gcc/config/i386/i386-options.cc index 5fa6e02..38037de 100644 --- a/gcc/config/i386/i386-options.cc +++ b/gcc/config/i386/i386-options.cc @@ -755,7 +755,7 @@ static unsigned HOST_WIDE_INT initial_ix86_arch_features[X86_ARCH_LAST] = { ~m_386, }; -/* This table must be in sync with enum processor_type in i386.h. */ +/* This table must be in sync with enum processor_type in i386.h. */ static const struct processor_costs *processor_cost_table[] = { &generic_cost, @@ -1546,9 +1546,9 @@ ix86_valid_target_attribute_p (tree fndecl, tree old_optimize = build_optimization_node (&global_options, &global_options_set); - /* Get the optimization options of the current function. */ + /* Get the optimization options of the current function. */ tree func_optimize = DECL_FUNCTION_SPECIFIC_OPTIMIZATION (fndecl); - + if (!func_optimize) func_optimize = old_optimize; @@ -2837,7 +2837,7 @@ ix86_option_override_internal (bool main_args_p, /* For all chips supporting SSE2, -mfpmath=sse performs better than fpmath=387. The second is however default at many targets since the extra 80bit precision of temporaries is considered to be part of ABI. - Overwrite the default at least for -ffast-math. + Overwrite the default at least for -ffast-math. TODO: -mfpmath=both seems to produce same performing code with bit smaller binaries. It is however not clear if register allocation is ready for this setting. diff --git a/gcc/config/i386/i386-opts.h b/gcc/config/i386/i386-opts.h index c7ec0d9..35542b2 100644 --- a/gcc/config/i386/i386-opts.h +++ b/gcc/config/i386/i386-opts.h @@ -29,7 +29,7 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see enum stringop_alg { #undef DEF_ALG -#define DEF_ALG(alg, name) alg, +#define DEF_ALG(alg, name) alg, #include "stringop.def" last_alg diff --git a/gcc/config/i386/i386.cc b/gcc/config/i386/i386.cc index 9e5a6c0..473e4cb 100644 --- a/gcc/config/i386/i386.cc +++ b/gcc/config/i386/i386.cc @@ -512,7 +512,7 @@ ix86_conditional_register_usage (void) /* See the definition of CALL_USED_REGISTERS in i386.h. */ c_mask = CALL_USED_REGISTERS_MASK (TARGET_64BIT_MS_ABI); - + CLEAR_HARD_REG_SET (reg_class_contents[(int)CLOBBERED_REGS]); for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) @@ -1940,7 +1940,7 @@ init_cumulative_args (CUMULATIVE_ARGS *cum, /* Argument info to initialize */ The midde-end can't deal with the vector types > 16 bytes. In this case, we return the original mode and warn ABI change if CUM isn't - NULL. + NULL. If INT_RETURN is true, warn ABI change if the vector mode isn't available for function return value. */ @@ -4270,7 +4270,7 @@ ix86_function_value_1 (const_tree valtype, const_tree fntype_or_decl, if (fntype_or_decl && DECL_P (fntype_or_decl)) fn = fntype_or_decl; fntype = fn ? TREE_TYPE (fn) : fntype_or_decl; - + if (ix86_function_type_abi (fntype) == MS_ABI) { if (TARGET_64BIT) @@ -4388,7 +4388,7 @@ ix86_return_in_memory (const_tree type, const_tree fntype ATTRIBUTE_UNUSED) /* Unless ABI prescibes otherwise, MMX/3dNow values are returned in MM0 if available. */ - + if (size == 8) return TARGET_VECT8_RETURNS || !TARGET_MMX; @@ -4507,7 +4507,7 @@ ix86_build_builtin_va_list (void) /* For SYSV_ABI we use an array of one record. */ sysv_va_list_type_node = ix86_build_builtin_va_list_64 (); - + /* For MS_ABI we use plain pointer to argument area. */ tree char_ptr_type = build_pointer_type (char_type_node); tree attr = tree_cons (get_identifier ("ms_abi va_list"), NULL_TREE, @@ -5464,7 +5464,7 @@ standard_sse_constant_opcode (rtx_insn *insn, rtx *operands) && float_vector_all_ones_operand (x, mode))) { enum attr_mode insn_mode = get_attr_mode (insn); - + switch (insn_mode) { case MODE_XI: @@ -5984,7 +5984,7 @@ ix86_frame_pointer_required (void) /* SSE saves require frame-pointer when stack is misaligned. */ if (TARGET_64BIT_MS_ABI && ix86_incoming_stack_boundary < 128) return true; - + /* In ix86_option_override_internal, TARGET_OMIT_LEAF_FRAME_POINTER turns off the frame pointer by default. Turn it back on now if we've not got a leaf function. */ @@ -10791,7 +10791,7 @@ ix86_decompose_address (rtx addr, struct ix86_address *out) addr = XEXP (addr, 0); if (CONST_INT_P (addr)) return false; - } + } else if (GET_CODE (addr) == AND && const_32bit_mask (XEXP (addr, 1), DImode)) { @@ -13647,7 +13647,7 @@ ix86_print_operand (FILE *file, rtx x, int code) case 2: putc ('w', file); break; - + case 4: putc ('l', file); break; @@ -16008,7 +16008,7 @@ ix86_avoid_lea_for_addr (rtx_insn *insn, rtx operands[]) if (optimize_size > 1 && parts.scale > 1 && !parts.base - && (!parts.disp || parts.disp == const0_rtx)) + && (!parts.disp || parts.disp == const0_rtx)) return true; /* Check we need to optimize. */ @@ -17169,7 +17169,7 @@ ix86_output_call_insn (rtx_insn *insn, rtx call_op) seh_nop_p = true; break; } - + /* If we get to another real insn, we don't need the nop. */ if (INSN_P (i)) break; @@ -17759,7 +17759,7 @@ ix86_dependencies_evaluation_hook (rtx_insn *head, rtx_insn *tail) using topological ordering in the region. */ if (rgn == CONTAINING_RGN (e->src->index) && BLOCK_TO_BB (bb->index) > BLOCK_TO_BB (e->src->index)) - add_dependee_for_func_arg (first_arg, e->src); + add_dependee_for_func_arg (first_arg, e->src); } } insn = first_arg; @@ -18131,7 +18131,7 @@ ix86_local_alignment (tree exp, machine_mode mode, other unit cannot rely on the alignment. Exclude va_list type. It is the common case of local array where - we cannot benefit from the alignment. + we cannot benefit from the alignment. TODO: Probably one should optimize for size only when var is not escaping. */ if (TARGET_64BIT && optimize_function_for_speed_p (cfun) @@ -22281,7 +22281,7 @@ ix86_rtx_costs (rtx x, machine_mode mode, int outer_code_i, int opno, *total = COSTS_N_BYTES (1); else if (TARGET_SLOW_STC) *total = COSTS_N_INSNS (2); - else + else *total = COSTS_N_INSNS (1); return true; } @@ -25824,7 +25824,7 @@ extract_base_offset_in_addr (rtx mem, rtx *base, rtx *symbase, rtx *offset) gcc_assert (MEM_P (mem)); addr = XEXP (mem, 0); - + if (GET_CODE (addr) == CONST) addr = XEXP (addr, 0); diff --git a/gcc/config/i386/i386.h b/gcc/config/i386/i386.h index f3c98f5..2dcd880 100644 --- a/gcc/config/i386/i386.h +++ b/gcc/config/i386/i386.h @@ -545,7 +545,7 @@ extern GTY(()) tree x86_mfence; #define TARGET_SUBTARGET64_ISA_DEFAULT \ (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_SSE2) -/* Replace MACH-O, ifdefs by in-line tests, where possible. +/* Replace MACH-O, ifdefs by in-line tests, where possible. (a) Macros defined in config/i386/darwin.h */ #define TARGET_MACHO 0 #define TARGET_MACHO_SYMBOL_STUBS 0 @@ -1574,11 +1574,11 @@ enum reg_class /* If defined, the maximum amount of space required for outgoing arguments will be computed and placed into the variable `crtl->outgoing_args_size'. No space will be pushed onto the stack for each call; instead, the - function prologue should increase the stack frame size by this amount. + function prologue should increase the stack frame size by this amount. In 32bit mode enabling argument accumulation results in about 5% code size growth because move instructions are less compact than push. In 64bit - mode the difference is less drastic but visible. + mode the difference is less drastic but visible. FIXME: Unlike earlier implementations, the size of unwind info seems to actually grow with accumulation. Is that because accumulated args diff --git a/gcc/config/i386/openbsdelf.h b/gcc/config/i386/openbsdelf.h index 89982b9..01de0fc 100644 --- a/gcc/config/i386/openbsdelf.h +++ b/gcc/config/i386/openbsdelf.h @@ -1,5 +1,5 @@ /* Configuration for an OpenBSD i386 target. - + Copyright (C) 2005-2024 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/smmintrin.h b/gcc/config/i386/smmintrin.h index 4c315fe..c2d8277 100644 --- a/gcc/config/i386/smmintrin.h +++ b/gcc/config/i386/smmintrin.h @@ -385,7 +385,7 @@ _mm_extract_ps (__m128 __X, const int __N) by index N. */ #define _MM_EXTRACT_FLOAT(D, S, N) \ { (D) = __builtin_ia32_vec_ext_v4sf ((__v4sf)(S), (N)); } - + /* Extract specified single precision float element into the lower part of __m128. */ #define _MM_PICK_OUT_PS(X, N) \ diff --git a/gcc/config/i386/sol2.h b/gcc/config/i386/sol2.h index b93bc4c..f51fb2e 100644 --- a/gcc/config/i386/sol2.h +++ b/gcc/config/i386/sol2.h @@ -80,7 +80,7 @@ along with GCC; see the file COPYING3. If not see #define ASM_CPU_SPEC "%(asm_cpu_default) " ASM_XBRACE_COMMENT_SPEC /* Don't include ASM_PIC_SPEC. While the Solaris 10+ assembler accepts -K PIC, - it gives many warnings: + it gives many warnings: Absolute relocation is used for symbol "<symbol>" GNU as doesn't recognize -K at all. */ #undef ASM_SPEC diff --git a/gcc/config/i386/stringop.def b/gcc/config/i386/stringop.def index 07de314..7de514d 100644 --- a/gcc/config/i386/stringop.def +++ b/gcc/config/i386/stringop.def @@ -13,7 +13,7 @@ but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. -You should have received a copy of the GNU General Public License +You should have received a copy of the GNU General Public License along with GCC; see the files COPYING3. If not, see <http://www.gnu.org/licenses/>. */ diff --git a/gcc/config/i386/wmmintrin.h b/gcc/config/i386/wmmintrin.h index 34ddd3e..c9ebbb9 100644 --- a/gcc/config/i386/wmmintrin.h +++ b/gcc/config/i386/wmmintrin.h @@ -38,17 +38,17 @@ #define __DISABLE_AES__ #endif /* __AES__ */ -/* Performs 1 round of AES decryption of the first m128i using +/* Performs 1 round of AES decryption of the first m128i using the second m128i as a round key. */ #define _mm_aesdec_si128(X, Y) \ (__m128i) __builtin_ia32_aesdec128 ((__v2di) (X), (__v2di) (Y)) -/* Performs the last round of AES decryption of the first m128i +/* Performs the last round of AES decryption of the first m128i using the second m128i as a round key. */ #define _mm_aesdeclast_si128(X, Y) \ (__m128i) __builtin_ia32_aesdeclast128 ((__v2di) (X), (__v2di) (Y)) -/* Performs 1 round of AES encryption of the first m128i using +/* Performs 1 round of AES encryption of the first m128i using the second m128i as a round key. */ #define _mm_aesenc_si128(X, Y) \ (__m128i) __builtin_ia32_aesenc128 ((__v2di) (X), (__v2di) (Y)) @@ -58,7 +58,7 @@ #define _mm_aesenclast_si128(X, Y) \ (__m128i) __builtin_ia32_aesenclast128 ((__v2di) (X), (__v2di) (Y)) -/* Performs the InverseMixColumn operation on the source m128i +/* Performs the InverseMixColumn operation on the source m128i and stores the result into m128i destination. */ extern __inline __m128i __attribute__((__gnu_inline__, __always_inline__, __artificial__)) _mm_aesimc_si128 (__m128i __X) diff --git a/gcc/config/ia64/freebsd.h b/gcc/config/ia64/freebsd.h index c1eb8d5..bc8366b 100644 --- a/gcc/config/ia64/freebsd.h +++ b/gcc/config/ia64/freebsd.h @@ -36,7 +36,7 @@ along with GCC; see the file COPYING3. If not see /************************[ Target stuff ]***********************************/ -/* Define the actual types of some ANSI-mandated types. +/* Define the actual types of some ANSI-mandated types. Needs to agree with <machine/ansi.h>. GCC defaults come from c-decl.cc, c-common.cc, and config/<arch>/<arch>.h. */ diff --git a/gcc/config/ia64/ia64.cc b/gcc/config/ia64/ia64.cc index 54706da..4acbd82 100644 --- a/gcc/config/ia64/ia64.cc +++ b/gcc/config/ia64/ia64.cc @@ -352,7 +352,7 @@ struct expand_vec_perm_d machine_mode vmode; unsigned char nelt; bool one_operand_p; - bool testing_p; + bool testing_p; }; static bool ia64_expand_vec_perm_const_1 (struct expand_vec_perm_d *d); @@ -815,7 +815,7 @@ ia64_vms_common_object_attribute (tree *node, tree name, tree args, tree id; gcc_assert (DECL_P (decl)); - + DECL_COMMON (decl) = 1; id = TREE_VALUE (args); if (TREE_CODE (id) != IDENTIFIER_NODE && TREE_CODE (id) != STRING_CST) @@ -1042,7 +1042,7 @@ ia64_legitimate_address_p (machine_mode mode ATTRIBUTE_UNUSED, rtx x, return true; else if ((GET_CODE (x) == POST_INC || GET_CODE (x) == POST_DEC) && ia64_legitimate_address_reg (XEXP (x, 0), strict) - && XEXP (x, 0) != arg_pointer_rtx) + && XEXP (x, 0) != arg_pointer_rtx) return true; else if (GET_CODE (x) == POST_MODIFY && ia64_legitimate_address_reg (XEXP (x, 0), strict) @@ -1356,7 +1356,7 @@ ia64_expand_move (rtx op0, rtx op1) else if (aligned_offset_symbol_operand (sym, mode)) { HOST_WIDE_INT addend_lo, addend_hi; - + addend_lo = ((addend & 0x3fff) ^ 0x2000) - 0x2000; addend_hi = addend - addend_lo; @@ -1441,7 +1441,7 @@ ia64_split_tmode (rtx out[2], rtx in, bool reversed, bool dead) case CONST_DOUBLE: /* Cannot occur reversed. */ gcc_assert (!reversed); - + if (GET_MODE (in) != TFmode) split_double (in, &out[0], &out[1]); else @@ -1496,7 +1496,7 @@ ia64_split_tmode (rtx out[2], rtx in, bool reversed, bool dead) case POST_INC: gcc_assert (!reversed && !dead); - + /* Just do the increment in two steps. */ out[0] = adjust_automodify_address (in, DImode, 0, 0); out[1] = adjust_automodify_address (in, DImode, 0, 8); @@ -1504,7 +1504,7 @@ ia64_split_tmode (rtx out[2], rtx in, bool reversed, bool dead) case POST_DEC: gcc_assert (!reversed && !dead); - + /* Add 8, subtract 24. */ base = XEXP (base, 0); out[0] = adjust_automodify_address @@ -1592,7 +1592,7 @@ ia64_split_tmode_move (rtx operands[]) the appropriate order so that the pointer is not destroyed too early. Also we must not generate a postmodify for that second load, or rws_access_regno will die. And we must not generate a - postmodify for the second load if the destination register + postmodify for the second load if the destination register overlaps with the base register. */ if (GET_CODE (operands[1]) == MEM && reg_overlap_mentioned_p (operands[0], operands[1])) @@ -1838,7 +1838,7 @@ ia64_expand_compare (rtx *expr, rtx *op0, rtx *op1) int magic; enum rtx_code ncode; rtx ret; - + gcc_assert (cmptf_libfunc && GET_MODE (*op1) == TFmode); switch (code) { @@ -2862,7 +2862,7 @@ ia64_compute_frame_size (HOST_WIDE_INT size) if (df_regs_ever_live_p (AR_PFS_REGNUM)) { SET_HARD_REG_BIT (mask, AR_PFS_REGNUM); - current_frame_info.r[reg_save_ar_pfs] + current_frame_info.r[reg_save_ar_pfs] = find_gr_spill (reg_save_ar_pfs, 1); if (current_frame_info.r[reg_save_ar_pfs] == 0) { @@ -2877,8 +2877,8 @@ ia64_compute_frame_size (HOST_WIDE_INT size) it is absolutely critical that FP get the only hard register that's guaranteed to be free, so we allocated it first. If all three did happen to be allocated hard regs, and are consecutive, rearrange them - into the preferred order now. - + into the preferred order now. + If we have already emitted code for any of those registers, then it's already too late to change. */ min_regno = MIN (current_frame_info.r[reg_fp], @@ -2932,7 +2932,7 @@ ia64_compute_frame_size (HOST_WIDE_INT size) { df_set_regs_ever_live (AR_UNAT_REGNUM, true); SET_HARD_REG_BIT (mask, AR_UNAT_REGNUM); - current_frame_info.r[reg_save_ar_unat] + current_frame_info.r[reg_save_ar_unat] = find_gr_spill (reg_save_ar_unat, spill_size == 0); if (current_frame_info.r[reg_save_ar_unat] == 0) { @@ -2944,7 +2944,7 @@ ia64_compute_frame_size (HOST_WIDE_INT size) if (df_regs_ever_live_p (AR_LC_REGNUM)) { SET_HARD_REG_BIT (mask, AR_LC_REGNUM); - current_frame_info.r[reg_save_ar_lc] + current_frame_info.r[reg_save_ar_lc] = find_gr_spill (reg_save_ar_lc, spill_size == 0); if (current_frame_info.r[reg_save_ar_lc] == 0) { @@ -3531,7 +3531,7 @@ ia64_expand_prologue (void) ia64_emit_probe_stack_range (get_stack_check_protect (), size, bs_size); } - if (dump_file) + if (dump_file) { fprintf (dump_file, "ia64 frame related registers " "recorded in current_frame_info.r[]:\n"); @@ -4145,7 +4145,7 @@ ia64_expand_epilogue (int sibcall_p) names of r2 and HARD_FRAME_POINTER_REGNUM, so we have to make sure we're using the string "r2" when emitting the register name for the assembler. */ - if (current_frame_info.r[reg_fp] + if (current_frame_info.r[reg_fp] && current_frame_info.r[reg_fp] == GR_REG (2)) fp = HARD_FRAME_POINTER_REGNUM; @@ -4272,7 +4272,7 @@ ia64_hard_regno_rename_ok (int from, int to) unsigned int r; for (r = reg_fp; r <= reg_save_ar_lc; r++) - if (to == current_frame_info.r[r] + if (to == current_frame_info.r[r] || from == current_frame_info.r[r] || to == emitted_frame_related_regs[r] || from == emitted_frame_related_regs[r]) @@ -4881,7 +4881,7 @@ ia64_function_arg_1 (cumulative_args_t cum_v, const function_arg_info &arg, } return gen_rtx_PARALLEL (arg.mode, gen_rtvec_v (i, loc)); } - + /* Integral and aggregates go in general registers. If we have run out of FR registers, then FP values must also go in general registers. This can happen when we have a SFmode HFA. */ @@ -5231,7 +5231,7 @@ ia64_function_value (const_tree valtype, if (fn_decl_or_type && !DECL_P (fn_decl_or_type)) func = NULL; - + mode = TYPE_MODE (valtype); hfa_mode = hfa_element_mode (valtype, 0); @@ -5877,7 +5877,7 @@ ia64_preferred_reload_class (rtx x, reg_class_t rclass) of the f/f case when reloading (set (reg fX) (mem/v)). */ if (MEM_P (x) && MEM_VOLATILE_P (x)) return NO_REGS; - + /* Force all unrecognized constants into the constant pool. */ if (CONSTANT_P (x)) return NO_REGS; @@ -6487,7 +6487,7 @@ update_set_flags (rtx x, struct reg_flags *pflags) doloop_end_internal, (3) The destination is an fp register, in which case this is an fselect instruction. - (4) The condition has (unspec [(reg)] UNSPEC_LDC), in which case + (4) The condition has (unspec [(reg)] UNSPEC_LDC), in which case this is a check load. In all cases, nothing we do in this function applies. */ return; @@ -6539,12 +6539,12 @@ set_src_needs_barrier (rtx x, struct reg_flags flags, int pred) } if (ia64_spec_check_src_p (src)) - /* Avoid checking one register twice (in condition + /* Avoid checking one register twice (in condition and in 'then' section) for ldc pattern. */ { gcc_assert (REG_P (XEXP (src, 2))); need_barrier = rtx_needs_barrier (XEXP (src, 2), flags, pred); - + /* We process MEM below. */ src = XEXP (src, 1); } @@ -7435,7 +7435,7 @@ static void ia64_sched_init_global (FILE *dump ATTRIBUTE_UNUSED, int sched_verbose ATTRIBUTE_UNUSED, int max_ready ATTRIBUTE_UNUSED) -{ +{ gcc_assert (pending_data_specs == 0); } @@ -7640,7 +7640,7 @@ ia64_variable_issue (FILE *dump ATTRIBUTE_UNUSED, if (reload_completed) { int needed = group_barrier_needed (insn); - + gcc_assert (!needed); if (CALL_P (insn)) init_insn_group_barriers (); @@ -7774,7 +7774,7 @@ ia64_dfa_new_cycle (FILE *dump, int verbose, rtx_insn *insn, int last_clock, static void ia64_h_i_d_extended (void) { - if (stops_p != NULL) + if (stops_p != NULL) { int new_clocks_length = get_max_uid () * 3 / 2; stops_p = (char *) xrecalloc (stops_p, new_clocks_length, clocks_length, 1); @@ -7861,7 +7861,7 @@ static void ia64_clear_sched_context (void *_sc) { ia64_sched_context_t sc = (ia64_sched_context_t) _sc; - + free (sc->prev_cycle_state); sc->prev_cycle_state = NULL; } @@ -8040,13 +8040,13 @@ ia64_set_sched_flags (spec_info_t spec_info) || (mflag_sched_ar_in_data_spec && reload_completed))) mask |= BE_IN_DATA; } - + if (mflag_sched_control_spec && (!sel_sched_p () || reload_completed)) { mask |= BEGIN_CONTROL; - + if (!sel_sched_p () && mflag_sched_in_control_spec) mask |= BE_IN_CONTROL; } @@ -8059,9 +8059,9 @@ ia64_set_sched_flags (spec_info_t spec_info) if (mask & BE_IN_SPEC) *flags |= NEW_BBS; - + spec_info->flags = 0; - + if ((mask & CONTROL_SPEC) && sel_sched_p () && mflag_sel_sched_dont_check_control_spec) spec_info->flags |= SEL_SCHED_SPEC_DONT_CHECK_CONTROL; @@ -8070,7 +8070,7 @@ ia64_set_sched_flags (spec_info_t spec_info) spec_info->dump = sched_dump; else spec_info->dump = 0; - + if (mflag_sched_count_spec_in_critical_path) spec_info->flags |= COUNT_SPEC_IN_CRITICAL_PATH; } @@ -8317,10 +8317,10 @@ insn_can_be_in_speculative_p (rtx insn ATTRIBUTE_UNUSED, return 0. */ static int ia64_speculate_insn (rtx_insn *insn, ds_t ts, rtx *new_pat) -{ +{ int mode_no; int res; - + gcc_assert (!(ts & ~SPECULATIVE)); if (ia64_spec_check_p (insn)) @@ -8507,12 +8507,12 @@ ia64_gen_spec_check (rtx_insn *insn, rtx_insn *label, ds_t ds) gcc_assert (!ia64_needs_block_p (ds)); op1 = copy_rtx (recog_data.operand[1]); } - + gen_check = get_spec_check_gen_function (ds, mode_no, label == NULL_RTX, true); check_pat = gen_check (copy_rtx (recog_data.operand[0]), op1); - + pat = PATTERN (insn); if (GET_CODE (pat) == COND_EXEC) check_pat = gen_rtx_COND_EXEC (VOIDmode, copy_rtx (COND_EXEC_TEST (pat)), @@ -8544,14 +8544,14 @@ ia64_spec_check_src_p (rtx src) t = XEXP (src, 0); if (GET_CODE (t) == NE) { - t = XEXP (t, 0); + t = XEXP (t, 0); if (GET_CODE (t) == UNSPEC) { int code; - + code = XINT (t, 1); - + if (code == UNSPEC_LDCCLR || code == UNSPEC_LDCNC || code == UNSPEC_CHKACLR @@ -9263,7 +9263,7 @@ bundling (FILE *dump, int verbose, rtx_insn *prev_head_insn, rtx_insn *tail) INSN_UID (insn)); } } - + /* We should find a solution because the 2nd insn scheduling has found one. */ gcc_assert (index_to_bundle_states [insn_num]); @@ -9643,7 +9643,7 @@ ia64_st_address_bypass_p (rtx_insn *producer, rtx_insn *consumer) if (GET_CODE (reg) == SUBREG) reg = SUBREG_REG (reg); gcc_assert (GET_CODE (reg) == REG); - + dest = ia64_single_set (consumer); gcc_assert (dest); mem = SET_DEST (dest); @@ -9667,12 +9667,12 @@ ia64_ld_address_bypass_p (rtx_insn *producer, rtx_insn *consumer) if (GET_CODE (reg) == SUBREG) reg = SUBREG_REG (reg); gcc_assert (GET_CODE (reg) == REG); - + src = ia64_single_set (consumer); gcc_assert (src); mem = SET_SRC (src); gcc_assert (mem); - + if (GET_CODE (mem) == UNSPEC && XVECLEN (mem, 0) > 0) mem = XVECEXP (mem, 0, 0); else if (GET_CODE (mem) == IF_THEN_ELSE) @@ -9681,7 +9681,7 @@ ia64_ld_address_bypass_p (rtx_insn *producer, rtx_insn *consumer) gcc_assert (XINT (XEXP (XEXP (mem, 0), 0), 1) == UNSPEC_LDCCLR); mem = XEXP (mem, 1); } - + while (GET_CODE (mem) == SUBREG || GET_CODE (mem) == ZERO_EXTEND) mem = XEXP (mem, 0); @@ -9889,7 +9889,7 @@ ia64_reorg (void) emit_all_insn_group_barriers (dump_file); df_analyze (); - + /* A call must not be the last instruction in a function, so that the return address is still within the function, so that unwinding works properly. Note that IA-64 differs from dwarf2 on this point. */ @@ -10089,9 +10089,9 @@ process_cfa_adjust_cfa (FILE *out_file, rtx pat, rtx insn, { rtx op0 = XEXP (src, 0); rtx op1 = XEXP (src, 1); - + gcc_assert (op0 == dest && GET_CODE (op1) == CONST_INT); - + if (INTVAL (op1) < 0) { gcc_assert (!frame_pointer_needed); @@ -10919,7 +10919,7 @@ ia64_struct_retval_addr_is_first_parm_p (tree fntype) these return values. */ return (abi_version_at_least (2) && ret_type - && TYPE_MODE (ret_type) == BLKmode + && TYPE_MODE (ret_type) == BLKmode && TREE_ADDRESSABLE (ret_type) && lang_GNU_CXX ()); } @@ -11511,7 +11511,7 @@ expand_vec_perm_shrp (struct expand_vec_perm_d *d) static bool expand_vec_perm_1 (struct expand_vec_perm_d *d) -{ +{ unsigned i, nelt = d->nelt; unsigned char perm2[MAX_VECT_LEN]; @@ -11548,8 +11548,8 @@ expand_vec_perm_1 (struct expand_vec_perm_d *d) if (expand_vec_perm_shrp (d)) return true; - /* ??? Look for deposit-like permutations where most of the result - comes from one vector unchanged and the rest comes from a + /* ??? Look for deposit-like permutations where most of the result + comes from one vector unchanged and the rest comes from a sequential hunk of the other vector. */ return false; @@ -11636,7 +11636,7 @@ expand_vec_perm_interleave_2 (struct expand_vec_perm_d *d) h1 = h0 << nelt2; h2 = h0 << nelt; h3 = h0 << (nelt + nelt2); - + if ((contents & (h0 | h2)) == contents) /* punpck even halves */ { for (i = 0; i < nelt; ++i) @@ -11901,7 +11901,7 @@ ia64_expand_vec_setv2sf (rtx operands[3]) struct expand_vec_perm_d d; unsigned int which; bool ok; - + d.target = operands[0]; d.op0 = operands[0]; d.op1 = gen_reg_rtx (V2SFmode); diff --git a/gcc/config/iq2000/iq2000.cc b/gcc/config/iq2000/iq2000.cc index 136675d..42935d3 100644 --- a/gcc/config/iq2000/iq2000.cc +++ b/gcc/config/iq2000/iq2000.cc @@ -1572,7 +1572,7 @@ final_prescan_insn (rtx_insn *insn, rtx opvec[] ATTRIBUTE_UNUSED, rtx_insn *nop_insn = emit_insn_after (gen_nop (), insn); INSN_ADDRESSES_NEW (nop_insn, -1); } - + if (TARGET_STATS && (JUMP_P (insn) || CALL_P (insn))) dslots_jump_total ++; @@ -1684,7 +1684,7 @@ compute_frame_size (HOST_WIDE_INT size) gp_reg_rounded = IQ2000_STACK_ALIGN (gp_reg_size); total_size += gp_reg_rounded + IQ2000_STACK_ALIGN (fp_reg_size); - /* The gp reg is caller saved, so there is no need for leaf routines + /* The gp reg is caller saved, so there is no need for leaf routines (total_size == extra_size) to save the gp reg. */ if (total_size == extra_size && ! profile_flag) @@ -1751,18 +1751,18 @@ iq2000_initial_elimination_offset (int from, int to ATTRIBUTE_UNUSED) { int offset; - compute_frame_size (get_frame_size ()); - if ((from) == FRAME_POINTER_REGNUM) - (offset) = 0; - else if ((from) == ARG_POINTER_REGNUM) - (offset) = (cfun->machine->total_size); - else if ((from) == RETURN_ADDRESS_POINTER_REGNUM) + compute_frame_size (get_frame_size ()); + if ((from) == FRAME_POINTER_REGNUM) + (offset) = 0; + else if ((from) == ARG_POINTER_REGNUM) + (offset) = (cfun->machine->total_size); + else if ((from) == RETURN_ADDRESS_POINTER_REGNUM) { - if (leaf_function_p ()) - (offset) = 0; - else (offset) = cfun->machine->gp_sp_offset - + ((UNITS_PER_WORD - (POINTER_SIZE / BITS_PER_UNIT)) - * (BYTES_BIG_ENDIAN != 0)); + if (leaf_function_p ()) + (offset) = 0; + else (offset) = cfun->machine->gp_sp_offset + + ((UNITS_PER_WORD - (POINTER_SIZE / BITS_PER_UNIT)) + * (BYTES_BIG_ENDIAN != 0)); } else gcc_unreachable (); @@ -1771,7 +1771,7 @@ iq2000_initial_elimination_offset (int from, int to ATTRIBUTE_UNUSED) } /* Common code to emit the insns (or to write the instructions to a file) - to save/restore registers. + to save/restore registers. Other parts of the code assume that IQ2000_TEMP1_REGNUM (aka large_reg) is not modified within save_restore_insns. */ @@ -1891,7 +1891,7 @@ save_restore_insns (int store_p) if (store_p) iq2000_emit_frame_related_store (mem_rtx, reg_rtx, gp_offset); - else + else { emit_move_insn (reg_rtx, mem_rtx); } @@ -2632,7 +2632,7 @@ expand_one_builtin (enum insn_code icode, rtx target, tree exp, default: gcc_unreachable (); } - + if (! pat) return 0; emit_insn (pat); @@ -2663,7 +2663,7 @@ iq2000_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED, { default: break; - + case IQ2000_BUILTIN_ADO16: return expand_one_builtin (CODE_FOR_ado16, target, exp, code, 2); @@ -2672,10 +2672,10 @@ iq2000_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED, code[2] = CONST_INT; code[3] = CONST_INT; return expand_one_builtin (CODE_FOR_ram, target, exp, code, 4); - + case IQ2000_BUILTIN_CHKHDR: return expand_one_builtin (CODE_FOR_chkhdr, target, exp, code, 2); - + case IQ2000_BUILTIN_PKRL: return expand_one_builtin (CODE_FOR_pkrl, target, exp, code, 2); @@ -2822,7 +2822,7 @@ iq2000_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED, case IQ2000_BUILTIN_SYSCALL: return expand_one_builtin (CODE_FOR_syscall, target, exp, code, 0); } - + return NULL_RTX; } @@ -2843,39 +2843,39 @@ iq2000_setup_incoming_varargs (cumulative_args_t cum_v, int *pretend_size, int no_rtl) { CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v); - unsigned int iq2000_off = ! cum->last_arg_fp; - unsigned int iq2000_fp_off = cum->last_arg_fp; + unsigned int iq2000_off = ! cum->last_arg_fp; + unsigned int iq2000_fp_off = cum->last_arg_fp; if ((cum->arg_words < MAX_ARGS_IN_REGISTERS - iq2000_off)) { - int iq2000_save_gp_regs - = MAX_ARGS_IN_REGISTERS - cum->arg_words - iq2000_off; - int iq2000_save_fp_regs - = (MAX_ARGS_IN_REGISTERS - cum->fp_arg_words - iq2000_fp_off); + int iq2000_save_gp_regs + = MAX_ARGS_IN_REGISTERS - cum->arg_words - iq2000_off; + int iq2000_save_fp_regs + = (MAX_ARGS_IN_REGISTERS - cum->fp_arg_words - iq2000_fp_off); - if (iq2000_save_gp_regs < 0) - iq2000_save_gp_regs = 0; - if (iq2000_save_fp_regs < 0) - iq2000_save_fp_regs = 0; + if (iq2000_save_gp_regs < 0) + iq2000_save_gp_regs = 0; + if (iq2000_save_fp_regs < 0) + iq2000_save_fp_regs = 0; - *pretend_size = ((iq2000_save_gp_regs * UNITS_PER_WORD) - + (iq2000_save_fp_regs * UNITS_PER_FPREG)); + *pretend_size = ((iq2000_save_gp_regs * UNITS_PER_WORD) + + (iq2000_save_fp_regs * UNITS_PER_FPREG)); - if (! (no_rtl)) + if (! (no_rtl)) { - if (cum->arg_words < MAX_ARGS_IN_REGISTERS - iq2000_off) + if (cum->arg_words < MAX_ARGS_IN_REGISTERS - iq2000_off) { - rtx ptr, mem; + rtx ptr, mem; ptr = plus_constant (Pmode, virtual_incoming_args_rtx, - (iq2000_save_gp_regs * UNITS_PER_WORD)); - mem = gen_rtx_MEM (BLKmode, ptr); - move_block_from_reg - (cum->arg_words + GP_ARG_FIRST + iq2000_off, - mem, + mem = gen_rtx_MEM (BLKmode, ptr); + move_block_from_reg + (cum->arg_words + GP_ARG_FIRST + iq2000_off, + mem, iq2000_save_gp_regs); - } - } + } + } } } @@ -3297,7 +3297,7 @@ iq2000_rtx_costs (rtx x, machine_mode mode, int outer_code ATTRIBUTE_UNUSED, * total = COSTS_N_INSNS (2 * num_words); break; } - + case FFS: * total = COSTS_N_INSNS (6); break; @@ -3316,7 +3316,7 @@ iq2000_rtx_costs (rtx x, machine_mode mode, int outer_code ATTRIBUTE_UNUSED, * total = COSTS_N_INSNS ((GET_CODE (XEXP (x, 1)) == CONST_INT) ? 4 : 12); else * total = COSTS_N_INSNS (1); - break; + break; case ABS: if (mode == SFmode || mode == DFmode) @@ -3324,7 +3324,7 @@ iq2000_rtx_costs (rtx x, machine_mode mode, int outer_code ATTRIBUTE_UNUSED, else * total = COSTS_N_INSNS (4); break; - + case PLUS: case MINUS: if (mode == SFmode || mode == DFmode) @@ -3334,7 +3334,7 @@ iq2000_rtx_costs (rtx x, machine_mode mode, int outer_code ATTRIBUTE_UNUSED, else * total = COSTS_N_INSNS (1); break; - + case NEG: * total = (mode == DImode) ? 4 : 1; break; @@ -3357,16 +3357,16 @@ iq2000_rtx_costs (rtx x, machine_mode mode, int outer_code ATTRIBUTE_UNUSED, else * total = COSTS_N_INSNS (69); break; - + case UDIV: case UMOD: * total = COSTS_N_INSNS (69); break; - + case SIGN_EXTEND: * total = COSTS_N_INSNS (2); break; - + case ZERO_EXTEND: * total = COSTS_N_INSNS (1); break; @@ -3374,7 +3374,7 @@ iq2000_rtx_costs (rtx x, machine_mode mode, int outer_code ATTRIBUTE_UNUSED, case CONST_INT: * total = 0; break; - + case LABEL_REF: * total = COSTS_N_INSNS (2); break; @@ -3399,19 +3399,19 @@ iq2000_rtx_costs (rtx x, machine_mode mode, int outer_code ATTRIBUTE_UNUSED, case SYMBOL_REF: * total = COSTS_N_INSNS (SYMBOL_REF_FLAG (x) ? 1 : 2); break; - + case CONST_DOUBLE: { rtx high, low; - + split_double (x, & high, & low); - + * total = COSTS_N_INSNS ( (high == CONST0_RTX (GET_MODE (high)) || low == CONST0_RTX (GET_MODE (low))) ? 2 : 4); break; } - + default: return false; } diff --git a/gcc/config/iq2000/iq2000.h b/gcc/config/iq2000/iq2000.h index c3562be..08801ce 100644 --- a/gcc/config/iq2000/iq2000.h +++ b/gcc/config/iq2000/iq2000.h @@ -1,4 +1,4 @@ -/* Definitions of target machine for GNU compiler. +/* Definitions of target machine for GNU compiler. Vitesse IQ2000 processors Copyright (C) 2003-2024 Free Software Foundation, Inc. @@ -60,7 +60,7 @@ /* Storage Layout. */ #define BITS_BIG_ENDIAN 0 -#define BYTES_BIG_ENDIAN 1 +#define BYTES_BIG_ENDIAN 1 #define WORDS_BIG_ENDIAN 1 #define BITS_PER_WORD 32 #define MAX_BITS_PER_WORD 64 @@ -295,7 +295,7 @@ typedef struct iq2000_args init_cumulative_args (& CUM, FNTYPE, LIBNAME) \ #define FUNCTION_ARG_REGNO_P(N) \ - (((N) >= GP_ARG_FIRST && (N) <= GP_ARG_LAST)) + (((N) >= GP_ARG_FIRST && (N) <= GP_ARG_LAST)) /* On the IQ2000, R2 and R3 are the only register thus used. */ diff --git a/gcc/config/kopensolaris-gnu.h b/gcc/config/kopensolaris-gnu.h index e7f6198..880aa27 100644 --- a/gcc/config/kopensolaris-gnu.h +++ b/gcc/config/kopensolaris-gnu.h @@ -18,7 +18,7 @@ You should have received a copy of the GNU General Public License along with GCC; see the file COPYING3. If not see <http://www.gnu.org/licenses/>. */ -#undef GNU_USER_TARGET_OS_CPP_BUILTINS +#undef GNU_USER_TARGET_OS_CPP_BUILTINS #define GNU_USER_TARGET_OS_CPP_BUILTINS() \ do \ { \ diff --git a/gcc/config/lm32/lm32-protos.h b/gcc/config/lm32/lm32-protos.h index fed0de6..861a406 100644 --- a/gcc/config/lm32/lm32-protos.h +++ b/gcc/config/lm32/lm32-protos.h @@ -20,13 +20,13 @@ <http://www.gnu.org/licenses/>. */ extern int lm32_return_in_memory (tree type); -extern void lm32_declare_object (FILE *stream, char *name, char *init_string, +extern void lm32_declare_object (FILE *stream, char *name, char *init_string, char *final_string, int size); extern void lm32_expand_prologue (void); extern void lm32_expand_epilogue (void); extern void lm32_print_operand (FILE *file, rtx op, int letter); extern void lm32_print_operand_address (FILE *file, rtx addr); -extern HOST_WIDE_INT lm32_compute_initial_elimination_offset (int from, +extern HOST_WIDE_INT lm32_compute_initial_elimination_offset (int from, int to); extern int lm32_can_use_return (void); extern rtx lm32_return_addr_rtx (int count, rtx frame); diff --git a/gcc/config/lm32/lm32.cc b/gcc/config/lm32/lm32.cc index 594f733..206b3f8 100644 --- a/gcc/config/lm32/lm32.cc +++ b/gcc/config/lm32/lm32.cc @@ -158,20 +158,20 @@ emit_add (rtx dest, rtx src0, rtx src1) } /* Generate the code to compare (and possibly branch) two integer values - TEST_CODE is the comparison code we are trying to emulate + TEST_CODE is the comparison code we are trying to emulate (or implement directly) - RESULT is where to store the result of the comparison, + RESULT is where to store the result of the comparison, or null to emit a branch CMP0 CMP1 are the two comparison operands DESTINATION is the destination of the branch, or null to only compare */ static void -gen_int_relational (enum rtx_code code, - rtx result, - rtx cmp0, - rtx cmp1, - rtx destination) +gen_int_relational (enum rtx_code code, + rtx result, + rtx cmp0, + rtx cmp1, + rtx destination) { machine_mode mode; int branch_p; @@ -183,7 +183,7 @@ gen_int_relational (enum rtx_code code, /* Is this a branch or compare. */ branch_p = (destination != 0); - /* Instruction set doesn't support LE or LT, so swap operands and use + /* Instruction set doesn't support LE or LT, so swap operands and use GE, GT. */ switch (code) { @@ -270,7 +270,7 @@ lm32_expand_scc (rtx operands[]) rtx op0 = operands[2]; rtx op1 = operands[3]; - gen_int_relational (code, target, op0, op1, NULL_RTX); + gen_int_relational (code, target, op0, op1, NULL_RTX); } /* Compare OPERANDS[1] with OPERANDS[2] using comparison code @@ -284,7 +284,7 @@ lm32_expand_conditional_branch (rtx operands[]) rtx op1 = operands[2]; rtx destination = operands[3]; - gen_int_relational (code, NULL_RTX, op0, op1, destination); + gen_int_relational (code, NULL_RTX, op0, op1, destination); } /* Generate and emit RTL to save or restore callee save registers. */ @@ -304,10 +304,10 @@ expand_save_restore (struct lm32_frame_info *info, int op) { rtx offset_rtx; rtx mem; - + offset_rtx = GEN_INT (offset); if (satisfies_constraint_K (offset_rtx)) - { + { mem = gen_rtx_MEM (word_mode, gen_rtx_PLUS (Pmode, stack_pointer_rtx, @@ -316,23 +316,23 @@ expand_save_restore (struct lm32_frame_info *info, int op) else { /* r10 is caller saved so it can be used as a temp reg. */ - rtx r10; - + rtx r10; + r10 = gen_rtx_REG (word_mode, 10); insn = emit_move_insn (r10, offset_rtx); if (op == 0) RTX_FRAME_RELATED_P (insn) = 1; insn = emit_add (r10, r10, stack_pointer_rtx); if (op == 0) - RTX_FRAME_RELATED_P (insn) = 1; + RTX_FRAME_RELATED_P (insn) = 1; mem = gen_rtx_MEM (word_mode, r10); - } - + } + if (op == 0) insn = emit_move_insn (mem, gen_rtx_REG (word_mode, regno)); else insn = emit_move_insn (gen_rtx_REG (word_mode, regno), mem); - + /* only prologue instructions which set the sp fp or save a register should be marked as frame related. */ if (op == 0) @@ -391,11 +391,11 @@ lm32_expand_prologue (void) { /* Move sp to fp. */ insn = emit_move_insn (frame_pointer_rtx, stack_pointer_rtx); - RTX_FRAME_RELATED_P (insn) = 1; + RTX_FRAME_RELATED_P (insn) = 1; - /* Add offset - Don't use total_size, as that includes pretend_size, + /* Add offset - Don't use total_size, as that includes pretend_size, which isn't part of this frame? */ - insn = emit_add (frame_pointer_rtx, + insn = emit_add (frame_pointer_rtx, frame_pointer_rtx, GEN_INT (current_frame_info.args_size + current_frame_info.callee_size + @@ -513,7 +513,7 @@ lm32_print_operand (FILE * file, rtx op, int letter) fprintf (file, "%s", reg_names[regnum]); } else if (code == HIGH) - output_addr_const (file, XEXP (op, 0)); + output_addr_const (file, XEXP (op, 0)); else if (code == MEM) output_address (GET_MODE (op), XEXP (op, 0)); else if (letter == 'z' && GET_CODE (op) == CONST_INT && INTVAL (op) == 0) @@ -1129,7 +1129,7 @@ lm32_rtx_costs (rtx x, machine_mode mode, int outer_code, *total = COSTS_N_INSNS (2); return true; } - /* Fall through. */ + /* Fall through. */ default: if (satisfies_constraint_K (x)) @@ -1194,32 +1194,32 @@ lm32_can_eliminate (const int from ATTRIBUTE_UNUSED, const int to) static bool lm32_legitimate_address_p (machine_mode mode ATTRIBUTE_UNUSED, rtx x, bool strict, code_helper) -{ - /* (rM) */ +{ + /* (rM) */ if (strict && REG_P (x) && STRICT_REG_OK_FOR_BASE_P (x)) return true; if (!strict && REG_P (x) && NONSTRICT_REG_OK_FOR_BASE_P (x)) return true; - - /* (rM)+literal) */ - if (GET_CODE (x) == PLUS - && REG_P (XEXP (x, 0)) + + /* (rM)+literal) */ + if (GET_CODE (x) == PLUS + && REG_P (XEXP (x, 0)) && ((strict && STRICT_REG_OK_FOR_BASE_P (XEXP (x, 0))) - || (!strict && NONSTRICT_REG_OK_FOR_BASE_P (XEXP (x, 0)))) - && GET_CODE (XEXP (x, 1)) == CONST_INT + || (!strict && NONSTRICT_REG_OK_FOR_BASE_P (XEXP (x, 0)))) + && GET_CODE (XEXP (x, 1)) == CONST_INT && satisfies_constraint_K (XEXP ((x), 1))) return true; - - /* gp(sym) */ - if (GET_CODE (x) == SYMBOL_REF && SYMBOL_REF_SMALL_P (x)) + + /* gp(sym) */ + if (GET_CODE (x) == SYMBOL_REF && SYMBOL_REF_SMALL_P (x)) return true; - - return false; + + return false; } -/* Check a move is not memory to memory. */ +/* Check a move is not memory to memory. */ -bool +bool lm32_move_ok (machine_mode mode, rtx operands[2]) { if (memory_operand (operands[0], mode)) return register_or_zero_operand (operands[1], mode); diff --git a/gcc/config/lm32/lm32.h b/gcc/config/lm32/lm32.h index e761e14..ecad4cd 100644 --- a/gcc/config/lm32/lm32.h +++ b/gcc/config/lm32/lm32.h @@ -52,7 +52,7 @@ %{muser-enabled} \ " -/* Let link script define all link options. +/* Let link script define all link options. Default to using simulator link script. */ #undef STARTFILE_SPEC @@ -162,7 +162,7 @@ do { \ enum reg_class { - NO_REGS, + NO_REGS, GENERAL_REGS, ALL_REGS, LIM_REG_CLASSES diff --git a/gcc/config/m32c/m32c.cc b/gcc/config/m32c/m32c.cc index 38abf17..d27538e 100644 --- a/gcc/config/m32c/m32c.cc +++ b/gcc/config/m32c/m32c.cc @@ -873,7 +873,7 @@ m32c_matches_constraint_p (rtx value, int constraint) && A0_OR_PSEUDO (patternr[5]) && GET_MODE (patternr[5]) == HImode) || RTX_IS ("ms"))); - case CONSTRAINT_Sd: + case CONSTRAINT_Sd: { /* This is the common "src/dest" address */ rtx r; @@ -2790,7 +2790,7 @@ m32c_print_operand (FILE * file, rtx x, int code) #undef TARGET_PRINT_OPERAND_PUNCT_VALID_P #define TARGET_PRINT_OPERAND_PUNCT_VALID_P m32c_print_operand_punct_valid_p -static bool +static bool m32c_print_operand_punct_valid_p (unsigned char c) { if (c == '&' || c == '!') @@ -3036,7 +3036,7 @@ m32c_insert_attributes (tree node ATTRIBUTE_UNUSED, { TREE_THIS_VOLATILE (node) = true; } - } + } } /* Hash table of pragma info. */ @@ -3227,7 +3227,7 @@ m32c_immd_dbl_mov (rtx * operands ATTRIBUTE_UNUSED, /* ??? This relied on the now-defunct MEM_SCALAR and MEM_IN_STRUCT_P flags. */ return false; -} +} /* Expanders */ @@ -4099,7 +4099,7 @@ m32c_emit_prologue (void) if (flag_stack_usage_info) current_function_static_stack_size = frame_size; - + if (frame_size > 254) { extra_frame_size = frame_size - 254; diff --git a/gcc/config/m32r/m32r.cc b/gcc/config/m32r/m32r.cc index c45a7d6..4742ceb 100644 --- a/gcc/config/m32r/m32r.cc +++ b/gcc/config/m32r/m32r.cc @@ -307,7 +307,7 @@ init_reg_tables (void) for (i = 0; i < NUM_MACHINE_MODES; i++) { machine_mode m = (machine_mode) i; - + switch (GET_MODE_CLASS (m)) { case MODE_INT: diff --git a/gcc/config/m32r/m32r.h b/gcc/config/m32r/m32r.h index 7be8dfd..06d5d04 100644 --- a/gcc/config/m32r/m32r.h +++ b/gcc/config/m32r/m32r.h @@ -222,7 +222,7 @@ #define UNITS_PER_WORD 4 /* Define this macro if it is advisable to hold scalars in registers - in a wider mode than that declared by the program. In such cases, + in a wider mode than that declared by the program. In such cases, the value is constrained to be within the bounds of the declared type, but kept valid in the wider mode. The signedness of the extension may differ from that of the type. */ @@ -303,7 +303,7 @@ #endif #define FIRST_PSEUDO_REGISTER (M32R_NUM_REGISTERS + SUBTARGET_NUM_REGISTERS) - + /* 1 for registers that have pervasive standard uses and are not available for the register allocator. diff --git a/gcc/config/m68k/linux.h b/gcc/config/m68k/linux.h index b711f49..fad360f 100644 --- a/gcc/config/m68k/linux.h +++ b/gcc/config/m68k/linux.h @@ -90,7 +90,7 @@ along with GCC; see the file COPYING3. If not see /* Currently, JUMP_TABLES_IN_TEXT_SECTION must be defined in order to keep switch tables in the text section. */ - + #define JUMP_TABLES_IN_TEXT_SECTION 1 /* Use the default action for outputting the case label. */ diff --git a/gcc/config/m68k/m68k.cc b/gcc/config/m68k/m68k.cc index 729a1e8..d642bcb 100644 --- a/gcc/config/m68k/m68k.cc +++ b/gcc/config/m68k/m68k.cc @@ -772,7 +772,7 @@ m68k_get_function_kind (tree func) tree a; gcc_assert (TREE_CODE (func) == FUNCTION_DECL); - + a = lookup_attribute ("interrupt", DECL_ATTRIBUTES (func)); if (a != NULL_TREE) return m68k_fk_interrupt_handler; @@ -1400,7 +1400,7 @@ static bool m68k_ok_for_sibcall_p (tree decl, tree exp) { enum m68k_function_kind kind; - + /* We cannot use sibcalls for nested functions because we use the static chain register for indirect calls. */ if (CALL_EXPR_STATIC_CHAIN (exp)) @@ -1436,7 +1436,7 @@ m68k_ok_for_sibcall_p (tree decl, tree exp) the same. */ if (decl && m68k_get_function_kind (decl) == kind) return true; - + return false; } @@ -1733,7 +1733,7 @@ m68k_asm_final_postscan_insn (FILE *, rtx_insn *insn, rtx [], int) return; } -/* Output a dbCC; jCC sequence. Note we do not handle the +/* Output a dbCC; jCC sequence. Note we do not handle the floating point version of this sequence (Fdbcc). OPERANDS are as in the two peepholes. CODE is the code returned by m68k_output_branch_<mode>. */ @@ -2628,19 +2628,19 @@ m68k_wrap_symbol_into_got_ref (rtx x, enum m68k_reloc reloc, rtx temp_reg) /* Legitimize PIC addresses. If the address is already position-independent, we return ORIG. Newly generated position-independent addresses go to REG. If we need more - than one register, we lose. + than one register, we lose. An address is legitimized by making an indirect reference through the Global Offset Table with the name of the symbol - used as an offset. + used as an offset. - The assembler and linker are responsible for placing the + The assembler and linker are responsible for placing the address of the symbol in the GOT. The function prologue is responsible for initializing a5 to the starting address of the GOT. The assembler is also responsible for translating a symbol name - into a constant displacement from the start of the GOT. + into a constant displacement from the start of the GOT. A quick example may make things a little clearer: @@ -2660,9 +2660,9 @@ m68k_wrap_symbol_into_got_ref (rtx x, enum m68k_reloc reloc, rtx temp_reg) movel a5@(_foo:w), a0 movel #12345, a0@ - - That (in a nutshell) is how *all* symbol and label references are + + That (in a nutshell) is how *all* symbol and label references are handled. */ rtx @@ -2691,7 +2691,7 @@ legitimize_pic_address (rtx orig, machine_mode mode ATTRIBUTE_UNUSED, /* legitimize both operands of the PLUS */ gcc_assert (GET_CODE (XEXP (orig, 0)) == PLUS); - + base = legitimize_pic_address (XEXP (XEXP (orig, 0), 0), Pmode, reg); orig = legitimize_pic_address (XEXP (XEXP (orig, 0), 1), Pmode, base == reg ? 0 : reg); @@ -2753,13 +2753,13 @@ m68k_call_tls_get_addr (rtx x, rtx eqv, enum m68k_reloc reloc) is the simpliest way of generating a call. The difference between __tls_get_addr() and libcall is that the result is returned in D0 instead of A0. To workaround this, we use m68k_libcall_value_in_a0_p - which temporarily switches returning the result to A0. */ + which temporarily switches returning the result to A0. */ m68k_libcall_value_in_a0_p = true; a0 = emit_library_call_value (m68k_get_tls_get_addr (), NULL_RTX, LCT_PURE, Pmode, x, Pmode); m68k_libcall_value_in_a0_p = false; - + insns = get_insns (); end_sequence (); @@ -2787,7 +2787,7 @@ m68k_get_m68k_read_tp (void) /* Emit instruction sequence that calls __m68k_read_tp. A pseudo register with result of __m68k_read_tp call is returned. */ -static rtx +static rtx m68k_call_m68k_read_tp (void) { rtx a0; @@ -2801,7 +2801,7 @@ m68k_call_m68k_read_tp (void) is the simpliest way of generating a call. The difference between __m68k_read_tp() and libcall is that the result is returned in D0 instead of A0. To workaround this, we use m68k_libcall_value_in_a0_p - which temporarily switches returning the result to A0. */ + which temporarily switches returning the result to A0. */ /* Emit the call sequence. */ m68k_libcall_value_in_a0_p = true; @@ -2840,7 +2840,7 @@ m68k_legitimize_tls_address (rtx orig) rtx eqv; rtx a0; rtx x; - + /* Attach a unique REG_EQUIV, to allow the RTL optimizers to share the LDM result with other LD model accesses. */ eqv = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx), @@ -4848,7 +4848,7 @@ output_move_const_single (rtx *operands) to get the desired constant. */ /* This code has been fixed for cross-compilation. */ - + static int inited_68881_table = 0; static const char *const strings_68881[7] = { @@ -4916,7 +4916,7 @@ standard_68881_constant_p (rtx x) if (real_identical (r, &values_68881[i])) return (codes_68881[i]); } - + if (GET_MODE (x) == SFmode) return 0; @@ -5205,7 +5205,7 @@ m68k_delegitimize_address (rtx orig_x) unspec = XEXP (addr.offset, 0); if (GET_CODE (unspec) == PLUS && CONST_INT_P (XEXP (unspec, 1))) unspec = XEXP (unspec, 0); - if (GET_CODE (unspec) != UNSPEC + if (GET_CODE (unspec) != UNSPEC || (XINT (unspec, 1) != UNSPEC_RELOC16 && XINT (unspec, 1) != UNSPEC_RELOC32)) return orig_x; @@ -5226,7 +5226,7 @@ m68k_delegitimize_address (rtx orig_x) x = replace_equiv_address_nv (orig_x, x); return x; } - + /* A C compound statement to output to stdio stream STREAM the assembler syntax for an instruction operand that is a memory @@ -5240,7 +5240,7 @@ m68k_delegitimize_address (rtx orig_x) It is possible for PIC to generate a (plus (label_ref...) (reg...)) and we handle that just like we would a (plus (symbol_ref...) (reg...)). - This routine is responsible for distinguishing between -fpic and -fPIC + This routine is responsible for distinguishing between -fpic and -fPIC style relocations in an address. When generating -fpic code the offset is output in word mode (e.g. movel a5@(_foo:w), a0). When generating -fPIC code the offset is output in long mode (e.g. movel a5@(_foo:l), a0) */ @@ -6661,7 +6661,7 @@ m68k_sched_variable_issue (FILE *sched_dump ATTRIBUTE_UNUSED, case CPU_CFV3: insn_size = sched_get_attr_size_int (insn); - + /* ColdFire V3 and V4 cores have instruction buffers that can accumulate up to 8 instructions regardless of instructions' sizes. So we should take care not to "prefetch" 24 one-word diff --git a/gcc/config/m68k/m68kelf.h b/gcc/config/m68k/m68kelf.h index 0af1951..f53e40f 100644 --- a/gcc/config/m68k/m68kelf.h +++ b/gcc/config/m68k/m68kelf.h @@ -104,7 +104,7 @@ do { \ #define DEBUGGER_REGNO(REGNO) (REGNO) #if 0 -/* SVR4 m68k assembler is bitching on the `comm i,1,1' which askes for +/* SVR4 m68k assembler is bitching on the `comm i,1,1' which askes for 1 byte alignment. Don't generate alignment for COMMON seems to be safer until we the assembler is fixed. */ #undef ASM_OUTPUT_ALIGNED_COMMON @@ -126,7 +126,7 @@ do { \ /* Currently, JUMP_TABLES_IN_TEXT_SECTION must be defined in order to keep switch tables in the text section. */ - + #define JUMP_TABLES_IN_TEXT_SECTION 1 /* In m68k svr4, using swbeg is the standard way to do switch diff --git a/gcc/config/m68k/netbsd-elf.h b/gcc/config/m68k/netbsd-elf.h index 6fc5ad1..3d2043b 100644 --- a/gcc/config/m68k/netbsd-elf.h +++ b/gcc/config/m68k/netbsd-elf.h @@ -35,7 +35,7 @@ along with GCC; see the file COPYING3. If not see } \ while (0) -/* Don't try using XFmode on the 68010. */ +/* Don't try using XFmode on the 68010. */ #undef LONG_DOUBLE_TYPE_MODE #define LONG_DOUBLE_TYPE_MODE (TARGET_68020 ? XFmode : DFmode) diff --git a/gcc/config/mcore/mcore-elf.h b/gcc/config/mcore/mcore-elf.h index 6c522c7..c367bad 100644 --- a/gcc/config/mcore/mcore-elf.h +++ b/gcc/config/mcore/mcore-elf.h @@ -1,4 +1,4 @@ -/* Definitions of MCore target. +/* Definitions of MCore target. Copyright (C) 1998-2024 Free Software Foundation, Inc. Contributed by Cygnus Solutions. @@ -78,7 +78,7 @@ along with GCC; see the file COPYING3. If not see ASM_OUTPUT_LABEL(FILE, NAME); \ } \ while (0) - + /* Output the size directive for a decl in rest_of_decl_compilation in the case where we did not do so before the initializer. Once we find the error_mark_node, we know that the value of @@ -121,5 +121,5 @@ along with GCC; see the file COPYING3. If not see #define CTORS_SECTION_ASM_OP "\t.section\t.ctors,\"aw\"" #undef DTORS_SECTION_ASM_OP #define DTORS_SECTION_ASM_OP "\t.section\t.dtors,\"aw\"" - + #endif /* __MCORE_ELF_H__ */ diff --git a/gcc/config/mcore/mcore.cc b/gcc/config/mcore/mcore.cc index ee58c8f..99c0a6c 100644 --- a/gcc/config/mcore/mcore.cc +++ b/gcc/config/mcore/mcore.cc @@ -293,12 +293,12 @@ output_stack_adjust (int direction, int size) emit_insn (gen_movsi (nval, val)); val = nval; } - + if (direction > 0) insn = gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, val); else insn = gen_subsi3 (stack_pointer_rtx, stack_pointer_rtx, val); - + emit_insn (insn); } } @@ -311,7 +311,7 @@ calc_live_regs (int * count) { int reg; int live_regs_mask = 0; - + * count = 0; for (reg = 0; reg < FIRST_PSEUDO_REGISTER; reg++) @@ -336,7 +336,7 @@ mcore_print_operand_address (FILE * stream, machine_mode /*mode*/, rtx x) case REG: fprintf (stream, "(%s)", reg_names[REGNO (x)]); break; - + case PLUS: { rtx base = XEXP (x, 0); @@ -463,25 +463,25 @@ mcore_const_costs (rtx exp, enum rtx_code code) HOST_WIDE_INT val = INTVAL (exp); /* Easy constants. */ - if ( CONST_OK_FOR_I (val) - || CONST_OK_FOR_M (val) - || CONST_OK_FOR_N (val) + if ( CONST_OK_FOR_I (val) + || CONST_OK_FOR_M (val) + || CONST_OK_FOR_N (val) || (code == PLUS && CONST_OK_FOR_L (val))) - return 1; + return 1; else if (code == AND && ( CONST_OK_FOR_M (~val) || CONST_OK_FOR_N (~val))) return 2; - else if (code == PLUS - && ( CONST_OK_FOR_I (-val) - || CONST_OK_FOR_M (-val) - || CONST_OK_FOR_N (-val))) - return 2; + else if (code == PLUS + && ( CONST_OK_FOR_I (-val) + || CONST_OK_FOR_M (-val) + || CONST_OK_FOR_N (-val))) + return 2; - return 5; + return 5; } -/* What does an and instruction cost - we do this b/c immediates may +/* What does an and instruction cost - we do this b/c immediates may have been relaxed. We want to ensure that cse will cse relaxed immeds out. Otherwise we'll get bad code (multiple reloads of the same const). */ @@ -494,7 +494,7 @@ mcore_and_cost (rtx x) return 2; val = INTVAL (XEXP (x, 1)); - + /* Do it directly. */ if (CONST_OK_FOR_K (val) || CONST_OK_FOR_M (~val)) return 2; @@ -530,7 +530,7 @@ mcore_ior_cost (rtx x) /* Takes two instructions to load. */ else if (TARGET_HARDLIT && mcore_const_ok_for_inline (val)) return 4; - + /* Takes a lrw to load. */ return 5; } @@ -572,7 +572,7 @@ mcore_rtx_costs (rtx x, machine_mode mode ATTRIBUTE_UNUSED, int outer_code, case FIX: *total = COSTS_N_INSNS (100); return true; - + default: return false; } @@ -590,7 +590,7 @@ mcore_gen_compare (enum rtx_code code, rtx op0, rtx op1) if (GET_CODE (op1) == CONST_INT) { HOST_WIDE_INT val = INTVAL (op1); - + switch (code) { case GTU: @@ -610,12 +610,12 @@ mcore_gen_compare (enum rtx_code code, rtx op0, rtx op1) code = code == LE ? LT : GE; } break; - + default: break; } } - + if (CONSTANT_P (op1) && GET_CODE (op1) != CONST_INT) op1 = force_reg (SImode, op1); @@ -628,7 +628,7 @@ mcore_gen_compare (enum rtx_code code, rtx op0, rtx op1) code = NE; invert = true; /* FALLTHRU */ - + case NE: /* Use normal condition, cmpne. */ if (GET_CODE (op1) == CONST_INT && ! CONST_OK_FOR_K (INTVAL (op1))) op1 = force_reg (SImode, op1); @@ -638,7 +638,7 @@ mcore_gen_compare (enum rtx_code code, rtx op0, rtx op1) code = GT; invert = true; /* FALLTHRU */ - + case GT: /* Use normal condition, reversed cmplt. */ if (GET_CODE (op1) == CONST_INT) op1 = force_reg (SImode, op1); @@ -648,9 +648,9 @@ mcore_gen_compare (enum rtx_code code, rtx op0, rtx op1) code = LT; invert = true; /* FALLTHRU */ - + case LT: /* Use normal condition, cmplt. */ - if (GET_CODE (op1) == CONST_INT && + if (GET_CODE (op1) == CONST_INT && /* covered by btsti x,31. */ INTVAL (op1) != 0 && ! CONST_OK_FOR_J (INTVAL (op1))) @@ -663,7 +663,7 @@ mcore_gen_compare (enum rtx_code code, rtx op0, rtx op1) code = LEU; invert = true; /* FALLTHRU */ - + case LEU: /* Use normal condition, reversed cmphs. */ if (GET_CODE (op1) == CONST_INT && INTVAL (op1) != 0) op1 = force_reg (SImode, op1); @@ -673,7 +673,7 @@ mcore_gen_compare (enum rtx_code code, rtx op0, rtx op1) code = GEU; invert = true; /* FALLTHRU */ - + case GEU: /* Use normal condition, cmphs. */ if (GET_CODE (op1) == CONST_INT && INTVAL (op1) != 0) op1 = force_reg (SImode, op1); @@ -712,13 +712,13 @@ mcore_output_call (rtx operands[], int index) { static char buffer[20]; rtx addr = operands [index]; - + if (REG_P (addr)) { if (TARGET_CG_DATA) { gcc_assert (mcore_current_function_name); - + ASM_OUTPUT_CG_EDGE (asm_out_file, mcore_current_function_name, "unknown", 1); } @@ -731,11 +731,11 @@ mcore_output_call (rtx operands[], int index) { gcc_assert (mcore_current_function_name); gcc_assert (GET_CODE (addr) == SYMBOL_REF); - + ASM_OUTPUT_CG_EDGE (asm_out_file, mcore_current_function_name, XSTR (addr, 0), 0); } - + sprintf (buffer, "jbsr\t%%%d", index); } @@ -749,15 +749,15 @@ const_ok_for_mcore (HOST_WIDE_INT value) { if (value >= 0 && value <= 127) return 1; - + /* Try exact power of two. */ if (CONST_OK_FOR_M (value)) return 1; - + /* Try exact power of two - 1. */ if (CONST_OK_FOR_N (value) && value != -1) return 1; - + return 0; } @@ -767,7 +767,7 @@ int mcore_const_ok_for_inline (HOST_WIDE_INT value) { HOST_WIDE_INT x, y; - + return try_constant_tricks (value, & x, & y) > 0; } @@ -778,12 +778,12 @@ mcore_const_trick_uses_not (HOST_WIDE_INT value) { HOST_WIDE_INT x, y; - return try_constant_tricks (value, & x, & y) == 2; -} + return try_constant_tricks (value, & x, & y) == 2; +} /* Try tricks to load a constant inline and return the trick number if success (0 is non-inlinable). - + 0: not inlinable 1: single instruction (do the usual thing) 2: single insn followed by a 'not' @@ -805,8 +805,8 @@ try_constant_tricks (HOST_WIDE_INT value, HOST_WIDE_INT * x, HOST_WIDE_INT * y) if (const_ok_for_mcore (value)) return 1; /* Do the usual thing. */ - - if (! TARGET_HARDLIT) + + if (! TARGET_HARDLIT) return 0; if (const_ok_for_mcore (~value)) @@ -912,13 +912,13 @@ try_constant_tricks (HOST_WIDE_INT value, HOST_WIDE_INT * x, HOST_WIDE_INT * y) return 11; } - + return 0; } /* Check whether reg is dead at first. This is done by searching ahead for either the next use (i.e., reg is live), a death note, or a set of - reg. Don't just use dead_or_set_p() since reload does not always mark + reg. Don't just use dead_or_set_p() since reload does not always mark deaths (especially if PRESERVE_DEATH_NOTES_REGNO_P is not defined). We can ignore subregs by extracting the actual register. BRC */ @@ -1032,11 +1032,11 @@ mcore_output_bseti (rtx dst, int mask) if ((mask & 0x1) == 0x1) { out_operands[1] = GEN_INT (bit); - + output_asm_insn ("bseti\t%0,%1", out_operands); } mask >>= 1; - } + } return ""; } @@ -1056,12 +1056,12 @@ mcore_output_bclri (rtx dst, int mask) if ((mask & 0x1) == 0x0) { out_operands[1] = GEN_INT (bit); - + output_asm_insn ("bclri\t%0,%1", out_operands); } - + mask >>= 1; - } + } return ""; } @@ -1098,7 +1098,7 @@ mcore_output_cmov (rtx operands[], int cmp_t, const char * test) /* First output the test if folded into the pattern. */ - if (test) + if (test) output_asm_insn (test, operands); /* Load the constant - for now, only support constants that can be @@ -1111,7 +1111,7 @@ mcore_output_cmov (rtx operands[], int cmp_t, const char * test) output_asm_insn ("bgeni\t%0,%P1", out_operands); else if (CONST_OK_FOR_N (load_value)) output_asm_insn ("bmaski\t%0,%N1", out_operands); - + /* Output the constant adjustment. */ if (load_value > adjust_value) { @@ -1131,7 +1131,7 @@ mcore_output_cmov (rtx operands[], int cmp_t, const char * test) return ""; } -/* Outputs the peephole for moving a constant that gets not'ed followed +/* Outputs the peephole for moving a constant that gets not'ed followed by an and (i.e. combine the not and the and into andn). BRC */ const char * @@ -1152,15 +1152,15 @@ mcore_output_andn (rtx insn ATTRIBUTE_UNUSED, rtx operands[]) if (x >= 0 && x <= 127) load_op = "movi\t%0,%1"; - + /* Try exact power of two. */ else if (CONST_OK_FOR_M (x)) load_op = "bgeni\t%0,%P1"; - + /* Try exact power of two - 1. */ else if (CONST_OK_FOR_N (x)) load_op = "bmaski\t%0,%N1"; - + else { load_op = "BADMOVI-andn\t%0, %1"; @@ -1193,14 +1193,14 @@ output_inline_const (machine_mode mode, rtx operands[]) turned into lrw's. Our caller uses try_constant_tricks to back off to an lrw rather than calling this routine. */ gcc_assert (trick_no != 0); - + if (trick_no == 1) x = value; /* operands: 0 = dst, 1 = load immed., 2 = immed. adjustment. */ out_operands[0] = operands[0]; out_operands[1] = GEN_INT (x); - + if (trick_no > 2) out_operands[2] = GEN_INT (y); @@ -1212,20 +1212,20 @@ output_inline_const (machine_mode mode, rtx operands[]) if (x >= 0 && x <= 127) sprintf (load_op, "movi\t%s,%%1", dst_fmt); - + /* Try exact power of two. */ else if (CONST_OK_FOR_M (x)) sprintf (load_op, "bgeni\t%s,%%P1", dst_fmt); - + /* Try exact power of two - 1. */ else if (CONST_OK_FOR_N (x)) sprintf (load_op, "bmaski\t%s,%%N1", dst_fmt); - + else { sprintf (load_op, "BADMOVI-inline_const %s, %%1", dst_fmt); gcc_unreachable (); - } + } switch (trick_no) { @@ -1266,7 +1266,7 @@ output_inline_const (machine_mode mode, rtx operands[]) default: return ""; } - + output_asm_insn (buf, out_operands); return ""; @@ -1284,15 +1284,15 @@ mcore_output_move (rtx insn ATTRIBUTE_UNUSED, rtx operands[], if (GET_CODE (dst) == REG) { if (GET_CODE (src) == REG) - { + { if (REGNO (src) == CC_REG) /* r-c */ - return "mvc\t%0"; - else + return "mvc\t%0"; + else return "mov\t%0,%1"; /* r-r*/ } else if (GET_CODE (src) == MEM) { - if (GET_CODE (XEXP (src, 0)) == LABEL_REF) + if (GET_CODE (XEXP (src, 0)) == LABEL_REF) return "lrw\t%0,[%1]"; /* a-R */ else switch (GET_MODE (src)) /* r-m */ @@ -1310,7 +1310,7 @@ mcore_output_move (rtx insn ATTRIBUTE_UNUSED, rtx operands[], else if (GET_CODE (src) == CONST_INT) { HOST_WIDE_INT x, y; - + if (CONST_OK_FOR_I (INTVAL (src))) /* r-I */ return "movi\t%0,%1"; else if (CONST_OK_FOR_M (INTVAL (src))) /* r-M */ @@ -1319,7 +1319,7 @@ mcore_output_move (rtx insn ATTRIBUTE_UNUSED, rtx operands[], return "bmaski\t%0,%N1\t// %1 %x1"; else if (try_constant_tricks (INTVAL (src), &x, &y)) /* R-P */ return output_inline_const (SImode, operands); /* 1-2 insns */ - else + else return "lrw\t%0,%x1\t// %1"; /* Get it from literal pool. */ } else @@ -1357,7 +1357,7 @@ mcore_output_movedouble (rtx operands[], machine_mode mode ATTRIBUTE_UNUSED) { int dstreg = REGNO (dst); int srcreg = REGNO (src); - + /* Ensure the second source not overwritten. */ if (srcreg + 1 == dstreg) return "mov %R0,%R1\n\tmov %0,%1"; @@ -1369,10 +1369,10 @@ mcore_output_movedouble (rtx operands[], machine_mode mode ATTRIBUTE_UNUSED) rtx memexp = XEXP (src, 0); int dstreg = REGNO (dst); int basereg = -1; - + if (GET_CODE (memexp) == LABEL_REF) return "lrw\t%0,[%1]\n\tlrw\t%R0,[%R1]"; - else if (GET_CODE (memexp) == REG) + else if (GET_CODE (memexp) == REG) basereg = REGNO (memexp); else if (GET_CODE (memexp) == PLUS) { @@ -1391,7 +1391,7 @@ mcore_output_movedouble (rtx operands[], machine_mode mode ATTRIBUTE_UNUSED) { /* Just load them in reverse order. */ return "ldw\t%R0,%R1\n\tldw\t%0,%1"; - + /* XXX: alternative: move basereg to basereg+1 and then fall through. */ } @@ -1449,7 +1449,7 @@ mcore_arith_S_operand (rtx op) { if (GET_CODE (op) == CONST_INT && CONST_OK_FOR_M (~INTVAL (op))) return 1; - + return 0; } @@ -1484,7 +1484,7 @@ mcore_expand_insv (rtx operands[]) gen_rtx_IOR (SImode, operands[0], GEN_INT (mask)))); } - + return 1; } @@ -1496,7 +1496,7 @@ mcore_expand_insv (rtx operands[]) if (width == 8 && posn % 8 == 0) /* Byte sized and aligned; let caller break it up. */ return 0; - + if (width == 16 && posn % 16 == 0) /* Short sized and aligned; let caller break it up. */ return 0; @@ -1539,7 +1539,7 @@ mcore_expand_insv (rtx operands[]) bits. */ if (width + posn != (int) GET_MODE_SIZE (SImode)) { - ereg = force_reg (SImode, GEN_INT ((1 << width) - 1)); + ereg = force_reg (SImode, GEN_INT ((1 << width) - 1)); emit_insn (gen_rtx_SET (sreg, gen_rtx_AND (SImode, sreg, ereg))); } @@ -1547,7 +1547,7 @@ mcore_expand_insv (rtx operands[]) if (posn != 0) emit_insn (gen_rtx_SET (sreg, gen_rtx_ASHIFT (SImode, sreg, GEN_INT (posn)))); - + emit_insn (gen_rtx_SET (operands[0], gen_rtx_IOR (SImode, operands[0], sreg))); @@ -1630,7 +1630,7 @@ block_move_sequence (rtx dst_mem, rtx src_mem, int size, int align) if (active[phase]) { active[phase] = false; - + x = adjust_address (dst_mem, mode[phase], offset_st); emit_insn (gen_rtx_SET (x, temp[phase])); @@ -1712,11 +1712,11 @@ layout_mcore_frame (struct mcore_frame * infp) /* Might have to spill bytes to re-assemble a big argument that was passed partially in registers and partially on the stack. */ nbytes = crtl->args.pretend_args_size; - + /* Determine how much space for spilled anonymous args (e.g., stdarg). */ if (current_function_anonymous_args) nbytes += (NPARM_REGS - number_of_regs_before_varargs) * UNITS_PER_WORD; - + infp->arg_size = nbytes; /* How much space to save non-volatile registers we stomp. */ @@ -1730,7 +1730,7 @@ layout_mcore_frame (struct mcore_frame * infp) /* Make sure we have a whole number of words for the locals. */ if (infp->local_size % STACK_BYTES) infp->local_size = (infp->local_size + STACK_BYTES - 1) & ~ (STACK_BYTES -1); - + /* Only thing we know we have to pad is the outbound space, since we've aligned our locals assuming that base of locals is aligned. */ infp->pad_local = 0; @@ -1765,23 +1765,23 @@ layout_mcore_frame (struct mcore_frame * infp) step = localregarg + infp->pad_reg; infp->reg_offset = infp->local_size; - + if (outbounds + step <= ADDI_REACH && !frame_pointer_needed) { step += outbounds; infp->reg_offset += outbounds; outbounds = 0; } - + infp->arg_offset = step - 4; infp->growth[growths++] = step; infp->reg_growth = growths; infp->local_growth = growths; - + /* If we haven't already folded it in. */ if (outbounds) infp->growth[growths++] = outbounds; - + goto finish; } @@ -1803,7 +1803,7 @@ layout_mcore_frame (struct mcore_frame * infp) step = ADDI_REACH; /* As much up front as we can. */ if (step > all) step = all; - + /* XXX: Consider whether step will still be aligned; we believe so. */ infp->arg_offset = step - 4; infp->growth[growths++] = step; @@ -1829,7 +1829,7 @@ layout_mcore_frame (struct mcore_frame * infp) /* Finish off if we need to do so. */ if (outbounds) infp->growth[growths++] = outbounds; - + goto finish; } @@ -1845,28 +1845,28 @@ layout_mcore_frame (struct mcore_frame * infp) if (infp->local_size % STACK_BYTES) infp->pad_local = STACK_BYTES - (infp->local_size % STACK_BYTES); - + step = infp->local_size + infp->pad_local; - + if (!frame_pointer_needed) { step += outbounds; outbounds = 0; } - + infp->growth[growths++] = step; infp->local_growth = growths; /* If there's any left to be done. */ if (outbounds) infp->growth[growths++] = outbounds; - + goto finish; } /* XXX: optimizations that we'll want to play with.... -- regarg is not aligned, but it's a small number of registers; - use some of localsize so that regarg is aligned and then + use some of localsize so that regarg is aligned and then save the registers. */ /* Simple encoding; plods down the stack buying the pieces as it goes. @@ -1875,27 +1875,27 @@ layout_mcore_frame (struct mcore_frame * infp) -- but it is safe for all alignments. */ if (regarg % STACK_BYTES != 0) infp->pad_reg = STACK_BYTES - (regarg % STACK_BYTES); - + infp->growth[growths++] = infp->arg_size + infp->reg_size + infp->pad_reg; infp->reg_growth = growths; infp->arg_offset = infp->growth[0] - 4; infp->reg_offset = 0; - + if (frame_pointer_needed) { if (infp->local_size % STACK_BYTES != 0) infp->pad_local = STACK_BYTES - (infp->local_size % STACK_BYTES); - + infp->growth[growths++] = infp->local_size + infp->pad_local; infp->local_growth = growths; - + infp->growth[growths++] = outbounds; } else { if ((infp->local_size + outbounds) % STACK_BYTES != 0) infp->pad_local = STACK_BYTES - ((infp->local_size + outbounds) % STACK_BYTES); - + infp->growth[growths++] = infp->local_size + infp->pad_local + outbounds; infp->local_growth = growths; } @@ -1904,7 +1904,7 @@ layout_mcore_frame (struct mcore_frame * infp) finish: gcc_assert (infp->reg_offset >= 0); gcc_assert (growths <= MAX_STACK_GROWS); - + for (i = 0; i < growths; i++) gcc_assert (!(infp->growth[i] % STACK_BYTES)); } @@ -1956,12 +1956,12 @@ mcore_setup_incoming_varargs (cumulative_args_t args_so_far_v, number_of_regs_before_varargs = *args_so_far; if (!TYPE_NO_NAMED_ARGS_STDARG_P (TREE_TYPE (current_function_decl))) number_of_regs_before_varargs += mcore_num_arg_regs (arg.mode, arg.type); - + /* There is a bug somewhere in the arg handling code. Until I can find it this workaround always pushes the last named argument onto the stack. */ number_of_regs_before_varargs = *args_so_far; - + /* The last named argument may be split between argument registers and the stack. Allow for this here. */ if (number_of_regs_before_varargs > NPARM_REGS) @@ -1977,7 +1977,7 @@ mcore_expand_prolog (void) /* Find out what we're doing. */ layout_mcore_frame (&fi); - + space_allocated = fi.arg_size + fi.reg_size + fi.local_size + fi.outbound_size + fi.pad_outbound + fi.pad_local + fi.pad_reg; @@ -1987,17 +1987,17 @@ mcore_expand_prolog (void) rtx x; x = DECL_RTL (current_function_decl); - + gcc_assert (GET_CODE (x) == MEM); - + x = XEXP (x, 0); - + gcc_assert (GET_CODE (x) == SYMBOL_REF); - + free (mcore_current_function_name); - + mcore_current_function_name = xstrdup (XSTR (x, 0)); - + ASM_OUTPUT_CG_NODE (asm_out_file, mcore_current_function_name, space_allocated); if (cfun->calls_alloca) @@ -2017,7 +2017,7 @@ mcore_expand_prolog (void) if (mcore_naked_function_p ()) return; - + /* Handle stdarg+regsaves in one shot: can't be more than 64 bytes. */ output_stack_adjust (-1, fi.growth[growth++]); /* Grows it. */ @@ -2048,7 +2048,7 @@ mcore_expand_prolog (void) { int i; int offs = fi.reg_offset; - + for (i = 15; i >= 0; i--) { if (offs == 0 && i == 15 && ((fi.reg_mask & 0xc000) == 0xc000)) @@ -2084,7 +2084,7 @@ mcore_expand_prolog (void) /* If we haven't already purchased to 'fp'. */ if (growth < fi.local_growth) output_stack_adjust (-1, fi.growth[growth++]); /* Grows it. */ - + emit_insn (gen_movsi (frame_pointer_rtx, stack_pointer_rtx)); /* ... and then go any remaining distance for outbounds, etc. */ @@ -2108,7 +2108,7 @@ mcore_expand_epilog (void) int offs; int growth = MAX_STACK_GROWS - 1 ; - + /* Find out what we're doing. */ layout_mcore_frame(&fi); @@ -2137,9 +2137,9 @@ mcore_expand_epilog (void) register save information back off the stack. */ while (growth >= fi.reg_growth) output_stack_adjust ( 1, fi.growth[growth--]); - + offs = fi.reg_offset; - + for (i = 15; i >= 0; i--) { if (offs == 0 && i == 15 && ((fi.reg_mask & 0xc000) == 0xc000)) @@ -2148,10 +2148,10 @@ mcore_expand_epilog (void) /* Find the starting register. */ first_reg = 15; - + while (fi.reg_mask & (1 << first_reg)) first_reg--; - + first_reg++; emit_insn (gen_load_multiple (gen_rtx_REG (SImode, first_reg), @@ -2257,16 +2257,16 @@ mcore_output_jump_label_table (void) if (pool_size) { fprintf (asm_out_file, "\t.align 2\n"); - + for (i = 0; i < pool_size; i++) { pool_node * p = pool_vector + i; (*targetm.asm_out.internal_label) (asm_out_file, "L", CODE_LABEL_NUMBER (p->label)); - + output_asm_insn (".long %0", &p->value); } - + pool_size = 0; } @@ -2279,7 +2279,7 @@ static cond_type is_cond_candidate (rtx insn) { /* The only things we conditionalize are those that can be directly - changed into a conditional. Only bother with SImode items. If + changed into a conditional. Only bother with SImode items. If we wanted to be a little more aggressive, we could also do other modes such as DImode with reg-reg move or load 0. */ if (NONJUMP_INSN_P (insn)) @@ -2296,7 +2296,7 @@ is_cond_candidate (rtx insn) GET_CODE (dst) != SUBREG) || GET_MODE (dst) != SImode) return COND_NO; - + src = XEXP (pat, 1); if ((GET_CODE (src) == REG || @@ -2304,7 +2304,7 @@ is_cond_candidate (rtx insn) GET_CODE (SUBREG_REG (src)) == REG)) && GET_MODE (src) == SImode) return COND_MOV_INSN; - else if (GET_CODE (src) == CONST_INT && + else if (GET_CODE (src) == CONST_INT && INTVAL (src) == 0) return COND_CLR_INSN; else if (GET_CODE (src) == PLUS && @@ -2330,7 +2330,7 @@ is_cond_candidate (rtx insn) /* Some insns that we don't bother with: (set (rx:DI) (ry:DI)) (set (rx:DI) (const_int 0)) - */ + */ } else if (JUMP_P (insn) @@ -2369,7 +2369,7 @@ emit_new_cond_insn (rtx_insn *insn, int cond) switch (num) { - case COND_MOV_INSN: + case COND_MOV_INSN: case COND_CLR_INSN: if (cond) c_insn = gen_movt0 (dst, src, dst); @@ -2383,7 +2383,7 @@ emit_new_cond_insn (rtx_insn *insn, int cond) else c_insn = gen_incscc_false (dst, dst); break; - + case COND_DEC_INSN: if (cond) c_insn = gen_decscc (dst, dst); @@ -2411,7 +2411,7 @@ emit_new_cond_insn (rtx_insn *insn, int cond) used any more beyond this point for the mcore). */ REG_NOTES (c_insn) = REG_NOTES (insn); } - + if (num == COND_BRANCH_INSN) { /* For jumps, we need to be a little bit careful and emit the new jump @@ -2419,32 +2419,32 @@ emit_new_cond_insn (rtx_insn *insn, int cond) This way, the barrier following the old (uncond) jump will get deleted, but the label won't. */ c_insn = emit_jump_insn_before (c_insn, insn); - + ++ LABEL_NUSES (dst); - + JUMP_LABEL (c_insn) = dst; } else c_insn = emit_insn_after (c_insn, insn); delete_insn (insn); - + return as_a <rtx_insn *> (c_insn); } /* Attempt to change a basic block into a series of conditional insns. This - works by taking the branch at the end of the 1st block and scanning for the + works by taking the branch at the end of the 1st block and scanning for the end of the 2nd block. If all instructions in the 2nd block have cond. versions and the label at the start of block 3 is the same as the target from the branch at block 1, then conditionalize all insn in block 2 using the inverse condition of the branch at block 1. (Note I'm bending the definition of basic block here.) - e.g., change: + e.g., change: bt L2 <-- end of block 1 (delete) - mov r7,r8 - addu r7,1 + mov r7,r8 + addu r7,1 br L3 <-- end of block 2 L2: ... <-- start of block 3 (NUSES==1) @@ -2473,7 +2473,7 @@ conditionalize_block (rtx_insn *first) int br_lab_num; int blk_size = 0; - + /* Check that the first insn is a candidate conditional jump. This is the one that we'll eliminate. If not, advance to the next insn to try. */ @@ -2506,12 +2506,12 @@ conditionalize_block (rtx_insn *first) /* Scan forward for the start of block 2: it must start with a label and that label must be the same as the branch target label from block 1. We don't care about whether block 2 actually - ends with a branch or a label (an uncond. branch is + ends with a branch or a label (an uncond. branch is conditionalizable). */ for (insn = NEXT_INSN (first); insn; insn = NEXT_INSN (insn)) { enum rtx_code code; - + code = GET_CODE (insn); /* Look for the label at the start of block 3. */ @@ -2523,7 +2523,7 @@ conditionalize_block (rtx_insn *first) just return the next insn so we can start over from that point. */ if (code != BARRIER && code != NOTE && !is_cond_candidate (insn)) return NEXT_INSN (insn); - + /* Remember the last real insn before the label (i.e. end of block 2). */ if (code == JUMP_INSN || code == INSN) { @@ -2534,16 +2534,16 @@ conditionalize_block (rtx_insn *first) if (!insn) return insn; - - /* It is possible for this optimization to slow performance if the blocks - are long. This really depends upon whether the branch is likely taken + + /* It is possible for this optimization to slow performance if the blocks + are long. This really depends upon whether the branch is likely taken or not. If the branch is taken, we slow performance in many cases. But, - if the branch is not taken, we always help performance (for a single - block, but for a double block (i.e. when the optimization is re-applied) + if the branch is not taken, we always help performance (for a single + block, but for a double block (i.e. when the optimization is re-applied) this is not true since the 'right thing' depends on the overall length of - the collapsed block). As a compromise, don't apply this optimization on + the collapsed block). As a compromise, don't apply this optimization on blocks larger than size 2 (unlikely for the mcore) when speed is important. - the best threshold depends on the latencies of the instructions (i.e., + the best threshold depends on the latencies of the instructions (i.e., the branch penalty). */ if (optimize > 1 && blk_size > 2) return insn; @@ -2552,16 +2552,16 @@ conditionalize_block (rtx_insn *first) it is the destination of the branch from block 1. Also, all instructions in the block 2 are conditionalizable. So, apply the conditionalization and delete the branch. */ - start_blk_3_lab = insn; - - for (insn = NEXT_INSN (end_blk_1_br); insn != start_blk_3_lab; + start_blk_3_lab = insn; + + for (insn = NEXT_INSN (end_blk_1_br); insn != start_blk_3_lab; insn = NEXT_INSN (insn)) { rtx_insn *newinsn; if (insn->deleted ()) continue; - + /* Try to form a conditional variant of the instruction and emit it. */ if ((newinsn = emit_new_cond_insn (insn, cond))) { @@ -2573,7 +2573,7 @@ conditionalize_block (rtx_insn *first) } /* Note whether we will delete the label starting blk 3 when the jump - gets deleted. If so, we want to re-apply this optimization at the + gets deleted. If so, we want to re-apply this optimization at the last real instruction right before the label. */ if (LABEL_NUSES (start_blk_3_lab) == 1) { @@ -2588,7 +2588,7 @@ conditionalize_block (rtx_insn *first) if (! start_blk_3_lab) return end_blk_2_insn; - + /* Return the insn right after the label at the start of block 3. */ return NEXT_INSN (start_blk_3_lab); } @@ -2597,8 +2597,8 @@ conditionalize_block (rtx_insn *first) outer loop that traverses through the insns scanning for a branch that signifies an opportunity to apply the optimization. Note that this optimization is applied late. If we could apply it earlier, - say before cse 2, it may expose more optimization opportunities. - but, the pay back probably isn't really worth the effort (we'd have + say before cse 2, it may expose more optimization opportunities. + but, the pay back probably isn't really worth the effort (we'd have to update all reg/flow/notes/links/etc to make it work - and stick it in before cse 2). */ @@ -2618,10 +2618,10 @@ mcore_reorg (void) { /* Reset this variable. */ current_function_anonymous_args = 0; - + if (optimize == 0) return; - + /* Conditionalize blocks where we can. */ conditionalize_optimization (); @@ -2687,7 +2687,7 @@ mcore_is_same_reg (rtx x, rtx y) /* Strip any and all of the subreg wrappers. */ while (GET_CODE (x) == SUBREG) x = SUBREG_REG (x); - + while (GET_CODE (y) == SUBREG) y = SUBREG_REG (y); @@ -2706,7 +2706,7 @@ mcore_option_override (void) } -/* Compute the number of word sized registers needed to +/* Compute the number of word sized registers needed to hold a function argument of mode MODE and type TYPE. */ int @@ -2745,11 +2745,11 @@ handle_structs_in_regs (machine_mode mode, const_tree type, int reg) && (size % UNITS_PER_WORD != 0) && (reg + mcore_num_arg_regs (mode, type) <= (FIRST_PARM_REG + NPARM_REGS))) { - rtx arg_regs [NPARM_REGS]; + rtx arg_regs [NPARM_REGS]; int nregs; rtx result; rtvec rtvec; - + for (nregs = 0; size > 0; size -= UNITS_PER_WORD) { arg_regs [nregs] = @@ -2762,11 +2762,11 @@ handle_structs_in_regs (machine_mode mode, const_tree type, int reg) gcc_assert (ARRAY_SIZE (arg_regs) == 6); rtvec = gen_rtvec (nregs, arg_regs[0], arg_regs[1], arg_regs[2], arg_regs[3], arg_regs[4], arg_regs[5]); - + result = gen_rtx_PARALLEL (mode, rtvec); return result; } - + return gen_rtx_REG (mode, reg); } @@ -2775,12 +2775,12 @@ mcore_function_value (const_tree valtype, const_tree func) { machine_mode mode; int unsigned_p; - + mode = TYPE_MODE (valtype); /* Since we promote return types, we must promote the mode here too. */ mode = promote_function_mode (valtype, mode, &unsigned_p, func, 1); - + return handle_structs_in_regs (mode, valtype, FIRST_RET_REG); } @@ -2801,7 +2801,7 @@ static rtx mcore_function_arg (cumulative_args_t cum, const function_arg_info &arg) { int arg_reg; - + if (!arg.named || arg.end_marker_p ()) return 0; @@ -2809,7 +2809,7 @@ mcore_function_arg (cumulative_args_t cum, const function_arg_info &arg) return 0; arg_reg = ROUND_REG (*get_cumulative_args (cum), arg.mode); - + if (arg_reg < NPARM_REGS) return handle_structs_in_regs (arg.mode, arg.type, FIRST_PARM_REG + arg_reg); @@ -2852,7 +2852,7 @@ mcore_arg_partial_bytes (cumulative_args_t cum, const function_arg_info &arg) if (targetm.calls.must_pass_in_stack (arg)) return 0; - + /* REG is not the *hardware* register number of the register that holds the argument, it is the *argument* register number. So for example, the first argument to a function goes in argument register 0, which @@ -2904,12 +2904,12 @@ mcore_mark_dllexport (tree decl) tree idp; rtlname = XEXP (DECL_RTL (decl), 0); - + if (GET_CODE (rtlname) == MEM) rtlname = XEXP (rtlname, 0); gcc_assert (GET_CODE (rtlname) == SYMBOL_REF); oldname = XSTR (rtlname, 0); - + if (mcore_dllexport_name_p (oldname)) return; /* Already done. */ @@ -2939,12 +2939,12 @@ mcore_mark_dllimport (tree decl) rtx newrtl; rtlname = XEXP (DECL_RTL (decl), 0); - + if (GET_CODE (rtlname) == MEM) rtlname = XEXP (rtlname, 0); gcc_assert (GET_CODE (rtlname) == SYMBOL_REF); oldname = XSTR (rtlname, 0); - + gcc_assert (!mcore_dllexport_name_p (oldname)); if (mcore_dllimport_name_p (oldname)) return; /* Already done. */ @@ -2960,7 +2960,7 @@ mcore_mark_dllimport (tree decl) error ("initialized variable %q+D is marked dllimport", decl); return; } - + /* `extern' needn't be specified with dllimport. Specify `extern' now and hope for the best. Sigh. */ if (VAR_P (decl) @@ -3019,7 +3019,7 @@ mcore_encode_section_info (tree decl, rtx rtl ATTRIBUTE_UNUSED, int first ATTRIB mcore_mark_dllexport (decl); else if (mcore_dllimport_p (decl)) mcore_mark_dllimport (decl); - + /* It might be that DECL has already been marked as dllimport, but a subsequent definition nullified that. The attribute is gone but DECL_RTL still has @i.__imp_foo. We need to remove that. */ @@ -3084,7 +3084,7 @@ mcore_unique_section (tree decl, int reloc ATTRIBUTE_UNUSED) const char * prefix; name = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl)); - + /* Strip off any encoding in name. */ name = (* targetm.strip_name_encoding) (name); @@ -3099,10 +3099,10 @@ mcore_unique_section (tree decl, int reloc ATTRIBUTE_UNUSED) prefix = ".rdata$"; else prefix = ".data$"; - + len = strlen (name) + strlen (prefix); string = XALLOCAVEC (char, len + 1); - + sprintf (string, "%s%s", prefix, name); set_decl_section_name (decl, string); @@ -3124,7 +3124,7 @@ mcore_warn_func_return (tree decl) #ifdef OBJECT_FORMAT_ELF static void -mcore_asm_named_section (const char *name, +mcore_asm_named_section (const char *name, unsigned int flags ATTRIBUTE_UNUSED, tree decl ATTRIBUTE_UNUSED) { @@ -3214,13 +3214,13 @@ mcore_reg_ok_for_base_p (const_rtx reg, bool strict_p) static bool mcore_base_register_rtx_p (const_rtx x, bool strict_p) { - return REG_P(x) && mcore_reg_ok_for_base_p (x, strict_p); + return REG_P(x) && mcore_reg_ok_for_base_p (x, strict_p); } /* A legitimate index for a QI is 0..15, for HI is 0..30, for SI is 0..60, and for DI is 0..56 because we use two SI loads, etc. */ -static bool +static bool mcore_legitimate_index_p (machine_mode mode, const_rtx op) { if (CONST_INT_P (op)) @@ -3237,11 +3237,11 @@ mcore_legitimate_index_p (machine_mode mode, const_rtx op) if (GET_MODE_SIZE (mode) == 1 && ((unsigned HOST_WIDE_INT) INTVAL (op)) <= 15) return true; - } + } return false; } - + /* Worker function for TARGET_ADDR_SPACE_LEGITIMATE_ADDRESS_P. Allow REG diff --git a/gcc/config/mcore/mcore.h b/gcc/config/mcore/mcore.h index 36dc860..17502e0 100644 --- a/gcc/config/mcore/mcore.h +++ b/gcc/config/mcore/mcore.h @@ -22,7 +22,7 @@ #define GCC_MCORE_H /* RBE: need to move these elsewhere. */ -#undef LIKE_PPC_ABI +#undef LIKE_PPC_ABI #define MCORE_STRUCT_ARGS /* RBE: end of "move elsewhere". */ @@ -80,7 +80,7 @@ #define TARGET_8ALIGN 1 extern char * mcore_current_function_name; - + /* Target machine storage Layout. */ #define PROMOTE_MODE(MODE,UNSIGNEDP,TYPE) \ @@ -136,7 +136,7 @@ extern char * mcore_current_function_name; /* Every structures size must be a multiple of 8 bits. */ #define STRUCTURE_SIZE_BOUNDARY 8 -/* Look at the fundamental type that is used for a bit-field and use +/* Look at the fundamental type that is used for a bit-field and use that to impose alignment on the enclosing structure. struct s {int a:8}; should have same alignment as "int", not "char". */ #define PCC_BITFIELD_TYPE_MATTERS 1 @@ -150,14 +150,14 @@ extern char * mcore_current_function_name; (TREE_CODE (TYPE) == ARRAY_TYPE \ && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \ && (ALIGN) < FASTEST_ALIGNMENT ? FASTEST_ALIGNMENT : (ALIGN)) - + /* Set this nonzero if move instructions will actually fail to work when given unaligned data. */ #define STRICT_ALIGNMENT 1 /* Standard register usage. */ -/* Register allocation for our first guess +/* Register allocation for our first guess r0 stack pointer r1 scratch, target reg for xtrb? @@ -333,7 +333,7 @@ extern const enum reg_class regno_reg_class[FIRST_PSEUDO_REGISTER]; but prevents the compiler from extending the lifetime of these registers. */ #define TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P hook_bool_mode_true - + /* The class value for index registers, and the one for base regs. */ #define INDEX_REG_CLASS NO_REGS #define BASE_REG_CLASS GENERAL_REGS @@ -369,7 +369,7 @@ extern const enum reg_class regno_reg_class[FIRST_PSEUDO_REGISTER]; mcore_secondary_reload_class (CLASS, MODE, X) /* Return the maximum number of consecutive registers - needed to represent mode MODE in a register of class CLASS. + needed to represent mode MODE in a register of class CLASS. On MCore this is the size of MODE in words. */ #define CLASS_MAX_NREGS(CLASS, MODE) \ @@ -434,9 +434,9 @@ extern const enum reg_class regno_reg_class[FIRST_PSEUDO_REGISTER]; #define ROUND_ADVANCE(SIZE) \ ((SIZE + UNITS_PER_WORD - 1) / UNITS_PER_WORD) -/* Round a register number up to a proper boundary for an arg of mode - MODE. - +/* Round a register number up to a proper boundary for an arg of mode + MODE. + We round to an even reg for things larger than a word. */ #define ROUND_REG(X, MODE) \ ((TARGET_8ALIGN \ @@ -486,7 +486,7 @@ extern const enum reg_class regno_reg_class[FIRST_PSEUDO_REGISTER]; #define REGNO_OK_FOR_INDEX_P(REGNO) 0 -/* Maximum number of registers that can appear in a valid memory +/* Maximum number of registers that can appear in a valid memory address. */ #define MAX_REGS_PER_ADDRESS 1 @@ -587,7 +587,7 @@ extern const enum reg_class regno_reg_class[FIRST_PSEUDO_REGISTER]; reg_names[STACK_POINTER_REGNUM], \ (STACK_BOUNDARY / BITS_PER_UNIT)) - + /* Output a reference to a label. */ #undef ASM_OUTPUT_LABELREF #define ASM_OUTPUT_LABELREF(STREAM, NAME) \ @@ -614,8 +614,8 @@ extern const enum reg_class regno_reg_class[FIRST_PSEUDO_REGISTER]; 0 a call from src to dst 1 the call is special (e.g. dst is "unknown" or "alloca") 2 the call is special (e.g., the src is a table instead of routine) - - Frame sizes are augmented with timestamps to help later tools + + Frame sizes are augmented with timestamps to help later tools differentiate between static entities with same names in different files. */ extern long mcore_current_compilation_timestamp; @@ -673,7 +673,7 @@ extern long mcore_current_compilation_timestamp; /* This says how to output an assembler line to define a global common symbol, with alignment information. */ -/* XXX - for now we ignore the alignment. */ +/* XXX - for now we ignore the alignment. */ #undef ASM_OUTPUT_ALIGNED_COMMON #define ASM_OUTPUT_ALIGNED_COMMON(FILE, NAME, SIZE, ALIGN) \ do \ diff --git a/gcc/config/microblaze/microblaze-c.cc b/gcc/config/microblaze/microblaze-c.cc index e60783e..52cc82b 100644 --- a/gcc/config/microblaze/microblaze-c.cc +++ b/gcc/config/microblaze/microblaze-c.cc @@ -30,10 +30,10 @@ #define builtin_define(TXT) cpp_define (pfile, TXT) #define builtin_assert(TXT) cpp_assert (pfile, TXT) -/* Define preprocessor symbols for MicroBlaze. +/* Define preprocessor symbols for MicroBlaze. Symbols which do not start with __ are deprecated. */ -void +void microblaze_cpp_define (cpp_reader *pfile) { builtin_assert ("cpu=microblaze"); @@ -52,7 +52,7 @@ microblaze_cpp_define (cpp_reader *pfile) builtin_define ("__BIG_ENDIAN__"); builtin_define ("__MICROBLAZEEB__"); } - if (!TARGET_SOFT_MUL) + if (!TARGET_SOFT_MUL) { if (!flag_iso) builtin_define ("HAVE_HW_MUL"); @@ -100,4 +100,4 @@ microblaze_cpp_define (cpp_reader *pfile) builtin_define ("HAVE_HW_FPU_SQRT"); builtin_define ("__HAVE_HW_FPU_SQRT__"); } -} +} diff --git a/gcc/config/microblaze/microblaze-protos.h b/gcc/config/microblaze/microblaze-protos.h index ae97cc2..7a25f03a 100644 --- a/gcc/config/microblaze/microblaze-protos.h +++ b/gcc/config/microblaze/microblaze-protos.h @@ -37,7 +37,7 @@ extern bool microblaze_expand_block_move (rtx, rtx, rtx, rtx); extern void microblaze_expand_divide (rtx *); extern void microblaze_expand_conditional_branch (machine_mode, rtx *); extern void microblaze_expand_conditional_branch_reg (machine_mode, rtx *); -extern void microblaze_expand_conditional_branch_sf (rtx *); +extern void microblaze_expand_conditional_branch_sf (rtx *); extern int microblaze_can_use_return_insn (void); extern void print_operand (FILE *, rtx, int); extern void print_operand_address (FILE *, rtx); @@ -65,6 +65,6 @@ extern void microblaze_eh_return (rtx op0); #endif /* RTX_CODE */ /* Declare functions in microblaze-c.cc. */ -extern void microblaze_cpp_define (struct cpp_reader *); +extern void microblaze_cpp_define (struct cpp_reader *); #endif /* GCC_MICROBLAZE_PROTOS_H */ diff --git a/gcc/config/microblaze/microblaze.cc b/gcc/config/microblaze/microblaze.cc index 98ec611..c036969 100644 --- a/gcc/config/microblaze/microblaze.cc +++ b/gcc/config/microblaze/microblaze.cc @@ -65,8 +65,8 @@ An invalid address. ADDRESS_REG -A natural register or a register + const_int offset address. -The register satisfies microblaze_valid_base_register_p and the +A natural register or a register + const_int offset address. +The register satisfies microblaze_valid_base_register_p and the offset is a const_arith_operand. ADDRESS_REG_INDEX @@ -99,7 +99,7 @@ enum microblaze_address_type /* Classifies symbols SYMBOL_TYPE_GENERAL - + A general symbol. */ enum microblaze_symbol_type { @@ -120,7 +120,7 @@ enum tls_reloc { struct microblaze_address_info { enum microblaze_address_type type; - rtx regA; /* Contains valid values on ADDRESS_REG, ADDRESS_REG_INDEX, + rtx regA; /* Contains valid values on ADDRESS_REG, ADDRESS_REG_INDEX, ADDRESS_SYMBOLIC. */ rtx regB; /* Contains valid values on ADDRESS_REG_INDEX. */ rtx offset; /* Contains valid values on ADDRESS_CONST_INT and ADDRESS_REG. */ @@ -143,7 +143,7 @@ struct GTY(()) microblaze_frame_info { int initialized; /* != 0 if frame size already calculated. */ int num_gp; /* number of gp registers saved. */ long insns_len; /* length of insns. */ - int alloc_stack; /* Flag to indicate if the current function + int alloc_stack; /* Flag to indicate if the current function must not create stack space. (As an optimization). */ }; @@ -158,18 +158,18 @@ static GTY(()) int microblaze_sched_use_dfa = 0; data area takes 2 instructions). */ int microblaze_section_threshold = -1; -/* Prevent scheduling potentially exception causing instructions in +/* Prevent scheduling potentially exception causing instructions in delay slots. -mcpu=v3.00.a or v4.00.a turns this on. */ int microblaze_no_unsafe_delay; /* Set to one if the targeted core has the CLZ insn. */ int microblaze_has_clz = 0; -/* Which CPU pipeline do we use. We haven't really standardized on a CPU - version having only a particular type of pipeline. There can still be - options on the CPU to scale pipeline features up or down. :( - Bad Presentation (??), so we let the MD file rely on the value of - this variable instead Making PIPE_5 the default. It should be backward +/* Which CPU pipeline do we use. We haven't really standardized on a CPU + version having only a particular type of pipeline. There can still be + options on the CPU to scale pipeline features up or down. :( + Bad Presentation (??), so we let the MD file rely on the value of + this variable instead Making PIPE_5 the default. It should be backward optimal with PIPE_3 MicroBlazes. */ enum pipeline_type microblaze_pipe = MICROBLAZE_PIPE_5; @@ -210,7 +210,7 @@ enum reg_class microblaze_regno_to_class[] = }; /* MicroBlaze specific machine attributes. - interrupt_handler - Interrupt handler attribute to add interrupt prologue + interrupt_handler - Interrupt handler attribute to add interrupt prologue and epilogue and use appropriate interrupt return. save_volatiles - Similar to interrupt handler, but use normal return. */ int interrupt_handler; @@ -719,8 +719,8 @@ get_base_reg (rtx x) const_int ADDRESS_REG_INDEX %0 %1 NULL NULL - ADDRESS_SYMBOLIC r0 / NULL NULL symbol - sda_base_reg + ADDRESS_SYMBOLIC r0 / NULL NULL symbol + sda_base_reg ADDRESS_CONST_INT r0 NULL const NULL @@ -1005,7 +1005,7 @@ microblaze_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED, result = gen_rtx_PLUS (Pmode, ptr_reg, constant); if (SMALL_INT (constant)) return result; - /* Otherwise we fall through so the code below will fix the + /* Otherwise we fall through so the code below will fix the constant. */ xinsn = result; } @@ -1363,7 +1363,7 @@ microblaze_rtx_costs (rtx x, machine_mode mode, int outer_code ATTRIBUTE_UNUSED, *total -= 2; } else - /* Double the worst cost of shifts when there is no barrel shifter and + /* Double the worst cost of shifts when there is no barrel shifter and the shift amount is in a reg. */ *total = COSTS_N_INSNS (32 * 4); return true; @@ -1498,7 +1498,7 @@ microblaze_address_cost (rtx addr, machine_mode mode ATTRIBUTE_UNUSED, return COSTS_N_INSNS (microblaze_address_insns (addr, GET_MODE (addr))); } -/* Return nonzero if X is an address which needs a temporary register when +/* Return nonzero if X is an address which needs a temporary register when reloaded while generating PIC code. */ int @@ -1680,7 +1680,7 @@ function_arg_partial_bytes (cumulative_args_t cum_v, return 0; } -/* Convert a version number of the form "vX.YY.Z" to an integer encoding +/* Convert a version number of the form "vX.YY.Z" to an integer encoding for easier range comparison. */ static int microblaze_version_to_int (const char *version) @@ -1794,7 +1794,7 @@ microblaze_option_override (void) } else { - /* We agree to use 5 pipe-stage model even on area optimized 3 + /* We agree to use 5 pipe-stage model even on area optimized 3 pipe-stage variants. */ #if 0 microblaze_select_flags &= ~(MICROBLAZE_MASK_NO_UNSAFE_DELAY); @@ -1807,7 +1807,7 @@ microblaze_option_override (void) || MICROBLAZE_VERSION_COMPARE (microblaze_select_cpu, "v5.00.c") == 0) { - /* Pattern compares are to be turned on by default only when + /* Pattern compares are to be turned on by default only when compiling for MB v5.00.'z'. */ target_flags |= MASK_PATTERN_COMPARE; } @@ -2039,7 +2039,7 @@ microblaze_must_save_register (int regno) if (microblaze_is_interrupt_variant ()) { - if (df_regs_ever_live_p (regno) + if (df_regs_ever_live_p (regno) || regno == MB_ABI_MSR_SAVE_REG || ((interrupt_handler || fast_interrupt) && (regno == MB_ABI_ASM_TEMP_REGNUM @@ -2109,7 +2109,7 @@ microblaze_must_save_register (int regno) */ static HOST_WIDE_INT -compute_frame_size (HOST_WIDE_INT size) +compute_frame_size (HOST_WIDE_INT size) { int regno; HOST_WIDE_INT total_size; /* # bytes that the entire frame takes up. */ @@ -2207,7 +2207,7 @@ microblaze_can_eliminate (const int from, const int to) } /* Implement INITIAL_ELIMINATION_OFFSET. FROM is either the frame - pointer or argument pointer or the return address pointer. TO is either + pointer or argument pointer or the return address pointer. TO is either the stack pointer or hard frame pointer. */ HOST_WIDE_INT @@ -2240,7 +2240,7 @@ microblaze_initial_elimination_offset (int from, int to) } /* Print operands using format code. - + The MicroBlaze specific codes are: 'X' X is CONST_INT, prints 32 bits in hexadecimal format = "0x%08x", @@ -2267,7 +2267,7 @@ microblaze_initial_elimination_offset (int from, int to) 'j' Print low word of const_double (int or float) value as hex 's' Print -1 if operand is negative, 0 if positive (sign extend) '@' Print the name of the temporary register (rMB_ABI_ASM_TEMP_REGNUM). - '#' Print nop if the delay slot of a branch is not filled. + '#' Print nop if the delay slot of a branch is not filled. */ void @@ -2463,7 +2463,7 @@ print_operand (FILE * file, rtx op, int letter) val[1] = INTVAL (op) & 0x00000000ffffffffLL; if (val[0] == 0 && val[1] < 0) val[0] = -1; - + } fprintf (file, "0x%8.8lx", (letter == 'h') ? val[0] : val[1]); } @@ -2543,19 +2543,19 @@ print_operand (FILE * file, rtx op, int letter) reference whose address is ADDR. ADDR is an RTL expression. Possible address classifications and output formats are, - + ADDRESS_REG "%0, r0" ADDRESS_REG with non-zero "%0, <addr_const>" - offset + offset - ADDRESS_REG_INDEX "rA, RB" + ADDRESS_REG_INDEX "rA, RB" (if rA is r0, rA and rB are swapped) ADDRESS_CONST_INT "r0, <addr_const>" - ADDRESS_SYMBOLIC "rBase, <addr_const>" - (rBase is a base register suitable for the + ADDRESS_SYMBOLIC "rBase, <addr_const>" + (rBase is a base register suitable for the symbol's type) */ @@ -2576,7 +2576,7 @@ print_operand_address (FILE * file, rtx addr) break; case ADDRESS_REG_INDEX: if (REGNO (info.regA) == 0) - /* Make rB == r0 instead of rA == r0. This helps reduce read port + /* Make rB == r0 instead of rA == r0. This helps reduce read port congestion. */ fprintf (file, "%s,%s", reg_names[REGNO (info.regB)], reg_names[REGNO (info.regA)]); @@ -2641,7 +2641,7 @@ print_operand_address (FILE * file, rtx addr) } /* Emit either a label, .comm, or .lcomm directive, and mark that the symbol - is used, so that we don't emit an .extern for it in + is used, so that we don't emit an .extern for it in microblaze_asm_file_end. */ void @@ -2649,7 +2649,7 @@ microblaze_declare_object (FILE * stream, const char *name, const char *section, const char *fmt, int size) { - fputs (section, stream); + fputs (section, stream); assemble_name (stream, name); fprintf (stream, fmt, size); } @@ -2662,7 +2662,7 @@ microblaze_declare_object (FILE * stream, const char *name, #define BITSET_P(VALUE,BIT) (((VALUE) & (1L << (BIT))) != 0) -/* Save or restore instructions based on whether this is the prologue or +/* Save or restore instructions based on whether this is the prologue or epilogue. prologue is 1 for the prologue. */ static void save_restore_insns (int prologue) @@ -2892,7 +2892,7 @@ microblaze_expand_prologue (void) && !cfun->returns_pcc_struct) { tree type = build_pointer_type (fntype); - tree function_result_decl = build_decl (BUILTINS_LOCATION, PARM_DECL, + tree function_result_decl = build_decl (BUILTINS_LOCATION, PARM_DECL, NULL_TREE, type); DECL_ARG_TYPE (function_result_decl) = type; @@ -3108,7 +3108,7 @@ microblaze_expand_epilogue (void) rtx reg_rtx; rtx mem_rtx; - /* In case of interrupt handlers use addki instead of addi for changing the + /* In case of interrupt handlers use addki instead of addi for changing the stack pointer value. */ if (microblaze_can_use_return_insn ()) @@ -3121,9 +3121,9 @@ microblaze_expand_epilogue (void) if (fsiz > 0) { - /* Restore SUB_RETURN_ADDR_REGNUM at first. This is to prevent the - sequence of load-followed by a use (in rtsd) in every prologue. Saves - a load-use stall cycle :) This is also important to handle alloca. + /* Restore SUB_RETURN_ADDR_REGNUM at first. This is to prevent the + sequence of load-followed by a use (in rtsd) in every prologue. Saves + a load-use stall cycle :) This is also important to handle alloca. (See comments for if (frame_pointer_needed) below. */ if (!crtl->is_leaf || interrupt_handler) @@ -3138,11 +3138,11 @@ microblaze_expand_epilogue (void) emit_move_insn (reg_rtx, mem_rtx); } - /* It is important that this is done after we restore the return address - register (above). When alloca is used, we want to restore the - sub-routine return address only from the current stack top and not - from the frame pointer (which we restore below). (frame_pointer + 0) - might have been over-written since alloca allocates memory on the + /* It is important that this is done after we restore the return address + register (above). When alloca is used, we want to restore the + sub-routine return address only from the current stack top and not + from the frame pointer (which we restore below). (frame_pointer + 0) + might have been over-written since alloca allocates memory on the current stack. */ if (frame_pointer_needed) emit_insn (gen_movsi (stack_pointer_rtx, hard_frame_pointer_rtx)); @@ -3186,8 +3186,8 @@ microblaze_can_use_return_insn (void) /* Implement TARGET_SECONDARY_RELOAD. */ static reg_class_t -microblaze_secondary_reload (bool in_p ATTRIBUTE_UNUSED, rtx x ATTRIBUTE_UNUSED, - reg_class_t rclass, machine_mode mode ATTRIBUTE_UNUSED, +microblaze_secondary_reload (bool in_p ATTRIBUTE_UNUSED, rtx x ATTRIBUTE_UNUSED, + reg_class_t rclass, machine_mode mode ATTRIBUTE_UNUSED, secondary_reload_info *sri ATTRIBUTE_UNUSED) { if (rclass == ST_REGS) @@ -3263,7 +3263,7 @@ microblaze_select_section (tree decl, int reloc, unsigned HOST_WIDE_INT align) case SECCAT_RODATA_MERGE_STR: case SECCAT_RODATA_MERGE_STR_INIT: /* MB binutils have various issues with mergeable string sections and - relaxation/relocation. Currently, turning mergeable sections + relaxation/relocation. Currently, turning mergeable sections into regular readonly sections. */ return readonly_data_section; @@ -3274,7 +3274,7 @@ microblaze_select_section (tree decl, int reloc, unsigned HOST_WIDE_INT align) /* Encode info about sections into the RTL based on a symbol's declaration. - The default definition of this hook, default_encode_section_info in + The default definition of this hook, default_encode_section_info in `varasm.cc', sets a number of commonly-useful bits in SYMBOL_REF_FLAGS. */ static void @@ -3521,7 +3521,7 @@ microblaze_eh_return (rtx op0) If the string size is below the threshold, put it into .sdata2. If the front-end is done, we must be being called from toplev.cc. In that case, do nothing. */ -void +void microblaze_asm_output_ident (const char *string) { const char *section_asm_op; @@ -3695,7 +3695,7 @@ microblaze_expand_divide (rtx operands[]) { /* Table lookup software divides. Works for all (nr/dr) where (0 <= nr,dr <= 15). */ - rtx regt1 = gen_reg_rtx (SImode); + rtx regt1 = gen_reg_rtx (SImode); rtx reg18 = gen_rtx_REG (SImode, R_TMP); rtx regqi = gen_reg_rtx (QImode); rtx_code_label *div_label = gen_label_rtx (); @@ -3707,9 +3707,9 @@ microblaze_expand_divide (rtx operands[]) insn = emit_insn (gen_iorsi3 (regt1, operands[1], operands[2])); cjump = emit_jump_insn_after (gen_cbranchsi4 ( - gen_rtx_GTU (SImode, regt1, GEN_INT (15)), + gen_rtx_GTU (SImode, regt1, GEN_INT (15)), regt1, GEN_INT (15), div_label), insn); - LABEL_NUSES (div_label) = 1; + LABEL_NUSES (div_label) = 1; JUMP_LABEL (cjump) = div_label; emit_insn (gen_rtx_CLOBBER (SImode, reg18)); @@ -3718,21 +3718,21 @@ microblaze_expand_divide (rtx operands[]) mem_rtx = gen_rtx_MEM (QImode, gen_rtx_PLUS (Pmode, regt1, div_table_rtx)); - insn = emit_insn (gen_movqi (regqi, mem_rtx)); + insn = emit_insn (gen_movqi (regqi, mem_rtx)); insn = emit_insn (gen_movsi (operands[0], gen_rtx_SUBREG (SImode, regqi, 0))); - jump = emit_jump_insn_after (gen_jump (div_end_label), insn); + jump = emit_jump_insn_after (gen_jump (div_end_label), insn); JUMP_LABEL (jump) = div_end_label; - LABEL_NUSES (div_end_label) = 1; + LABEL_NUSES (div_end_label) = 1; emit_barrier (); emit_label (div_label); - ret = emit_library_call_value (gen_rtx_SYMBOL_REF (Pmode, "__divsi3"), + ret = emit_library_call_value (gen_rtx_SYMBOL_REF (Pmode, "__divsi3"), operands[0], LCT_NORMAL, GET_MODE (operands[0]), operands[1], GET_MODE (operands[1]), operands[2], GET_MODE (operands[2])); if (ret != operands[0]) - emit_move_insn (operands[0], ret); + emit_move_insn (operands[0], ret); emit_label (div_end_label); emit_insn (gen_blockage ()); @@ -4014,7 +4014,7 @@ microblaze_starting_frame_offset (void) #define TARGET_LEGITIMIZE_ADDRESS microblaze_legitimize_address #undef TARGET_LEGITIMATE_ADDRESS_P -#define TARGET_LEGITIMATE_ADDRESS_P microblaze_legitimate_address_p +#define TARGET_LEGITIMATE_ADDRESS_P microblaze_legitimate_address_p #undef TARGET_FRAME_POINTER_REQUIRED #define TARGET_FRAME_POINTER_REQUIRED microblaze_frame_pointer_required @@ -4029,7 +4029,7 @@ microblaze_starting_frame_offset (void) #define TARGET_PROMOTE_FUNCTION_MODE default_promote_function_mode_always_promote #undef TARGET_FUNCTION_VALUE -#define TARGET_FUNCTION_VALUE microblaze_function_value +#define TARGET_FUNCTION_VALUE microblaze_function_value #undef TARGET_SECONDARY_RELOAD #define TARGET_SECONDARY_RELOAD microblaze_secondary_reload @@ -4047,7 +4047,7 @@ microblaze_starting_frame_offset (void) #define TARGET_ASM_INIT_SECTIONS microblaze_elf_asm_init_sections #undef TARGET_OPTION_OVERRIDE -#define TARGET_OPTION_OVERRIDE microblaze_option_override +#define TARGET_OPTION_OVERRIDE microblaze_option_override #undef TARGET_LEGITIMATE_CONSTANT_P #define TARGET_LEGITIMATE_CONSTANT_P microblaze_legitimate_constant_p diff --git a/gcc/config/microblaze/microblaze.h b/gcc/config/microblaze/microblaze.h index 5d28abf..a56b9de 100644 --- a/gcc/config/microblaze/microblaze.h +++ b/gcc/config/microblaze/microblaze.h @@ -68,8 +68,8 @@ extern enum pipeline_type microblaze_pipe; /* The default is to not need GOT for TLS. */ #define TLS_NEEDS_GOT 0 -/* What is the default setting for -mcpu= . We set it to v4.00.a even though - we are actually ahead. This is safest version that has generate code +/* What is the default setting for -mcpu= . We set it to v4.00.a even though + we are actually ahead. This is safest version that has generate code compatible for the original ISA */ #define MICROBLAZE_DEFAULT_CPU "v4.00.a" @@ -142,7 +142,7 @@ extern enum pipeline_type microblaze_pipe; #define MB_ABI_SUB_RETURN_ADDR_REGNUM 15 #define MB_ABI_DEBUG_RETURN_ADDR_REGNUM 16 #define MB_ABI_EXCEPTION_RETURN_ADDR_REGNUM 17 -#define MB_ABI_ASM_TEMP_REGNUM 18 +#define MB_ABI_ASM_TEMP_REGNUM 18 /* This is our temp register. */ #define MB_ABI_FRAME_POINTER_REGNUM 19 #define MB_ABI_PIC_ADDR_REGNUM 20 @@ -157,7 +157,7 @@ extern enum pipeline_type microblaze_pipe; #define MB_ABI_STATIC_CHAIN_REGNUM 3 #define MB_ABI_TEMP1_REGNUM 11 #define MB_ABI_TEMP2_REGNUM 12 -#define MB_ABI_MSR_SAVE_REG 11 +#define MB_ABI_MSR_SAVE_REG 11 /* Volatile register used to save MSR in interrupt handlers. */ @@ -177,8 +177,8 @@ extern enum pipeline_type microblaze_pipe; (GP_REG_FIRST + MB_ABI_SUB_RETURN_ADDR_REGNUM) /* Initial state of return address on entry to func = R15. - Actually, the RA is at R15+8, but gcc doesn't know how - to generate this. + Actually, the RA is at R15+8, but gcc doesn't know how + to generate this. NOTE: GDB has a workaround and expects this incorrect value. If this is fixed, a corresponding fix to GDB is needed. */ #define INCOMING_RETURN_ADDR_RTX \ @@ -294,7 +294,7 @@ extern enum pipeline_type microblaze_pipe; rMB_ABI_INTR_RETUREN_ADDR_REGNUM is a fixed register(return address for interrupt), and will not be used for anything else. */ - + #define FRAME_POINTER_REGNUM FRP_REG_NUM #define HARD_FRAME_POINTER_REGNUM \ (GP_REG_FIRST + MB_ABI_FRAME_POINTER_REGNUM) @@ -383,7 +383,7 @@ extern enum reg_class microblaze_regno_to_class[]; && (((VALUE) & 0x0000ffff) != 0 \ || (((VALUE) & ~2147483647) != 0 \ && ((VALUE) & ~2147483647) != ~2147483647))) - + #define PREFERRED_RELOAD_CLASS(X,CLASS) \ ((CLASS) != ALL_REGS \ ? (CLASS) \ @@ -470,7 +470,7 @@ typedef struct microblaze_args int fp_code; /* Mode of FP arguments */ int num_adjusts; /* number of adjustments made */ /* Adjustments made to args pass in regs. */ - /* ??? The size is doubled to work around a bug in the code that sets the + /* ??? The size is doubled to work around a bug in the code that sets the adjustments in function_arg. */ rtx adjust[MAX_ARGS_IN_REGISTERS * 2]; } CUMULATIVE_ARGS; @@ -512,7 +512,7 @@ typedef struct microblaze_args #define MAX_REGS_PER_ADDRESS 2 -/* Identify valid constant addresses. Exclude if PIC addr which +/* Identify valid constant addresses. Exclude if PIC addr which needs scratch register. */ #define CONSTANT_ADDRESS_P(X) microblaze_constant_address_p(X) @@ -608,7 +608,7 @@ typedef struct microblaze_args /* ASM_OUTPUT_ALIGNED_COMMON and ASM_OUTPUT_ALIGNED_LOCAL Unfortunately, we still need to set the section explicitly. Somehow, - our binutils assign .comm and .lcomm variables to the "current" section + our binutils assign .comm and .lcomm variables to the "current" section in the assembly file, rather than where they implicitly belong. We need to remove this explicit setting in GCC when binutils can understand sections better. */ @@ -836,11 +836,11 @@ do { \ #undef TARGET_ASM_NAMED_SECTION #define TARGET_ASM_NAMED_SECTION default_elf_asm_named_section -/* Define the strings to put out for each section in the object file. - - Note: For ctors/dtors, we want to give these sections the SHF_WRITE - attribute to allow shared libraries to patch/resolve addresses into - these locations. On Microblaze, there is no concept of shared libraries +/* Define the strings to put out for each section in the object file. + + Note: For ctors/dtors, we want to give these sections the SHF_WRITE + attribute to allow shared libraries to patch/resolve addresses into + these locations. On Microblaze, there is no concept of shared libraries yet, so this is for future use. */ #define TEXT_SECTION_ASM_OP "\t.text" #define DATA_SECTION_ASM_OP "\t.data" @@ -865,7 +865,7 @@ do { \ "\tbrlid r15, " #FUNC "\n\t nop\n" \ TEXT_SECTION_ASM_OP); -/* We need to group -lm as well, since some Newlib math functions +/* We need to group -lm as well, since some Newlib math functions reference __errno! */ #undef LIB_SPEC #define LIB_SPEC \ diff --git a/gcc/config/mingw/winnt-cxx.cc b/gcc/config/mingw/winnt-cxx.cc index 621366e..0be8095 100644 --- a/gcc/config/mingw/winnt-cxx.cc +++ b/gcc/config/mingw/winnt-cxx.cc @@ -46,8 +46,8 @@ i386_pe_type_dllimport_p (tree decl) || DECL_TEMPLATE_INSTANTIATION (decl) || DECL_ARTIFICIAL (decl))) return false; - - /* Overrides of the class dllimport decls by out-of-class definitions are + + /* Overrides of the class dllimport decls by out-of-class definitions are handled by tree.cc:merge_dllimport_decl_attributes. */ return true; } @@ -74,16 +74,16 @@ i386_pe_type_dllexport_p (tree decl) return true; } -static inline void maybe_add_dllimport (tree decl) +static inline void maybe_add_dllimport (tree decl) { if (i386_pe_type_dllimport_p (decl)) DECL_DLLIMPORT_P (decl) = 1; } -static inline void maybe_add_dllexport (tree decl) +static inline void maybe_add_dllexport (tree decl) { if (i386_pe_type_dllexport_p (decl)) - { + { tree decl_attrs = DECL_ATTRIBUTES (decl); if (lookup_attribute ("dllexport", decl_attrs) != NULL_TREE) /* Already done. */ @@ -99,8 +99,8 @@ i386_pe_adjust_class_at_definition (tree t) tree member; gcc_assert (CLASS_TYPE_P (t)); - - + + if (lookup_attribute ("dllexport", TYPE_ATTRIBUTES (t)) != NULL_TREE) { tree tmv = TYPE_MAIN_VARIANT (t); @@ -125,7 +125,7 @@ i386_pe_adjust_class_at_definition (tree t) { tree thunk; maybe_add_dllexport (member); - + /* Also add the attribute to its thunks. */ for (thunk = DECL_THUNKS (member); thunk; thunk = TREE_CHAIN (thunk)) @@ -157,13 +157,13 @@ i386_pe_adjust_class_at_definition (tree t) { tree thunk; maybe_add_dllimport (member); - + /* Also add the attribute to its thunks. */ for (thunk = DECL_THUNKS (member); thunk; thunk = DECL_CHAIN (thunk)) maybe_add_dllimport (thunk); } - + /* Check vtables */ for (member = CLASSTYPE_VTABLES (t); member; member = DECL_CHAIN (member)) @@ -173,6 +173,6 @@ i386_pe_adjust_class_at_definition (tree t) /* We leave typeinfo tables alone. We can't mark TI objects as dllimport, since the address of a secondary VTT may be needed for static initialization of a primary VTT. VTT's of - dllimport'd classes should always be link-once COMDAT. */ + dllimport'd classes should always be link-once COMDAT. */ } } diff --git a/gcc/config/mingw/winnt.cc b/gcc/config/mingw/winnt.cc index fb4b8a4..9d433da 100644 --- a/gcc/config/mingw/winnt.cc +++ b/gcc/config/mingw/winnt.cc @@ -121,7 +121,7 @@ i386_pe_determine_dllexport_p (tree decl) if (TREE_CODE (decl) == FUNCTION_DECL && DECL_DECLARED_INLINE_P (decl) && !flag_keep_inline_dllexport) - return false; + return false; if (lookup_attribute ("dllexport", DECL_ATTRIBUTES (decl))) return true; @@ -186,11 +186,11 @@ gen_stdcall_or_fastcall_suffix (tree decl, tree id, bool fastcall) tree arg; function_args_iterator args_iter; - gcc_assert (TREE_CODE (decl) == FUNCTION_DECL); + gcc_assert (TREE_CODE (decl) == FUNCTION_DECL); if (prototype_p (type)) { - /* This attribute is ignored for variadic functions. */ + /* This attribute is ignored for variadic functions. */ if (stdarg_p (type)) return NULL_TREE; @@ -236,7 +236,7 @@ i386_pe_maybe_mangle_decl_assembler_name (tree decl, tree id) tree new_id = NULL_TREE; if (TREE_CODE (decl) == FUNCTION_DECL) - { + { unsigned int ccvt = ix86_get_callcvt (TREE_TYPE (decl)); if ((ccvt & IX86_CALLCVT_STDCALL) != 0) { @@ -280,7 +280,7 @@ i386_pe_assemble_visibility (tree decl, int) tree i386_pe_mangle_decl_assembler_name (tree decl, tree id) { - tree new_id = i386_pe_maybe_mangle_decl_assembler_name (decl, id); + tree new_id = i386_pe_maybe_mangle_decl_assembler_name (decl, id); return (new_id ? new_id : id); } @@ -336,7 +336,7 @@ mingw_pe_encode_section_info (tree decl, rtx rtl, int first) flags |= SYMBOL_FLAG_DLLEXPORT; else if (i386_pe_determine_dllimport_p (decl)) flags |= SYMBOL_FLAG_DLLIMPORT; - + SYMBOL_REF_FLAGS (symbol) = flags; } @@ -368,7 +368,7 @@ i386_pe_binds_local_p (const_tree exp) && DECL_DECLARED_INLINE_P (exp)) return false; #endif - + return default_binds_local_p_1 (exp, 0); } @@ -496,7 +496,7 @@ mingw_pe_asm_named_section (const char *name, unsigned int flags, *f++ ='d'; /* This is necessary for older versions of gas. */ *f++ ='r'; } - else + else { if (flags & SECTION_CODE) *f++ = 'x'; @@ -528,7 +528,7 @@ mingw_pe_asm_named_section (const char *name, unsigned int flags, Instead, have the linker pick one, without warning. If 'selectany' attribute has been specified, MS compiler sets 'discard' characteristic, rather than telling linker - to warn of size or content mismatch, so do the same. */ + to warn of size or content mismatch, so do the same. */ bool discard = (flags & SECTION_CODE) || (TREE_CODE (decl) != IDENTIFIER_NODE && lookup_attribute ("selectany", @@ -556,7 +556,7 @@ i386_pe_asm_output_aligned_decl_common (FILE *stream, tree decl, rounded += (BIGGEST_ALIGNMENT / BITS_PER_UNIT) - 1; rounded = (rounded / (BIGGEST_ALIGNMENT / BITS_PER_UNIT) * (BIGGEST_ALIGNMENT / BITS_PER_UNIT)); - + mingw_pe_maybe_record_exported_symbol (decl, name, 1); fprintf (stream, "\t.comm\t"); diff --git a/gcc/config/mips/frame-header-opt.cc b/gcc/config/mips/frame-header-opt.cc index 1e7260e..70abd19 100644 --- a/gcc/config/mips/frame-header-opt.cc +++ b/gcc/config/mips/frame-header-opt.cc @@ -207,7 +207,7 @@ callees_functions_use_frame_header (function *fn) { called_fn = DECL_STRUCT_FUNCTION (called_fn_tree); if (called_fn == NULL - || DECL_WEAK (called_fn_tree) + || DECL_WEAK (called_fn_tree) || has_inlined_assembly (called_fn) || !is_leaf_function (called_fn) || !called_fn->machine->does_not_use_frame_header) diff --git a/gcc/config/mips/mips.cc b/gcc/config/mips/mips.cc index cd5c597..3927553 100644 --- a/gcc/config/mips/mips.cc +++ b/gcc/config/mips/mips.cc @@ -2804,7 +2804,7 @@ mips_lwxs_address_p (rtx addr) return false; } -/* Return true if ADDR matches the pattern for the L{B,H,W,D}{,U}X load +/* Return true if ADDR matches the pattern for the L{B,H,W,D}{,U}X load indexed address instruction. Note that such addresses are not considered legitimate in the TARGET_LEGITIMATE_ADDRESS_P sense, because their use is so restricted. */ @@ -4455,7 +4455,7 @@ mips_rtx_costs (rtx x, machine_mode mode, int outer_code, + set_src_cost (XEXP (XEXP (x, 1), 0), mode, speed)); return true; } - + /* Fall through. */ case IOR: @@ -12546,7 +12546,7 @@ mips_output_probe_stack_range (rtx reg1, rtx reg2) /* Probe at TEST_ADDR, test if TEST_ADDR == LAST_ADDR and branch. */ xops[1] = reg2; strcpy (tmp, "%(%<bne\t%0,%1,"); - output_asm_insn (strcat (tmp, &loop_lab[1]), xops); + output_asm_insn (strcat (tmp, &loop_lab[1]), xops); if (TARGET_64BIT) output_asm_insn ("sd\t$0,0(%0)%)", xops); else @@ -13730,7 +13730,7 @@ mips_memory_move_cost (machine_mode mode, reg_class_t rclass, bool in) { return (mips_cost->memory_latency + memory_move_secondary_cost (mode, rclass, in)); -} +} /* Implement TARGET_SECONDARY_MEMORY_NEEDED. @@ -14998,7 +14998,7 @@ bool mips_fmadd_bypass (rtx_insn *out_insn, rtx_insn *in_insn) { int dst_reg, src_reg; - + gcc_assert (get_attr_type (in_insn) == TYPE_FMADD); gcc_assert (get_attr_type (out_insn) == TYPE_FMADD); diff --git a/gcc/config/mips/mips.h b/gcc/config/mips/mips.h index 84dd64d..fb696ed 100644 --- a/gcc/config/mips/mips.h +++ b/gcc/config/mips/mips.h @@ -1759,7 +1759,7 @@ FP_ASM_SPEC "\ optimised to use word loads. */ #define LOCAL_ALIGNMENT(TYPE, ALIGN) \ DATA_ALIGNMENT (TYPE, ALIGN) - + #define PAD_VARARGS_DOWN \ (targetm.calls.function_arg_padding (TYPE_MODE (type), type) == PAD_DOWNWARD) diff --git a/gcc/config/mips/sde.h b/gcc/config/mips/sde.h index 35ca431..d177b08f 100644 --- a/gcc/config/mips/sde.h +++ b/gcc/config/mips/sde.h @@ -45,7 +45,7 @@ along with GCC; see the file COPYING3. If not see "%{!EB:%{!EL:%(endian_spec)}}", \ \ /* Configuration-independent MIPS rules. */ \ - BASE_DRIVER_SELF_SPECS + BASE_DRIVER_SELF_SPECS /* Use trap rather than break for all but MIPS I ISA. Force -no-mips16, so that MIPS16 assembler code requires an explicit ".set mips16". diff --git a/gcc/config/mmix/mmix.cc b/gcc/config/mmix/mmix.cc index 167aea7..ce01438 100644 --- a/gcc/config/mmix/mmix.cc +++ b/gcc/config/mmix/mmix.cc @@ -761,7 +761,7 @@ mmix_function_value (const_tree valtype, if (!outgoing) return gen_rtx_REG (mode, MMIX_RETURN_VALUE_REGNUM); - + /* Return values that fit in a register need no special handling. There's no register hole when parameters are passed in global registers. */ diff --git a/gcc/config/mn10300/linux.h b/gcc/config/mn10300/linux.h index 8cfe0e1..0e51e95 100644 --- a/gcc/config/mn10300/linux.h +++ b/gcc/config/mn10300/linux.h @@ -18,7 +18,7 @@ You should have received a copy of the GNU General Public License along with GCC; see the file COPYING3. If not see <http://www.gnu.org/licenses/>. */ - + #undef PREFERRED_DEBUGGING_TYPE #define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG @@ -77,7 +77,7 @@ extern int mn10300_protect_label; asm_fprintf (FILE, "+"); \ asm_fprintf (FILE, "%U%s", real_name); \ } \ - while (0) + while (0) #undef SIZE_TYPE #undef PTRDIFF_TYPE diff --git a/gcc/config/mn10300/mn10300.cc b/gcc/config/mn10300/mn10300.cc index 1cf0811..fab4641 100644 --- a/gcc/config/mn10300/mn10300.cc +++ b/gcc/config/mn10300/mn10300.cc @@ -475,7 +475,7 @@ mn10300_print_operand_address (FILE *file, rtx addr) { rtx base = XEXP (addr, 0); rtx index = XEXP (addr, 1); - + if (REG_P (index) && !REG_OK_FOR_INDEX_P (index)) { rtx x = base; @@ -651,7 +651,7 @@ mn10300_get_live_callee_saved_regs (unsigned int * bytes_saved) for (i = 0x04000; i < 0x40000; i <<= 1) if ((mask & i) == 0) ++ count; - + mask |= 0x3c000; } @@ -748,7 +748,7 @@ static inline unsigned int popcount (unsigned int mask) { unsigned int count = 0; - + while (mask) { ++ count; @@ -1333,7 +1333,7 @@ mn10300_preferred_reload_class (rtx x, reg_class_t rclass) if (x == stack_pointer_rtx && rclass != SP_REGS) return (TARGET_AM33 ? GENERAL_REGS : ADDRESS_REGS); else if (MEM_P (x) - || (REG_P (x) + || (REG_P (x) && !HARD_REGISTER_P (x)) || (GET_CODE (x) == SUBREG && REG_P (SUBREG_REG (x)) @@ -1706,7 +1706,7 @@ mn10300_output_add (rtx operands[3], bool need_flags) src2_regnum = true_regnum (src2); src2_class = REGNO_REG_CLASS (src2_regnum); - + if (dest_regnum == src1_regnum) return "add %2,%0"; if (dest_regnum == src2_regnum) @@ -2296,7 +2296,7 @@ mn10300_register_move_cost (machine_mode mode ATTRIBUTE_UNUSED, move cost above. This is not a problem. */ static int -mn10300_memory_move_cost (machine_mode mode ATTRIBUTE_UNUSED, +mn10300_memory_move_cost (machine_mode mode ATTRIBUTE_UNUSED, reg_class_t iclass, bool in ATTRIBUTE_UNUSED) { enum reg_class rclass = (enum reg_class) iclass; @@ -2410,7 +2410,7 @@ mn10300_rtx_costs (rtx x, machine_mode mode, int outer_code, } } goto do_arith_costs; - + case MINUS: case AND: case IOR: @@ -2533,7 +2533,7 @@ mn10300_trampoline_init (rtx m_tramp, tree fndecl, rtx chain_value) 0xdc jmp fnaddr <disp> - Note that the two extra insns are effectively nops; they + Note that the two extra insns are effectively nops; they clobber the flags but do not affect the contents of D0 or D1. */ disp = expand_binop (SImode, sub_optab, fnaddr, @@ -2631,7 +2631,7 @@ mn10300_hard_regno_mode_ok (unsigned int regno, machine_mode mode) || (TARGET_AM33 && REGNO_REG_CLASS (regno) == ADDRESS_REGS) || REGNO_REG_CLASS (regno) == EXTENDED_REGS) return GET_MODE_SIZE (mode) <= 4; - + return false; } @@ -2906,14 +2906,14 @@ mn10300_match_ccmode (rtx insn, machine_mode cc_mode) } /* This function is used to help split: - + (set (reg) (and (reg) (int))) - + into: - + (set (reg) (shift (reg) (int)) (set (reg) (shift (reg) (int)) - + where the shitfs will be shorter than the "and" insn. It returns the number of bits that should be shifted. A positive @@ -3038,7 +3038,7 @@ check_liw_constraints (struct liw_data * pliw1, struct liw_data * pliw2) check its values prior to any changes made by OP. */ if (pliw1->op == LIW_OP_CMP) { - /* Two sequential comparisons means dead code, which ought to + /* Two sequential comparisons means dead code, which ought to have been eliminated given that bundling only happens with optimization. We cannot bundle them in any case. */ gcc_assert (pliw1->op != pliw2->op); @@ -3076,7 +3076,7 @@ check_liw_constraints (struct liw_data * pliw1, struct liw_data * pliw2) || pliw2->op == LIW_OP_OR || pliw2->op == LIW_OP_XOR)) return false; - + pliw2->src = pliw1->src; return true; } @@ -3114,7 +3114,7 @@ mn10300_bundle_liw (void) if (liw1.slot == LIW_OP2 || liw2.slot == LIW_OP1) { struct liw_data temp; - + temp = liw1; liw1 = liw2; liw2 = temp; @@ -3191,7 +3191,7 @@ mn10300_insert_setlb_lcc (rtx_insn *label, rtx_insn *branch) if (GET_MODE (cmp_reg) == CC_FLOATmode) lcc = gen_FLcc (comparison, label); else - lcc = gen_Lcc (comparison, label); + lcc = gen_Lcc (comparison, label); rtx_insn *jump = emit_jump_insn_before (lcc, branch); mark_jump_label (XVECEXP (lcc, 0, 0), jump, 0); @@ -3294,7 +3294,7 @@ mn10300_scan_for_setlb_lcc (void) loop_optimizer_finalize (); - df_finish_pass (false); + df_finish_pass (false); DUMP ("SETLB scan complete", NULL_RTX); } diff --git a/gcc/config/moxie/moxie.cc b/gcc/config/moxie/moxie.cc index 47a14ea..eda7b08 100644 --- a/gcc/config/moxie/moxie.cc +++ b/gcc/config/moxie/moxie.cc @@ -63,12 +63,12 @@ moxie_return_in_memory (const_tree type, const_tree fntype ATTRIBUTE_UNUSED) /* Define how to find the value returned by a function. VALTYPE is the data type of the value (as a tree). If the precise function being called is known, FUNC is its - FUNCTION_DECL; otherwise, FUNC is 0. + FUNCTION_DECL; otherwise, FUNC is 0. We always return values in register $r0 for moxie. */ static rtx -moxie_function_value (const_tree valtype, +moxie_function_value (const_tree valtype, const_tree fntype_or_decl ATTRIBUTE_UNUSED, bool outgoing ATTRIBUTE_UNUSED) { @@ -118,12 +118,12 @@ moxie_print_operand_address (FILE *file, machine_mode, rtx x) case REG: fprintf (file, "(%s)", reg_names[REGNO (x)]); break; - + case PLUS: switch (GET_CODE (XEXP (x, 1))) { case CONST_INT: - fprintf (file, "%ld(%s)", + fprintf (file, "%ld(%s)", INTVAL(XEXP (x, 1)), reg_names[REGNO (XEXP (x, 0))]); break; case SYMBOL_REF: @@ -133,7 +133,7 @@ moxie_print_operand_address (FILE *file, machine_mode, rtx x) case CONST: { rtx plus = XEXP (XEXP (x, 1), 0); - if (GET_CODE (XEXP (plus, 0)) == SYMBOL_REF + if (GET_CODE (XEXP (plus, 0)) == SYMBOL_REF && CONST_INT_P (XEXP (plus, 1))) { output_addr_const(file, XEXP (plus, 0)); @@ -234,7 +234,7 @@ moxie_option_override (void) /* Set the per-function-data initializer. */ init_machine_status = moxie_init_machine_status; -#ifdef TARGET_MOXIEBOX +#ifdef TARGET_MOXIEBOX target_flags |= MASK_HAS_MULX; #endif } @@ -267,9 +267,9 @@ moxie_compute_frame (void) if (df_regs_ever_live_p (regno) && (! call_used_or_fixed_reg_p (regno))) cfun->machine->callee_saved_reg_size += 4; - cfun->machine->size_for_adjusting_sp = + cfun->machine->size_for_adjusting_sp = crtl->args.pretend_args_size - + cfun->machine->local_vars_size + + cfun->machine->local_vars_size + (ACCUMULATE_OUTGOING_ARGS ? (HOST_WIDE_INT) crtl->outgoing_args_size : 0); } @@ -298,19 +298,19 @@ moxie_expand_prologue (void) if (cfun->machine->size_for_adjusting_sp > 0) { - int i = cfun->machine->size_for_adjusting_sp; + int i = cfun->machine->size_for_adjusting_sp; while ((i >= 255) && (i <= 510)) { - insn = emit_insn (gen_subsi3 (stack_pointer_rtx, - stack_pointer_rtx, + insn = emit_insn (gen_subsi3 (stack_pointer_rtx, + stack_pointer_rtx, GEN_INT (255))); RTX_FRAME_RELATED_P (insn) = 1; i -= 255; } if (i <= 255) { - insn = emit_insn (gen_subsi3 (stack_pointer_rtx, - stack_pointer_rtx, + insn = emit_insn (gen_subsi3 (stack_pointer_rtx, + stack_pointer_rtx, GEN_INT (i))); RTX_FRAME_RELATED_P (insn) = 1; } @@ -319,8 +319,8 @@ moxie_expand_prologue (void) rtx reg = gen_rtx_REG (SImode, MOXIE_R12); insn = emit_move_insn (reg, GEN_INT (i)); RTX_FRAME_RELATED_P (insn) = 1; - insn = emit_insn (gen_subsi3 (stack_pointer_rtx, - stack_pointer_rtx, + insn = emit_insn (gen_subsi3 (stack_pointer_rtx, + stack_pointer_rtx, reg)); RTX_FRAME_RELATED_P (insn) = 1; } @@ -339,8 +339,8 @@ moxie_expand_epilogue (void) if (cfun->machine->callee_saved_reg_size <= 255) { emit_move_insn (reg, hard_frame_pointer_rtx); - emit_insn (gen_subsi3 - (reg, reg, + emit_insn (gen_subsi3 + (reg, reg, GEN_INT (cfun->machine->callee_saved_reg_size))); } else @@ -367,7 +367,7 @@ int moxie_initial_elimination_offset (int from, int to) { int ret; - + if ((from) == FRAME_POINTER_REGNUM && (to) == HARD_FRAME_POINTER_REGNUM) { /* Compute this since we need to use cfun->machine->local_vars_size. */ @@ -392,19 +392,19 @@ moxie_setup_incoming_varargs (cumulative_args_t cum_v, CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v); int regno; int regs = 8 - *cum; - + *pretend_size = regs < 0 ? 0 : GET_MODE_SIZE (SImode) * regs; - + if (no_rtl) return; - + for (regno = *cum; regno < 8; regno++) { rtx reg = gen_rtx_REG (SImode, regno); rtx slot = gen_rtx_PLUS (Pmode, gen_rtx_REG (SImode, ARG_POINTER_REGNUM), GEN_INT (UNITS_PER_WORD * (3 + (regno-2)))); - + emit_move_insn (gen_rtx_MEM (SImode, slot), reg); } } @@ -430,7 +430,7 @@ moxie_function_arg (cumulative_args_t cum_v, const function_arg_info &arg) if (*cum < 8) return gen_rtx_REG (arg.mode, *cum); - else + else return NULL_RTX; } @@ -567,7 +567,7 @@ moxie_reg_ok_for_base_p (const_rtx reg, bool strict_p) if (strict_p) return HARD_REGNO_OK_FOR_BASE_P (regno) || HARD_REGNO_OK_FOR_BASE_P (reg_renumber[regno]); - else + else return !HARD_REGISTER_NUM_P (regno) || HARD_REGNO_OK_FOR_BASE_P (regno); } diff --git a/gcc/config/moxie/moxie.h b/gcc/config/moxie/moxie.h index 4857c92..b2977e5 100644 --- a/gcc/config/moxie/moxie.h +++ b/gcc/config/moxie/moxie.h @@ -91,7 +91,7 @@ Special Registers... $pc - 32-bit program counter. - + */ #define REGISTER_NAMES { \ @@ -104,7 +104,7 @@ #define MOXIE_FP 0 #define MOXIE_SP 1 #define MOXIE_R0 2 -#define MOXIE_R1 3 +#define MOXIE_R1 3 #define MOXIE_R2 4 #define MOXIE_R3 5 #define MOXIE_R4 6 @@ -209,7 +209,7 @@ enum reg_class #define ACCUMULATE_OUTGOING_ARGS 1 /* A C statement (sans semicolon) for initializing the variable CUM - for the state at the beginning of the argument list. + for the state at the beginning of the argument list. For moxie, the first arg is passed in register 2 (aka $r0). */ #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,FNDECL,N_NAMED_ARGS) \ (CUM = MOXIE_R0) @@ -300,7 +300,7 @@ enum reg_class /* Every structures size must be a multiple of 8 bits. */ #define STRUCTURE_SIZE_BOUNDARY 8 -/* Look at the fundamental type that is used for a bit-field and use +/* Look at the fundamental type that is used for a bit-field and use that to impose alignment on the enclosing structure. struct s {int a:8}; should have same alignment as "int", not "char". */ #define PCC_BITFIELD_TYPE_MATTERS 1 @@ -314,7 +314,7 @@ enum reg_class (TREE_CODE (TYPE) == ARRAY_TYPE \ && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \ && (ALIGN) < FASTEST_ALIGNMENT ? FASTEST_ALIGNMENT : (ALIGN)) - + /* Set this nonzero if move instructions will actually fail to work when given unaligned data. */ #define STRICT_ALIGNMENT 1 @@ -351,7 +351,7 @@ enum reg_class #define ELIMINABLE_REGS \ {{ FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM }, \ - { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM }} + { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM }} /* This macro returns the initial difference between the specified pair of registers. */ diff --git a/gcc/config/netbsd.h b/gcc/config/netbsd.h index de72879..fe33f9a 100644 --- a/gcc/config/netbsd.h +++ b/gcc/config/netbsd.h @@ -131,7 +131,7 @@ along with GCC; see the file COPYING3. If not see #undef TARGET_LIBC_HAS_FUNCTION #define TARGET_LIBC_HAS_FUNCTION no_c99_libc_has_function -/* When building shared libraries, the initialization and finalization +/* When building shared libraries, the initialization and finalization functions for the library are .init and .fini respectively. */ #define COLLECT_SHARED_INIT_FUNC(STREAM,FUNC) \ diff --git a/gcc/config/nios2/elf.h b/gcc/config/nios2/elf.h index 44664c9..3efcdcf 100644 --- a/gcc/config/nios2/elf.h +++ b/gcc/config/nios2/elf.h @@ -1,6 +1,6 @@ /* Definitions of ELF target support for Altera Nios II. Copyright (C) 2012-2024 Free Software Foundation, Inc. - Contributed by Jonah Graham (jgraham@altera.com), + Contributed by Jonah Graham (jgraham@altera.com), Will Reece (wreece@altera.com), and Jeff DaSilva (jdasilva@altera.com). Contributed by Mentor Graphics, Inc. diff --git a/gcc/config/nios2/nios2.cc b/gcc/config/nios2/nios2.cc index a981e50..cb33c67 100644 --- a/gcc/config/nios2/nios2.cc +++ b/gcc/config/nios2/nios2.cc @@ -1,6 +1,6 @@ /* Target machine subroutines for Altera Nios II. Copyright (C) 2012-2024 Free Software Foundation, Inc. - Contributed by Jonah Graham (jgraham@altera.com), + Contributed by Jonah Graham (jgraham@altera.com), Will Reece (wreece@altera.com), and Jeff DaSilva (jdasilva@altera.com). Contributed by Mentor Graphics, Inc. @@ -343,7 +343,7 @@ static bool nios2_fpu_compare_enabled (enum rtx_code cond, machine_mode mode) { if (mode == SFmode) - switch (cond) + switch (cond) { case EQ: return N2FPU_OP_ENABLED_P (fcmpeqs); case NE: return N2FPU_OP_ENABLED_P (fcmpnes); @@ -354,7 +354,7 @@ nios2_fpu_compare_enabled (enum rtx_code cond, machine_mode mode) default: break; } else if (mode == DFmode) - switch (cond) + switch (cond) { case EQ: return N2FPU_OP_ENABLED_P (fcmpeqd); case NE: return N2FPU_OP_ENABLED_P (fcmpned); @@ -388,7 +388,7 @@ nios2_compute_frame_layout (void) if (cfun->machine->initialized) return cfun->machine->total_size; - + /* Calculate space needed for gp registers. */ save_reg_size = 0; for (regno = 0; regno <= LAST_GP_REG; regno++) @@ -434,7 +434,7 @@ nios2_compute_frame_layout (void) { unsigned i; unsigned r; - + for (i = 0; (r = EH_RETURN_DATA_REGNO (i)) != INVALID_REGNUM; i++) if (!(save_mask & (1 << r))) { @@ -552,7 +552,7 @@ nios2_create_cfa_notes (rtx_insn *insn, bool epilogue_p) #define TEMP_REG_NUM 8 /* Emit conditional trap for checking stack limit. SIZE is the number of - additional bytes required. + additional bytes required. GDB prologue analysis depends on this generating a direct comparison to the SP register, so the adjustment to add SIZE needs to be done on @@ -995,7 +995,7 @@ nios2_set_return_address (rtx address, rtx scratch) { unsigned offset = cfun->machine->save_reg_size - 4; rtx base; - + if (frame_pointer_needed) base = hard_frame_pointer_rtx; else @@ -1080,7 +1080,7 @@ static bool prologue_saved_reg_p (unsigned regno) { gcc_assert (GP_REG_P (regno)); - + if (df_regs_ever_live_p (regno) && !call_used_or_fixed_reg_p (regno)) return true; @@ -1135,7 +1135,7 @@ nios2_initial_elimination_offset (int from, int to) by the offset from the frame pointer to the stack pointer. */ if (to == HARD_FRAME_POINTER_REGNUM) offset -= (cfun->machine->save_regs_offset - + cfun->machine->fp_save_offset); + + cfun->machine->fp_save_offset); return offset; } @@ -1390,13 +1390,13 @@ nios2_option_override (void) /* Process -mgprel-sec= and -m0rel-sec=. */ if (nios2_gprel_sec) { - if (regcomp (&nios2_gprel_sec_regex, nios2_gprel_sec, + if (regcomp (&nios2_gprel_sec_regex, nios2_gprel_sec, REG_EXTENDED | REG_NOSUB)) error ("%<-mgprel-sec=%> argument is not a valid regular expression"); } if (nios2_r0rel_sec) { - if (regcomp (&nios2_r0rel_sec_regex, nios2_r0rel_sec, + if (regcomp (&nios2_r0rel_sec_regex, nios2_r0rel_sec, REG_EXTENDED | REG_NOSUB)) error ("%<-mr0rel-sec=%> argument is not a valid regular expression"); } @@ -1533,7 +1533,7 @@ nios2_rtx_costs (rtx x, machine_mode mode, *total = COSTS_N_INSNS (5); /* Guess? */ else if (speed) *total = COSTS_N_INSNS (2); /* Latency adjustment. */ - else + else *total = COSTS_N_INSNS (1); if (TARGET_HAS_MULX && GET_MODE (x) == DImode) { @@ -1557,7 +1557,7 @@ nios2_rtx_costs (rtx x, machine_mode mode, *total = COSTS_N_INSNS (5); /* Guess? */ else if (speed) *total = COSTS_N_INSNS (2); /* Latency adjustment. */ - else + else *total = COSTS_N_INSNS (1); return false; } @@ -1569,11 +1569,11 @@ nios2_rtx_costs (rtx x, machine_mode mode, { if (!speed) *total = COSTS_N_INSNS (1); - else + else *total = COSTS_N_INSNS (2); /* Latency adjustment. */ return false; } - + case ZERO_EXTRACT: if (TARGET_HAS_BMX) { @@ -1639,7 +1639,7 @@ nios2_call_tls_get_addr (rtx ti) rtx ret = gen_rtx_REG (Pmode, FIRST_RETVAL_REGNO); rtx fn; rtx_insn *insn; - + if (!nios2_tls_symbol) nios2_tls_symbol = init_one_libfunc ("__tls_get_addr"); @@ -2005,7 +2005,7 @@ nios2_validate_compare (machine_mode mode, rtx *cmp, rtx *op1, rtx *op2) } else if (!reg_or_0_operand (*op2, mode)) *op2 = force_reg (mode, *op2); - + check_rebuild_cmp: if (code == GT || code == GTU || code == LE || code == LEU) { @@ -2057,7 +2057,7 @@ nios2_symbolic_constant_p (rtx x) return false; } -/* Return true if X is an expression of the form +/* Return true if X is an expression of the form (PLUS reg large_constant). */ static bool nios2_plus_large_constant_p (rtx x) @@ -2134,7 +2134,7 @@ nios2_valid_addr_expr_p (rtx base, rtx offset, bool strict_p) && nios2_regno_ok_for_base_p (REGNO (base), strict_p) && (offset == NULL_RTX || nios2_valid_addr_offset_p (offset) - || (nios2_large_constant_allowed () + || (nios2_large_constant_allowed () && nios2_symbolic_constant_p (offset)) || nios2_unspec_reloc_p (offset))); } @@ -2159,7 +2159,7 @@ nios2_legitimate_address_p (machine_mode mode ATTRIBUTE_UNUSED, rtx operand, /* Else, fall through. */ case LABEL_REF: - if (nios2_large_constant_allowed () + if (nios2_large_constant_allowed () && nios2_symbolic_constant_p (operand)) return true; return false; @@ -2182,7 +2182,7 @@ nios2_legitimate_address_p (machine_mode mode ATTRIBUTE_UNUSED, rtx operand, rtx op0 = XEXP (operand, 0); rtx op1 = XEXP (operand, 1); - if (nios2_valid_addr_expr_p (op0, op1, strict_p) + if (nios2_valid_addr_expr_p (op0, op1, strict_p) || nios2_valid_addr_expr_p (op1, op0, strict_p)) return true; } @@ -2192,7 +2192,7 @@ nios2_legitimate_address_p (machine_mode mode ATTRIBUTE_UNUSED, rtx operand, This requires a 16-bit relocation and isn't valid with R2 io-variant load/stores. */ case LO_SUM: - if (TARGET_ARCH_R2 + if (TARGET_ARCH_R2 && (TARGET_BYPASS_CACHE || TARGET_BYPASS_CACHE_VOLATILE)) return false; else @@ -2216,18 +2216,18 @@ nios2_legitimate_address_p (machine_mode mode ATTRIBUTE_UNUSED, rtx operand, the (plus reg symbolic_constant) and (plus reg (const ...)) forms but giving (plus reg symbol_ref) address modes the same cost as those that don't require splitting. Also, from a theoretical point of view: - - This is in line with the recommendation in the GCC internals + - This is in line with the recommendation in the GCC internals documentation to make address forms involving multiple - registers more expensive than single-register forms. - - OTOH it still encourages fwprop1 to propagate constants into + registers more expensive than single-register forms. + - OTOH it still encourages fwprop1 to propagate constants into address expressions more aggressively. - We should discourage splitting (symbol + offset) into hi/lo pairs to allow CSE'ing the symbol when it's used with more than one offset, but not so heavily as to avoid this addressing mode at all. */ static int -nios2_address_cost (rtx address, +nios2_address_cost (rtx address, machine_mode mode ATTRIBUTE_UNUSED, - addr_space_t as ATTRIBUTE_UNUSED, + addr_space_t as ATTRIBUTE_UNUSED, bool speed ATTRIBUTE_UNUSED) { if (nios2_plus_large_constant_p (address)) @@ -2258,7 +2258,7 @@ nios2_large_constant_memory_operand_p (rtx x) } -/* Return true if X is something that needs to be split into a +/* Return true if X is something that needs to be split into a high/lo_sum pair. */ bool nios2_large_constant_p (rtx x) @@ -2269,8 +2269,8 @@ nios2_large_constant_p (rtx x) } /* Given an RTX X that satisfies nios2_large_constant_p, split it into - high and lo_sum parts using TEMP as a scratch register. Emit the high - instruction and return the lo_sum expression. + high and lo_sum parts using TEMP as a scratch register. Emit the high + instruction and return the lo_sum expression. Also handle special cases involving constant integers. */ rtx nios2_split_large_constant (rtx x, rtx temp) @@ -2293,7 +2293,7 @@ nios2_split_large_constant (rtx x, rtx temp) return gen_rtx_PLUS (Pmode, temp, gen_int_mode (low, Pmode)); } } - + emit_insn (gen_rtx_SET (temp, gen_rtx_HIGH (Pmode, copy_rtx (x)))); return gen_rtx_LO_SUM (Pmode, temp, copy_rtx (x)); } @@ -2317,7 +2317,7 @@ nios2_split_plus_large_constant (rtx op0, rtx op1) } /* Given a MEM OP with an address that includes a splittable symbol or - other large constant, emit some instructions to do the split and + other large constant, emit some instructions to do the split and return a new MEM. */ rtx nios2_split_large_constant_memory_operand (rtx op) @@ -2341,7 +2341,7 @@ nios2_small_section_name_p (const char *section) || startswith (section, ".sbss.") || strcmp (section, ".sdata") == 0 || startswith (section, ".sdata.") - || (nios2_gprel_sec + || (nios2_gprel_sec && regexec (&nios2_gprel_sec_regex, section, 0, NULL, 0) == 0)); } @@ -2349,7 +2349,7 @@ nios2_small_section_name_p (const char *section) static bool nios2_r0rel_section_name_p (const char *section) { - return (nios2_r0rel_sec + return (nios2_r0rel_sec && regexec (&nios2_r0rel_sec_regex, section, 0, NULL, 0) == 0); } @@ -2591,7 +2591,7 @@ nios2_legitimize_constant_address (rtx addr) base = nios2_legitimize_tls_address (base); else if (flag_pic) base = nios2_load_pic_address (base, UNSPEC_PIC_SYM, NULL_RTX); - else if (!nios2_large_constant_allowed () + else if (!nios2_large_constant_allowed () && nios2_symbolic_constant_p (addr)) return nios2_split_large_constant (addr, gen_reg_rtx (Pmode)); else if (CONST_INT_P (addr)) @@ -2625,7 +2625,7 @@ nios2_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED, machine_mode mode ATTRIBUTE_UNUSED) { rtx op0, op1; - + if (CONSTANT_P (x)) return nios2_legitimize_constant_address (x); @@ -2749,15 +2749,15 @@ nios2_emit_move_sequence (rtx *operands, machine_mode mode) } } else if (gprel_constant_p (from) || r0rel_constant_p (from)) - /* Handled directly by movsi_internal as gp + offset + /* Handled directly by movsi_internal as gp + offset or r0 + offset. */ ; else if (nios2_large_constant_p (from)) /* This case covers either a regular symbol reference or an UNSPEC - representing a 32-bit offset. We split the former + representing a 32-bit offset. We split the former only conditionally and the latter always. */ { - if (!nios2_large_constant_allowed () + if (!nios2_large_constant_allowed () || nios2_large_unspec_reloc_p (from)) { rtx lo = nios2_split_large_constant (from, to); @@ -2767,7 +2767,7 @@ nios2_emit_move_sequence (rtx *operands, machine_mode mode) return true; } } - else + else /* This is a TLS or PIC symbol. */ { from = nios2_legitimize_constant_address (from); @@ -2839,7 +2839,7 @@ nios2_print_operand_punct_valid_p (unsigned char code) z: prints the third register immediate operand in assembly instructions. Outputs const0_rtx as the 'zero' register instead of '0'. - + y: same as 'z', but for specifically for logical instructions, where the processing for immediates are slightly different. @@ -3292,7 +3292,7 @@ nios2_fpu_insn_asm (enum n2fpu_code code) static char buf[256]; const char *op1, *op2, *op3; int ln = 256, n = 0; - + int N = N2FPU_N (code); int num_operands = N2FPU (code).num_operands; const char *insn_name = N2FPU_NAME (code); @@ -3384,7 +3384,7 @@ nios2_fpu_insn_asm (enum n2fpu_code code) static rtx nios2_function_arg (cumulative_args_t cum_v, const function_arg_info &arg) { - CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v); + CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v); rtx return_rtx = NULL_RTX; if (cum->regs_used < NUM_ARG_REGS) @@ -3400,7 +3400,7 @@ nios2_function_arg (cumulative_args_t cum_v, const function_arg_info &arg) static int nios2_arg_partial_bytes (cumulative_args_t cum_v, const function_arg_info &arg) { - CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v); + CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v); HOST_WIDE_INT param_size = arg.promoted_size_in_bytes (); gcc_assert (param_size >= 0); @@ -3420,7 +3420,7 @@ static void nios2_function_arg_advance (cumulative_args_t cum_v, const function_arg_info &arg) { - CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v); + CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v); HOST_WIDE_INT param_size = arg.promoted_size_in_bytes (); gcc_assert (param_size >= 0); @@ -3517,7 +3517,7 @@ nios2_setup_incoming_varargs (cumulative_args_t cum_v, const function_arg_info &arg, int *pretend_size, int second_time) { - CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v); + CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v); CUMULATIVE_ARGS local_cum; cumulative_args_t local_cum_v = pack_cumulative_args (&local_cum); int regs_to_push; @@ -3838,8 +3838,8 @@ nios2_expand_builtin_insn (const struct nios2_builtin_desc *d, int n, else { error ("invalid argument to built-in function %s", d->name); - return has_target_p ? gen_reg_rtx (ops[0].mode) : const0_rtx; - } + return has_target_p ? gen_reg_rtx (ops[0].mode) : const0_rtx; + } } /* Expand ldio/stio and ldex/ldsex/stex/stsex form load-store @@ -3954,7 +3954,7 @@ nios2_expand_cache_builtin (tree exp, rtx target ATTRIBUTE_UNUSED, mem = gen_rtx_MEM (SImode, addr); create_input_operand (&ops[0], mem, SImode); - + return nios2_expand_builtin_insn (d, 1, ops, false); } @@ -3968,7 +3968,7 @@ nios2_expand_wrpie_builtin (tree exp, rtx target, val = expand_normal (CALL_EXPR_ARG (exp, 0)); create_input_operand (&ops[1], val, SImode); create_output_operand (&ops[0], target, SImode); - + return nios2_expand_builtin_insn (d, 2, ops, true); } @@ -3982,10 +3982,10 @@ nios2_expand_eni_builtin (tree exp, rtx target ATTRIBUTE_UNUSED, if (INTVAL (imm) != 0 && INTVAL (imm) != 1) { error ("the ENI instruction operand must be either 0 or 1"); - return const0_rtx; + return const0_rtx; } create_integer_operand (&ops[0], INTVAL (imm)); - + return nios2_expand_builtin_insn (d, 1, ops, false); } @@ -4307,7 +4307,7 @@ nios2_valid_target_attribute_rec (tree args) if (ISSPACE (*t)) continue; if (!ISDIGIT (*t)) - { + { error ("%<custom-%s=%> argument should be " "a non-negative integer", N2FPU_NAME (code)); return false; @@ -4323,7 +4323,7 @@ nios2_valid_target_attribute_rec (tree args) error ("%<custom-%s=%> is not recognized as FPU instruction", argstr + 7); return false; - } + } } else { @@ -4683,7 +4683,7 @@ static bool nios2_add_insn_narrow[] = { false, false}; /* Function to classify kinds of add instruction patterns. */ -static enum nios2_add_insn_kind +static enum nios2_add_insn_kind nios2_add_insn_classify (rtx_insn *insn ATTRIBUTE_UNUSED, rtx lhs, rtx rhs1, rtx rhs2) { @@ -5039,7 +5039,7 @@ ldstwm_operation_p (rtx op, bool load_p) { int start, i, end = XVECLEN (op, 0) - 1, last_regno = -1; unsigned int regset = 0; - rtx base_reg, offset; + rtx base_reg, offset; rtx first_elt = XVECEXP (op, 0, 0); bool inc_p = true; bool wb_p = base_reg_adjustment_p (first_elt, &base_reg, &offset); @@ -5413,7 +5413,7 @@ nios2_reorg (void) max_labelno = max_label_num (); min_labelno = get_first_label_num (); label_align = XCNEWVEC (unsigned char, max_labelno - min_labelno + 1); - + /* Iterate on inserting alignment and adjusting branch lengths until no more changes. */ while (changed) @@ -5464,7 +5464,7 @@ nios2_adjust_reg_alloc_order (void) const int cdx_reg_alloc_order[] = { /* Call-clobbered GPRs within CDX 3-bit encoded range. */ - 2, 3, 4, 5, 6, 7, + 2, 3, 4, 5, 6, 7, /* Call-saved GPRs within CDX 3-bit encoded range. */ 16, 17, /* Other call-clobbered GPRs. */ diff --git a/gcc/config/nios2/nios2.h b/gcc/config/nios2/nios2.h index bad72671..88ad166 100644 --- a/gcc/config/nios2/nios2.h +++ b/gcc/config/nios2/nios2.h @@ -1,6 +1,6 @@ /* Definitions of target machine for Altera Nios II. Copyright (C) 2012-2024 Free Software Foundation, Inc. - Contributed by Jonah Graham (jgraham@altera.com), + Contributed by Jonah Graham (jgraham@altera.com), Will Reece (wreece@altera.com), and Jeff DaSilva (jdasilva@altera.com). Contributed by Mentor Graphics, Inc. @@ -127,7 +127,7 @@ 29 r29 ea Exception Return Address 30 r30 ba Breakpoint Return Address 31 r31 ra Return Address - + 32 ctl0 status 33 ctl1 estatus STATUS saved by exception 34 ctl2 bstatus STATUS saved by break @@ -141,7 +141,7 @@ 40 First Pseudo Register In addition, r12 is used as the static chain register and r13, r14, and r15 - are clobbered by PLT code sequences. + are clobbered by PLT code sequences. The definitions for all the hard register numbers are located in nios2.md. */ diff --git a/gcc/config/nvptx/nvptx.cc b/gcc/config/nvptx/nvptx.cc index 3ac61b4..883bab6 100644 --- a/gcc/config/nvptx/nvptx.cc +++ b/gcc/config/nvptx/nvptx.cc @@ -597,7 +597,7 @@ nvptx_emit_forking (unsigned mask, bool is_call) if (mask) { rtx op = GEN_INT (mask | (is_call << GOMP_DIM_MAX)); - + /* Emit fork at all levels. This helps form SESE regions, as it creates a block with a single successor before entering a partitooned region. That is a good candidate for the end of @@ -905,10 +905,10 @@ write_return_mode (std::stringstream &s, bool for_proto, machine_mode mode) const char *ptx_type = nvptx_ptx_type_from_mode (mode, false); const char *pfx = "\t.reg"; const char *sfx = ";\n"; - + if (for_proto) pfx = "(.param", sfx = "_out) "; - + s << pfx << ptx_type << " " << reg_names[NVPTX_RETURN_REGNUM] << sfx; } @@ -931,7 +931,7 @@ write_return_type (std::stringstream &s, bool for_proto, tree type) { if (for_proto) return return_in_mem; - + /* Named return values can cause us to return a pointer as well as expect an argument for the return location. This is optimization-level specific, so no caller can make use of @@ -1057,7 +1057,7 @@ write_fn_proto_1 (std::stringstream &s, bool is_defn, for (; args; args = TREE_CHAIN (args), not_atomic_weak_arg--) { tree type = prototyped ? TREE_VALUE (args) : TREE_TYPE (args); - + if (not_atomic_weak_arg) argno = write_arg_type (s, -1, argno, type, prototyped); else @@ -1227,7 +1227,7 @@ static void nvptx_maybe_record_fnsym (rtx sym) { tree decl = SYMBOL_REF_DECL (sym); - + if (decl && TREE_CODE (decl) == FUNCTION_DECL && DECL_EXTERNAL (decl)) nvptx_record_needed_fndecl (decl); } @@ -1511,7 +1511,7 @@ nvptx_declare_function_name (FILE *file, const char *name, const_tree decl) bool return_in_mem = write_return_type (s, false, result_type); if (return_in_mem) argno = write_arg_type (s, 0, argno, ptr_type_node, true); - + /* Declare and initialize incoming arguments. */ tree args = TYPE_ARG_TYPES (fntype); bool prototyped = true; @@ -1946,7 +1946,7 @@ static rtx nvptx_gen_unpack (rtx dst0, rtx dst1, rtx src) { rtx res; - + switch (GET_MODE (src)) { case E_DImode: @@ -1967,7 +1967,7 @@ static rtx nvptx_gen_pack (rtx dst, rtx src0, rtx src1) { rtx res; - + switch (GET_MODE (dst)) { case E_DImode: @@ -2070,7 +2070,7 @@ nvptx_gen_shuffle (rtx dst, rtx src, rtx idx, nvptx_shuffle_kind kind) case E_BImode: { rtx tmp = gen_reg_rtx (SImode); - + start_sequence (); emit_insn (gen_sel_truesi (tmp, src, GEN_INT (1), const0_rtx)); emit_insn (nvptx_gen_shuffle (tmp, tmp, idx, kind)); @@ -2093,7 +2093,7 @@ nvptx_gen_shuffle (rtx dst, rtx src, rtx idx, nvptx_shuffle_kind kind) end_sequence (); } break; - + default: gcc_unreachable (); } @@ -2133,7 +2133,7 @@ enum propagate_mask /* Generate instruction(s) to spill or fill register REG to/from the worker broadcast array. PM indicates what is to be done, REP how many loop iterations will be executed (0 for not a loop). */ - + static rtx nvptx_gen_shared_bcast (rtx reg, propagate_mask pm, unsigned rep, broadcast_data_t *data, bool vector) @@ -2146,7 +2146,7 @@ nvptx_gen_shared_bcast (rtx reg, propagate_mask pm, unsigned rep, case E_BImode: { rtx tmp = gen_reg_rtx (SImode); - + start_sequence (); if (pm & PM_read) emit_insn (gen_sel_truesi (tmp, reg, GEN_INT (1), const0_rtx)); @@ -2173,7 +2173,7 @@ nvptx_gen_shared_bcast (rtx reg, propagate_mask pm, unsigned rep, if (data->offset) addr = gen_rtx_PLUS (Pmode, addr, GEN_INT (data->offset)); } - + addr = gen_rtx_MEM (mode, addr); if (pm == PM_read) res = gen_rtx_SET (addr, reg); @@ -2186,7 +2186,7 @@ nvptx_gen_shared_bcast (rtx reg, propagate_mask pm, unsigned rep, { /* We're using a ptr, increment it. */ start_sequence (); - + emit_insn (res); emit_insn (gen_adddi3 (data->ptr, data->ptr, GEN_INT (GET_MODE_SIZE (GET_MODE (reg))))); @@ -2259,7 +2259,7 @@ output_init_frag (rtx sym) init_frag.val = 0; init_frag.offset = 0; init_frag.remaining--; - + if (sym) { bool function = (SYMBOL_REF_DECL (sym) @@ -2740,7 +2740,7 @@ nvptx_output_call_insn (rtx_insn *insn, rtx result, rtx callee) fprintf (asm_out_file, "\t\tcall "); if (result != NULL_RTX) fprintf (asm_out_file, "(%s_in), ", reg_names[NVPTX_RETURN_REGNUM]); - + if (decl) { char *replaced_dots = NULL; @@ -3002,7 +3002,7 @@ nvptx_print_operand (FILE *file, rtx x, int code) { nvptx_shuffle_kind kind = (nvptx_shuffle_kind) UINTVAL (x); /* Same order as nvptx_shuffle_kind. */ - static const char *const kinds[] = + static const char *const kinds[] = {".up", ".down", ".bfly", ".idx"}; fputs (kinds[kind], file); } @@ -3497,7 +3497,7 @@ struct parallel { /* Parent parallel. */ parallel *parent; - + /* Next sibling parallel. */ parallel *next; @@ -3541,7 +3541,7 @@ parallel::parallel (parallel *parent_, unsigned mask_) forked_block = join_block = 0; forked_insn = join_insn = 0; fork_insn = joining_insn = 0; - + if (parent) { next = parent->inner; @@ -3629,7 +3629,7 @@ nvptx_split_blocks (bb_insn_map_t *map) block = elt->second; remap = block; } - + /* Split block before insn. The insn is in the new block */ edge e = split_block (block, PREV_INSN (elt->first)); @@ -3801,7 +3801,7 @@ nvptx_discover_pars (bb_insn_map_t *map) nvptx_dump_pars (par, 0); fprintf (dump_file, "\n"); } - + return par; } @@ -3832,7 +3832,7 @@ nvptx_discover_pars (bb_insn_map_t *map) the node itself and one for the output edges. Such back edges are referred to as 'Brackets'. Cycle equivalent nodes will have the same set of brackets. - + Determining bracket equivalency is done by maintaining a list of brackets in such a manner that the list length and final bracket uniquely identify the set. @@ -3842,7 +3842,7 @@ nvptx_discover_pars (bb_insn_map_t *map) algorithm. Notice it doesn't actually find the set of nodes within a particular region, just unorderd sets of nodes that are the entries and exits of SESE regions. - + After determining cycle equivalency, we need to find the minimal set of SESE regions. Do this with a DFS coloring walk of the complete graph. We're either 'looking' or 'coloring'. When @@ -3933,7 +3933,7 @@ struct bb_sese back.first ? back.first->index : 0, back.second); brackets.safe_push (bracket (back)); } - + void append (bb_sese *child); void remove (const pseudo_node_t &); @@ -4021,10 +4021,10 @@ nvptx_sese_number (int n, int p, int dir, basic_block b, if (dump_file) fprintf (dump_file, "Block %d(%d), parent (%d), orientation %+d\n", b->index, n, p, dir); - + BB_SET_SESE (b, new bb_sese (n, p, dir)); p = n; - + n += 3; list->quick_push (b); @@ -4041,7 +4041,7 @@ nvptx_sese_number (int n, int p, int dir, basic_block b, FOR_EACH_EDGE (e, ei, edges) { basic_block target = *(basic_block *)((char *)e + offset); - + if (target->flags & BB_VISITED) n = nvptx_sese_number (n, p, dir, target, list); } @@ -4119,7 +4119,7 @@ nvptx_sese_pseudo (basic_block me, bb_sese *sese, int depth, int dir, /* Non-parental ancestor node -- a backlink. */ int d = usd * t_sese->dir; int back = t_sese->node + d; - + if (hi_back > back) { hi_back = back; @@ -4154,7 +4154,7 @@ nvptx_sese_pseudo (basic_block me, bb_sese *sese, int depth, int dir, sese->push (pseudo_node_t (nullptr, 0)); } } - + /* If this node leads directly or indirectly to a no-return region of the graph, then fake a backedge to entry node. */ if (!sese->brackets.length () || !edges || !edges->length ()) @@ -4211,7 +4211,7 @@ nvptx_sese_pseudo (basic_block me, bb_sese *sese, int depth, int dir, node_child = t_sese->high; } } - + sese->push (node_child); } } @@ -4234,7 +4234,7 @@ nvptx_sese_color (auto_vec<unsigned> &color_counts, bb_pair_vec_t ®ions, gcc_assert (coloring < 0 || (sese && coloring == sese->color)); return; } - + block->flags |= BB_VISITED; if (sese) @@ -4266,7 +4266,7 @@ nvptx_sese_color (auto_vec<unsigned> &color_counts, bb_pair_vec_t ®ions, { edge e; edge_iterator ei; - + FOR_EACH_EDGE (e, ei, block->succs) nvptx_sese_color (color_counts, regions, e->dest, coloring); } @@ -4283,7 +4283,7 @@ nvptx_find_sese (auto_vec<basic_block> &blocks, bb_pair_vec_t ®ions) basic_block block; int ix; - /* First clear each BB of the whole function. */ + /* First clear each BB of the whole function. */ FOR_ALL_BB_FN (block, cfun) { block->flags &= ~BB_VISITED; @@ -4314,7 +4314,7 @@ nvptx_find_sese (auto_vec<basic_block> &blocks, bb_pair_vec_t ®ions) if (dump_file) fprintf (dump_file, "Searching graph starting at %d\n", block->index); - + /* Number the nodes reachable from block initial DFS order. */ int depth = nvptx_sese_number (2, 0, +1, block, &spanlist); @@ -4344,7 +4344,7 @@ nvptx_find_sese (auto_vec<basic_block> &blocks, bb_pair_vec_t ®ions) { unsigned count; const char *comma = ""; - + fprintf (dump_file, "Found %d cycle equivalents\n", color_counts.length ()); for (ix = 0; color_counts.iterate (ix, &count); ix++) @@ -4364,7 +4364,7 @@ nvptx_find_sese (auto_vec<basic_block> &blocks, bb_pair_vec_t ®ions) } fprintf (dump_file, "\n"); } - + /* Now we've colored every block in the subgraph. We now need to determine the minimal set of SESE regions that cover that subgraph. Do this with a DFS walk of the complete function. @@ -4386,7 +4386,7 @@ nvptx_find_sese (auto_vec<basic_block> &blocks, bb_pair_vec_t ®ions) { const char *comma = ""; int len = regions.length (); - + fprintf (dump_file, "SESE regions:"); for (ix = 0; ix != len; ix++) { @@ -4416,7 +4416,7 @@ nvptx_find_sese (auto_vec<basic_block> &blocks, bb_pair_vec_t ®ions) } fprintf (dump_file, "\n\n"); } - + for (ix = 0; blocks.iterate (ix, &block); ix++) delete BB_GET_SESE (block); } @@ -4478,7 +4478,7 @@ nvptx_propagate (bool is_call, basic_block block, rtx_insn *insn, idx = gen_reg_rtx (SImode); pred = gen_reg_rtx (BImode); label = gen_label_rtx (); - + emit_insn (gen_rtx_SET (idx, GEN_INT (fs))); /* Allow worker function to initialize anything needed. */ rtx init = fn (tmp, PM_loop_begin, fs, data, vector); @@ -4536,7 +4536,7 @@ warp_prop_gen (rtx reg, propagate_mask pm, { if (!(pm & PM_read_write)) return 0; - + return nvptx_gen_warp_bcast (reg); } @@ -4798,7 +4798,7 @@ verify_neutering_labels (basic_block to, rtx_insn *vector_label, /* Single neutering according to MASK. FROM is the incoming block and TO is the outgoing block. These may be the same block. Insert at start of FROM: - + if (tid.<axis>) goto end. and insert before ending branch of TO (if there is such an insn): @@ -5167,7 +5167,7 @@ nvptx_process_pars (parallel *par) { if (nvptx_optimize) nvptx_optimize_inner (par); - + unsigned inner_mask = par->mask; /* Do the inner parallels first. */ @@ -5233,7 +5233,7 @@ nvptx_neuter_pars (parallel *par, unsigned modes, unsigned outer) & (GOMP_DIM_MASK (GOMP_DIM_WORKER) | GOMP_DIM_MASK (GOMP_DIM_VECTOR))); unsigned skip_mask = 0, neuter_mask = 0; - + if (par->inner) nvptx_neuter_pars (par->inner, modes, outer | me); @@ -5294,7 +5294,7 @@ nvptx_neuter_pars (parallel *par, unsigned modes, unsigned outer) if (skip_mask) nvptx_skip_par (skip_mask, par); - + if (par->next) nvptx_neuter_pars (par->next, modes, outer); } @@ -5737,7 +5737,7 @@ nvptx_reorg (void) if (dump_file) df_dump (dump_file); - + /* Mark unused regs as unused. */ int max_regs = max_reg_num (); for (int i = LAST_VIRTUAL_REGISTER + 1; i < max_regs; i++) @@ -6031,7 +6031,7 @@ nvptx_expand_shuffle (tree exp, rtx target, machine_mode mode, int ignore) { if (ignore) return target; - + rtx src = expand_expr (CALL_EXPR_ARG (exp, 0), NULL_RTX, mode, EXPAND_NORMAL); if (!REG_P (src)) @@ -6041,7 +6041,7 @@ nvptx_expand_shuffle (tree exp, rtx target, machine_mode mode, int ignore) NULL_RTX, SImode, EXPAND_NORMAL); rtx op = expand_expr (CALL_EXPR_ARG (exp, 2), NULL_RTX, SImode, EXPAND_NORMAL); - + if (!REG_P (idx) && GET_CODE (idx) != CONST_INT) idx = copy_to_mode_reg (SImode, idx); @@ -6060,7 +6060,7 @@ nvptx_expand_brev (tree exp, rtx target, machine_mode mode, int ignore) { if (ignore) return target; - + rtx arg = expand_expr (CALL_EXPR_ARG (exp, 0), NULL_RTX, mode, EXPAND_NORMAL); if (!REG_P (arg)) @@ -6150,7 +6150,7 @@ nvptx_expand_cmp_swap (tree exp, rtx target, machine_mode ARG_UNUSED (m), int ARG_UNUSED (ignore)) { machine_mode mode = TYPE_MODE (TREE_TYPE (exp)); - + if (!target) target = gen_reg_rtx (mode); @@ -6167,7 +6167,7 @@ nvptx_expand_cmp_swap (tree exp, rtx target, cmp = copy_to_mode_reg (mode, cmp); if (!REG_P (src)) src = copy_to_mode_reg (mode, src); - + if (mode == SImode) pat = gen_atomic_compare_and_swapsi_1 (target, mem, cmp, src, const0_rtx); else @@ -6747,7 +6747,7 @@ nvptx_generate_vector_shuffle (location_t loc, fn = NVPTX_BUILTIN_SHUFFLELL; arg_type = long_long_unsigned_type_node; } - + tree call = nvptx_builtin_decl (fn, true); tree bits = build_int_cst (unsigned_type_node, shift); tree kind = build_int_cst (unsigned_type_node, SHUFFLE_DOWN); @@ -6784,7 +6784,7 @@ static tree nvptx_global_lock_addr () { tree v = global_lock_var; - + if (!v) { tree name = get_identifier ("__reduction_lock"); @@ -6847,7 +6847,7 @@ nvptx_lockless_update (location_t loc, gimple_stmt_iterator *gsi, gimple *init_end = gimple_seq_last (init_seq); gsi_insert_seq_before (gsi, init_seq, GSI_SAME_STMT); - + /* Split the block just after the init stmts. */ basic_block pre_bb = gsi_bb (*gsi); edge pre_edge = split_block (pre_bb, init_end); @@ -6859,7 +6859,7 @@ nvptx_lockless_update (location_t loc, gimple_stmt_iterator *gsi, tree expect_var = make_ssa_name (arg_type); tree actual_var = make_ssa_name (arg_type); tree write_var = make_ssa_name (arg_type); - + /* Build and insert the reduction calculation. */ gimple_seq red_seq = NULL; tree write_expr = fold_build1 (code, var_type, expect_var); @@ -6961,7 +6961,7 @@ nvptx_lockfull_update (location_t loc, gimple_stmt_iterator *gsi, basic_block update_bb = locked_edge->dest; lock_bb = locked_edge->src; *gsi = gsi_for_stmt (gsi_stmt (*gsi)); - + /* Create the lock loop ... */ locked_edge->flags ^= EDGE_TRUE_VALUE | EDGE_FALLTHRU; locked_edge->probability = profile_probability::even (); @@ -6993,11 +6993,11 @@ nvptx_lockfull_update (location_t loc, gimple_stmt_iterator *gsi, tree ref_in = build_simple_mem_ref (ptr); TREE_THIS_VOLATILE (ref_in) = 1; gimplify_assign (acc_in, ref_in, &red_seq); - + tree acc_out = make_ssa_name (var_type); tree update_expr = fold_build2 (op, var_type, ref_in, var); gimplify_assign (acc_out, update_expr, &red_seq); - + tree ref_out = build_simple_mem_ref (ptr); TREE_THIS_VOLATILE (ref_out) = 1; gimplify_assign (ref_out, acc_out, &red_seq); @@ -7060,7 +7060,7 @@ nvptx_goacc_reduction_setup (gcall *call, offload_attrs *oa) if (!integer_zerop (ref_to_res)) var = build_simple_mem_ref (ref_to_res); } - + if (level == GOMP_DIM_WORKER || (level == GOMP_DIM_VECTOR && oa->vector_length > PTX_WARP_SIZE)) { @@ -7097,7 +7097,7 @@ nvptx_goacc_reduction_init (gcall *call, offload_attrs *oa) tree init = omp_reduction_init_op (gimple_location (call), rcode, TREE_TYPE (var)); gimple_seq seq = NULL; - + push_gimplify_context (true); if (level == GOMP_DIM_VECTOR && oa->vector_length == PTX_WARP_SIZE) @@ -7122,7 +7122,7 @@ nvptx_goacc_reduction_init (gcall *call, offload_attrs *oa) /* Fixup flags from call_bb to init_bb. */ init_edge->flags ^= EDGE_FALLTHRU | EDGE_TRUE_VALUE; init_edge->probability = profile_probability::even (); - + /* Set the initialization stmts. */ gimple_seq init_seq = NULL; tree init_var = make_ssa_name (TREE_TYPE (var)); @@ -7134,7 +7134,7 @@ nvptx_goacc_reduction_init (gcall *call, offload_attrs *oa) gsi_prev (&gsi); edge inited_edge = split_block (gsi_bb (gsi), gsi_stmt (gsi)); basic_block dst_bb = inited_edge->dest; - + /* Create false edge from call_bb to dst_bb. */ edge nop_edge = make_edge (call_bb, dst_bb, EDGE_FALSE_VALUE); nop_edge->probability = profile_probability::even (); @@ -7249,7 +7249,7 @@ nvptx_goacc_reduction_teardown (gcall *call, offload_attrs *oa) tree var = gimple_call_arg (call, 2); int level = TREE_INT_CST_LOW (gimple_call_arg (call, 3)); gimple_seq seq = NULL; - + push_gimplify_context (true); if (level == GOMP_DIM_WORKER || (level == GOMP_DIM_VECTOR && oa->vector_length > PTX_WARP_SIZE)) @@ -7276,7 +7276,7 @@ nvptx_goacc_reduction_teardown (gcall *call, offload_attrs *oa) if (lhs) gimplify_assign (lhs, var, &seq); - + pop_gimplify_context (NULL); gsi_replace_with_seq (&gsi, seq, true); diff --git a/gcc/config/openbsd-stdint.h b/gcc/config/openbsd-stdint.h index a6da1da..00ca36c 100644 --- a/gcc/config/openbsd-stdint.h +++ b/gcc/config/openbsd-stdint.h @@ -1,5 +1,5 @@ #define SIG_ATOMIC_TYPE "int" - + #define INT8_TYPE "signed char" #define INT16_TYPE "short int" #define INT32_TYPE "int" @@ -8,7 +8,7 @@ #define UINT16_TYPE "short unsigned int" #define UINT32_TYPE "unsigned int" #define UINT64_TYPE "long long unsigned int" - + #define INT_LEAST8_TYPE "signed char" #define INT_LEAST16_TYPE "short int" #define INT_LEAST32_TYPE "int" @@ -17,7 +17,7 @@ #define UINT_LEAST16_TYPE "short unsigned int" #define UINT_LEAST32_TYPE "unsigned int" #define UINT_LEAST64_TYPE "long long unsigned int" - + #define INT_FAST8_TYPE "int" #define INT_FAST16_TYPE "int" #define INT_FAST32_TYPE "int" @@ -29,6 +29,6 @@ #define INTMAX_TYPE "long long int" #define UINTMAX_TYPE "long long unsigned int" - + #define INTPTR_TYPE "long int" #define UINTPTR_TYPE "long unsigned int" diff --git a/gcc/config/openbsd.h b/gcc/config/openbsd.h index 3493df9..6522527 100644 --- a/gcc/config/openbsd.h +++ b/gcc/config/openbsd.h @@ -17,27 +17,27 @@ You should have received a copy of the GNU General Public License along with GCC; see the file COPYING3. If not see <http://www.gnu.org/licenses/>. */ -/* Common OpenBSD configuration. +/* Common OpenBSD configuration. All OpenBSD architectures include this file, which is intended as - a repository for common defines. + a repository for common defines. Some defines are common to all architectures, a few of them are triggered by OBSD_* guards, so that we won't override architecture defaults by mistakes. - OBSD_HAS_CORRECT_SPECS: + OBSD_HAS_CORRECT_SPECS: another mechanism provides correct specs already. - OBSD_NO_DYNAMIC_LIBRARIES: + OBSD_NO_DYNAMIC_LIBRARIES: no implementation of dynamic libraries. - OBSD_OLD_GAS: + OBSD_OLD_GAS: older flavor of gas which needs help for PIC. OBSD_HAS_DECLARE_FUNCTION_NAME, OBSD_HAS_DECLARE_FUNCTION_SIZE, - OBSD_HAS_DECLARE_OBJECT: + OBSD_HAS_DECLARE_OBJECT: PIC support, FUNCTION_NAME/FUNCTION_SIZE are independent, whereas the corresponding logic for OBJECTS is necessarily coupled. There are also a few `default' defines such as ASM_WEAKEN_LABEL, - intended as common ground for arch that don't provide + intended as common ground for arch that don't provide anything suitable. */ /* OPENBSD_NATIVE is defined only when gcc is configured as part of @@ -104,7 +104,7 @@ while (0) /* CPP_SPEC appropriate for OpenBSD. We deal with -posix and -pthread. XXX the way threads are handled currently is not very satisfying, - since all code must be compiled with -pthread to work. + since all code must be compiled with -pthread to work. This two-stage defines makes it easy to pick that for targets that have subspecs. */ #ifdef CPP_CPU_SPEC @@ -122,8 +122,8 @@ while (0) #define CPP_SPEC OBSD_CPP_SPEC #ifdef OBSD_OLD_GAS -/* ASM_SPEC appropriate for OpenBSD. For some architectures, OpenBSD - still uses a special flavor of gas that needs to be told when generating +/* ASM_SPEC appropriate for OpenBSD. For some architectures, OpenBSD + still uses a special flavor of gas that needs to be told when generating pic code. */ #undef ASM_SPEC #define ASM_SPEC "%{" FPIE1_OR_FPIC1_SPEC ":-k} %{" FPIE2_OR_FPIC2_SPEC ":-k -K}" @@ -152,7 +152,7 @@ while (0) /* - we use . - _func instead of a local label, - - we put extra spaces in expressions such as + - we put extra spaces in expressions such as .type _func , @function This is more readable for a human being and confuses c++filt less. */ @@ -161,11 +161,11 @@ while (0) /* Define the strings used for the .type and .size directives. These strings generally do not vary from one system running OpenBSD to another, but if a given system needs to use different pseudo-op - names for these, they may be overridden in the arch specific file. */ + names for these, they may be overridden in the arch specific file. */ /* OpenBSD assembler is hacked to have .type & .size support even in a.out - format object files. Functions size are supported but not activated - yet (look for GRACE_PERIOD_EXPIRED in gas/config/obj-aout.c). + format object files. Functions size are supported but not activated + yet (look for GRACE_PERIOD_EXPIRED in gas/config/obj-aout.c). SET_ASM_OP is needed for attribute alias to work. */ #undef TYPE_ASM_OP @@ -191,12 +191,12 @@ while (0) /* These macros generate the special .type and .size directives which are used to set the corresponding fields of the linker symbol table - entries under OpenBSD. These macros also have to output the starting + entries under OpenBSD. These macros also have to output the starting labels for the relevant functions/objects. */ #ifndef OBSD_HAS_DECLARE_FUNCTION_NAME /* Extra assembler code needed to declare a function properly. - Some assemblers may also need to also have something extra said + Some assemblers may also need to also have something extra said about the function's return value. We allow for that here. */ #undef ASM_DECLARE_FUNCTION_NAME #define ASM_DECLARE_FUNCTION_NAME(FILE, NAME, DECL) \ @@ -238,7 +238,7 @@ while (0) /* Output the size directive for a decl in rest_of_decl_compilation in the case where we did not do so before the initializer. Once we find the error_mark_node, we know that the value of - size_directive_output was set by ASM_DECLARE_OBJECT_NAME + size_directive_output was set by ASM_DECLARE_OBJECT_NAME when it was run for the same decl. */ #undef ASM_FINISH_DECLARE_OBJECT #define ASM_FINISH_DECLARE_OBJECT(FILE, DECL, TOP_LEVEL, AT_END) \ @@ -260,11 +260,11 @@ do { \ /* Those are `generic' ways to weaken/globalize a label. We shouldn't need to override a processor specific definition. Hence, #ifndef ASM_* - In case overriding turns out to be needed, one can always #undef ASM_* + In case overriding turns out to be needed, one can always #undef ASM_* before including this file. */ /* Tell the assembler that a symbol is weak. */ -/* Note: netbsd arm32 assembler needs a .globl here. An override may +/* Note: netbsd arm32 assembler needs a .globl here. An override may be needed when/if we go for arm32 support. */ #ifndef ASM_WEAKEN_LABEL #define ASM_WEAKEN_LABEL(FILE,NAME) \ diff --git a/gcc/config/pa/pa-64.h b/gcc/config/pa/pa-64.h index 3fae3f8..c5e8d32 100644 --- a/gcc/config/pa/pa-64.h +++ b/gcc/config/pa/pa-64.h @@ -35,7 +35,7 @@ along with GCC; see the file COPYING3. If not see size_t 8 bytes ptrdiff_t 8 bytes wchar 4 bytes - + Make GCC agree with types.h. */ #undef SIZE_TYPE #define SIZE_TYPE "long unsigned int" @@ -91,7 +91,7 @@ along with GCC; see the file COPYING3. If not see the RTL to avoid scheduling related problems. For example, the store and load could be separated by a call to a pure or const function which has no frame and this function might also use SP-16. - + On the 64-bit port, I couldn't get SECONDARY_MEMORY_NEEDED to work with LRA, so I modified the move patterns to use SP-40. The HP compiler also uses this slot in the frame marker for moving data diff --git a/gcc/config/pa/pa.cc b/gcc/config/pa/pa.cc index 62f8764..94ee7db 100644 --- a/gcc/config/pa/pa.cc +++ b/gcc/config/pa/pa.cc @@ -58,7 +58,7 @@ along with GCC; see the file COPYING3. If not see /* This file should be included last. */ #include "target-def.h" -/* Return nonzero if there is a bypass for the output of +/* Return nonzero if there is a bypass for the output of OUT_INSN and the fp store IN_INSN. */ int pa_fpstore_bypass_p (rtx_insn *out_insn, rtx_insn *in_insn) @@ -83,7 +83,7 @@ pa_fpstore_bypass_p (rtx_insn *out_insn, rtx_insn *in_insn) return (GET_MODE_SIZE (store_mode) == GET_MODE_SIZE (other_mode)); } - + #ifndef DO_FRAME_NOTES #ifdef INCOMING_RETURN_ADDR_RTX @@ -1053,7 +1053,7 @@ legitimize_pic_address (rtx orig, machine_mode mode, rtx reg) gcc_assert (reg); gcc_assert (GET_CODE (XEXP (orig, 0)) == PLUS); - + base = legitimize_pic_address (XEXP (XEXP (orig, 0), 0), Pmode, reg); orig = legitimize_pic_address (XEXP (XEXP (orig, 0), 1), Pmode, base == reg ? 0 : reg); @@ -1103,7 +1103,7 @@ legitimize_tls_address (rtx addr) if (GET_CODE (addr) != SYMBOL_REF) return addr; - switch (SYMBOL_REF_TLS_MODEL (addr)) + switch (SYMBOL_REF_TLS_MODEL (addr)) { case TLS_MODEL_GLOBAL_DYNAMIC: tmp = gen_reg_rtx (Pmode); @@ -1126,7 +1126,7 @@ legitimize_tls_address (rtx addr) insn = get_insns (); end_sequence (); t2 = gen_reg_rtx (Pmode); - emit_libcall_block (insn, t2, t1, + emit_libcall_block (insn, t2, t1, gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx), UNSPEC_TLSLDBASE)); emit_insn (gen_tld_offset_load (ret, addr, t2)); @@ -2227,7 +2227,7 @@ pa_emit_move_sequence (rtx *operands, machine_mode mode, rtx scratch_reg) && !HARD_REGISTER_P (operand0)) copy_reg_pointer (operand0, operand1); } - + /* When MEMs are broken out, the REG_POINTER flag doesn't get set. In some cases, we can set the REG_POINTER flag from the declaration for the MEM. */ @@ -2870,7 +2870,7 @@ pa_output_move_double (rtx *operands) && GET_CODE (operands[0]) == REG); gcc_assert (!reg_overlap_mentioned_p (high_reg, addr)); - + /* No overlap between high target register and address register. (We do this in a non-obvious way to save a register file writeback) */ @@ -2885,7 +2885,7 @@ pa_output_move_double (rtx *operands) operands[0] = XEXP (addr, 0); gcc_assert (GET_CODE (operands[1]) == REG && GET_CODE (operands[0]) == REG); - + gcc_assert (!reg_overlap_mentioned_p (high_reg, addr)); /* No overlap between high target register and address register. (We do this in a non-obvious way to save a @@ -3106,15 +3106,15 @@ pa_output_fp_move_double (rtx *operands) else { rtx xoperands[2]; - + gcc_assert (operands[1] == CONST0_RTX (GET_MODE (operands[0]))); - + /* This is a pain. You have to be prepared to deal with an arbitrary address here including pre/post increment/decrement. so avoid this in the MD. */ gcc_assert (GET_CODE (operands[0]) == REG); - + xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1); xoperands[0] = operands[0]; output_asm_insn ("copy %%r0,%0\n\tcopy %%r0,%1", xoperands); @@ -4083,7 +4083,7 @@ pa_compute_frame_size (poly_int64 size, int *fregs_live) first slot is only used when the frame pointer is needed. */ if (size || frame_pointer_needed) size += pa_starting_frame_offset (); - + /* If the current function calls __builtin_eh_return, then we need to allocate stack space for registers that will hold data for the exception handler. */ @@ -4423,7 +4423,7 @@ pa_expand_prologue (void) to do for functions which make no calls and allocate no frame? Do we need to allocate a frame, or can we just omit the save? For now we'll just omit the save. - + We don't want a note on this insn as the frame marker can move if there is a dynamic stack allocation. */ if (flag_pic && actual_fsize != 0 && !TARGET_64BIT) @@ -5234,7 +5234,7 @@ pa_adjust_cost (rtx_insn *insn, int dep_type, rtx_insn *dep_insn, int cost, /* A fpload can't be issued until one cycle before a preceding arithmetic operation has finished if the target of the fpload is the destination of the - arithmetic operation. + arithmetic operation. Exception: For PA7100LC, PA7200 and PA7300, the cost is 3 cycles, unless they bundle together. We also @@ -5873,7 +5873,7 @@ pa_output_global_address (FILE *file, rtx x, int round_constant) default: gcc_unreachable (); } - + if (!read_only_operand (base, VOIDmode) && !flag_pic) fputs ("-$global$", file); if (offset) @@ -5933,7 +5933,7 @@ pa_file_start_mcount (const char *aswhat) if (profile_flag) fprintf (asm_out_file, "\t.IMPORT _mcount,%s\n", aswhat); } - + static void pa_elf_file_start (void) { @@ -7120,7 +7120,7 @@ const char * pa_output_lbranch (rtx dest, rtx_insn *insn, int xdelay) { rtx xoperands[4]; - + xoperands[0] = dest; /* First, free up the delay slot. */ @@ -7641,7 +7641,7 @@ pa_output_dbra (rtx *operands, rtx_insn *insn, int which_alternative) } else return "addib,%C2 %1,%0,%3"; - + case 8: /* Handle weird backwards branch with a fulled delay slot which is nullified. */ @@ -7691,7 +7691,7 @@ pa_output_dbra (rtx *operands, rtx_insn *insn, int which_alternative) return pa_output_lbranch (operands[3], insn, xdelay); } - + } /* Deal with gross reload from FP register case. */ else if (which_alternative == 1) @@ -8487,7 +8487,7 @@ pa_output_indirect_call (rtx_insn *insn, rtx call_dest) pa_output_arg_descriptor (insn); if (TARGET_PA_20) return "bve,l,n (%%r22),%%r2\n\tnop"; - return "ble 0(%%sr4,%%r22)\n\tcopy %%r31,%%r2"; + return "ble 0(%%sr4,%%r22)\n\tcopy %%r31,%%r2"; } if (TARGET_PORTABLE_RUNTIME) @@ -8499,7 +8499,7 @@ pa_output_indirect_call (rtx_insn *insn, rtx call_dest) } /* Now the normal case -- we can reach $$dyncall directly or - we're sure that we can get there via a long-branch stub. + we're sure that we can get there via a long-branch stub. No need to check target flags as the length uniquely identifies the remaining cases. */ @@ -9213,7 +9213,7 @@ pa_asm_out_destructor (rtx symbol, int priority) The ASM_OUTPUT_ALIGNED_BSS macro needs to be defined to call this function on the SOM port to prevent uninitialized global data from being placed in the data section. */ - + void pa_asm_output_aligned_bss (FILE *stream, const char *name, @@ -9379,7 +9379,7 @@ forward_branch_p (rtx_insn *insn) gcc_assert (lab != NULL_RTX); if (INSN_ADDRESSES_SET_P ()) - return INSN_ADDRESSES (INSN_UID (lab)) > INSN_ADDRESSES (INSN_UID (insn)); + return INSN_ADDRESSES (INSN_UID (lab)) > INSN_ADDRESSES (INSN_UID (insn)); while (insn) { @@ -9814,8 +9814,8 @@ pa_promote_function_mode (const_tree type ATTRIBUTE_UNUSED, to match the HP Compiler ABI. */ static rtx -pa_function_value (const_tree valtype, - const_tree func ATTRIBUTE_UNUSED, +pa_function_value (const_tree valtype, + const_tree func ATTRIBUTE_UNUSED, bool outgoing ATTRIBUTE_UNUSED) { machine_mode valmode; @@ -10338,7 +10338,7 @@ pa_select_section (tree exp, int reloc, and the function is in a COMDAT group, place the plabel reference in the .data.rel.ro.local section. The linker ignores references to symbols in discarded sections from this section. */ - + static section * pa_elf_select_rtx_section (machine_mode mode, rtx x, unsigned HOST_WIDE_INT align) @@ -10489,7 +10489,7 @@ pa_can_change_mode_class (machine_mode from, machine_mode to, if (COMPLEX_MODE_P (from) || VECTOR_MODE_P (from) || COMPLEX_MODE_P (to) || VECTOR_MODE_P (to)) return false; - + /* There is no way to load QImode or HImode values directly from memory to a FP register. SImode loads to the FP registers are not zero extended. On the 64-bit target, this conflicts with the definition @@ -10510,7 +10510,7 @@ pa_can_change_mode_class (machine_mode from, machine_mode to, } /* Implement TARGET_MODES_TIEABLE_P. - + We should return FALSE for QImode and HImode because these modes are not ok in the floating-point registers. However, this prevents tieing these modes to SImode and DImode in the general registers. @@ -10933,7 +10933,7 @@ pa_section_type_flags (tree decl, const char *name, int reloc) must provide patterns for doing indexed integer stores, or the move expanders must force the address of an indexed store to a register. We have adopted the latter approach. - + Another function of pa_legitimate_address_p is to ensure that the base register is a valid pointer for indexed instructions. On targets that have non-equivalent space registers, we have to @@ -11260,7 +11260,7 @@ pa_function_arg_size (machine_mode mode, const_tree type) { HOST_WIDE_INT size; - size = mode != BLKmode ? GET_MODE_SIZE (mode) : int_size_in_bytes (type); + size = mode != BLKmode ? GET_MODE_SIZE (mode) : int_size_in_bytes (type); /* The 64-bit runtime does not restrict the size of stack frames, but the gcc calling conventions limit argument sizes to 1G. Our diff --git a/gcc/config/pa/pa.h b/gcc/config/pa/pa.h index 6fcc2fa..fa6d05e 100644 --- a/gcc/config/pa/pa.h +++ b/gcc/config/pa/pa.h @@ -226,7 +226,7 @@ typedef struct GTY(()) machine_function } machine_function; /* Define this macro if it is advisable to hold scalars in registers - in a wider mode than that declared by the program. In such cases, + in a wider mode than that declared by the program. In such cases, the value is constrained to be within the bounds of the declared type, but kept valid in the wider mode. The signedness of the extension may differ from that of the type. */ @@ -260,7 +260,7 @@ typedef struct GTY(()) machine_function This needs to be 8 when TARGET_64BIT is true to allow building various TImode routines in libgcc. However, we also need the DImode DIVMOD routines because they are not currently implemented in pa.md. - + The HP runtime specification doesn't provide the alignment requirements and calling conventions for TImode variables. */ #ifdef IN_LIBGCC2 @@ -567,13 +567,13 @@ extern rtx hppa_pic_save_rtx (void); of arguments scanned so far (including the invisible argument, if any, which holds the structure-value-address). Thus, 4 or more means all following args should go on the stack. - + The INCOMING field tracks whether this is an "incoming" or "outgoing" argument. - + The INDIRECT field indicates whether this is an indirect call or not. - + The NARGS_PROTOTYPE field indicates that an argument does not have a prototype when it less than or equal to 0. */ @@ -715,7 +715,7 @@ extern int may_call_alloca; #define MIN_CACHELINE_SIZE 32 -/* Addressing modes, and classification of registers for them. +/* Addressing modes, and classification of registers for them. Using autoincrement addressing modes on PA8000 class machines is not profitable. */ @@ -973,7 +973,7 @@ do { \ /* Higher than the default as we prefer to use simple move insns (better scheduling and delay slot filling) and because our - built-in block move is really a 2X unrolled loop. + built-in block move is really a 2X unrolled loop. Believe it or not, this has to be big enough to allow for copying all arguments passed in registers to avoid infinite recursion during argument @@ -1166,7 +1166,7 @@ do { \ #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \ fprintf (FILE, "\t.word L$%d\n", VALUE) -/* This is how to output an element of a case-vector that is relative. +/* This is how to output an element of a case-vector that is relative. Since we always place jump tables in the text section, the difference is absolute and requires no relocation. */ @@ -1200,7 +1200,7 @@ do { \ #define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \ pa_asm_output_aligned_bss (FILE, NAME, SIZE, ALIGN) - + /* This says how to output an assembler line to define a global common symbol with size SIZE (in bytes) and alignment ALIGN (in bits). */ @@ -1214,7 +1214,7 @@ do { \ #define ASM_OUTPUT_ALIGNED_LOCAL(FILE, NAME, SIZE, ALIGN) \ pa_asm_output_aligned_local (FILE, NAME, SIZE, ALIGN) - + /* All HP assemblers use "!" to separate logical lines. */ #define IS_ASM_LOGICAL_LINE_SEPARATOR(C, STR) ((C) == '!') @@ -1298,7 +1298,7 @@ do { \ instructions for non-PIC and PIC, respectively. Import stubs are seven and five instructions for HP-UX and ELF targets, respectively. The default stub group size for ELF targets is 217856 bytes. - FIXME: We need an option to set the maximum offset. */ + FIXME: We need an option to set the maximum offset. */ #define MAX_PCREL17F_OFFSET (TARGET_HPUX ? 198164 : 217856) #define NEED_INDICATE_EXEC_STACK 0 diff --git a/gcc/config/pa/pa32-regs.h b/gcc/config/pa/pa32-regs.h index 6485ab2..3467e03 100644 --- a/gcc/config/pa/pa32-regs.h +++ b/gcc/config/pa/pa32-regs.h @@ -318,7 +318,7 @@ enum reg_class { NO_REGS, R1_REGS, GENERAL_REGS, FPUPPER_REGS, FP_REGS, /* 1 if N is a possible register number for function argument passing. */ #define FUNCTION_ARG_REGNO_P(N) \ - (((N) >= 23 && (N) <= 26) || (! TARGET_SOFT_FLOAT && (N) >= 32 && (N) <= 39)) + (((N) >= 23 && (N) <= 26) || (! TARGET_SOFT_FLOAT && (N) >= 32 && (N) <= 39)) /* How to refer to registers in assembler output. This sequence is indexed by compiler's hard-register-number (see above). */ diff --git a/gcc/config/pa/som.h b/gcc/config/pa/som.h index 1039a6a..39fdefd 100644 --- a/gcc/config/pa/som.h +++ b/gcc/config/pa/som.h @@ -25,7 +25,7 @@ along with GCC; see the file COPYING3. If not see linked executables and shared libraries. */ #define LDD_SUFFIX "chatr" /* Look for lines like "dynamic /usr/lib/X11R5/libX11.sl" - or "static /usr/lib/X11R5/libX11.sl". + or "static /usr/lib/X11R5/libX11.sl". HPUX 10.20 also has lines like "static branch prediction ..." so we filter that out explicitly. @@ -357,7 +357,7 @@ do { \ #define GTHREAD_USE_WEAK 0 /* Shared library suffix. Collect2 strips the version string after - this suffix when generating constructor/destructor names. */ + this suffix when generating constructor/destructor names. */ #define SHLIB_SUFFIX ".sl" /* We don't have named sections. */ diff --git a/gcc/config/pdp11/pdp11.cc b/gcc/config/pdp11/pdp11.cc index 084af21..600a4f3 100644 --- a/gcc/config/pdp11/pdp11.cc +++ b/gcc/config/pdp11/pdp11.cc @@ -50,7 +50,7 @@ along with GCC; see the file COPYING3. If not see /* This file should be included last. */ #include "target-def.h" -/* this is the current value returned by the macro FIRST_PARM_OFFSET +/* this is the current value returned by the macro FIRST_PARM_OFFSET defined in tm.h */ int current_first_parm_offset; @@ -220,7 +220,7 @@ static bool pdp11_scalar_mode_supported_p (scalar_mode); #undef TARGET_SECONDARY_RELOAD #define TARGET_SECONDARY_RELOAD pdp11_secondary_reload -#undef TARGET_REGISTER_MOVE_COST +#undef TARGET_REGISTER_MOVE_COST #define TARGET_REGISTER_MOVE_COST pdp11_register_move_cost #undef TARGET_PREFERRED_RELOAD_CLASS @@ -327,7 +327,7 @@ pdp11_saved_regno (unsigned regno) alloca storage if any. */ void pdp11_expand_prologue (void) -{ +{ HOST_WIDE_INT fsize = get_frame_size (); unsigned regno; rtx x, via_ac = NULL; @@ -339,7 +339,7 @@ pdp11_expand_prologue (void) emit_insn (gen_setd ()); emit_insn (gen_seti ()); } - + /* Save CPU registers. */ for (regno = R0_REGNUM; regno <= PC_REGNUM; regno++) if (pdp11_saved_regno (regno)) @@ -350,7 +350,7 @@ pdp11_expand_prologue (void) } /* Save FPU registers. */ - for (regno = AC0_REGNUM; regno <= AC3_REGNUM; regno++) + for (regno = AC0_REGNUM; regno <= AC3_REGNUM; regno++) if (pdp11_saved_regno (regno)) { x = gen_rtx_PRE_DEC (Pmode, stack_pointer_rtx); @@ -388,7 +388,7 @@ pdp11_expand_prologue (void) void pdp11_expand_epilogue (void) -{ +{ HOST_WIDE_INT fsize = get_frame_size (); unsigned regno; rtx x, reg, via_ac = NULL; @@ -476,13 +476,13 @@ pdp11_expand_operands (rtx *operands, rtx exops[][2], bool sameoff = false; enum { REGOP, OFFSOP, MEMOP, PUSHOP, POPOP, CNSTOP, RNDOP } optype; long sval[2]; - + /* If either piece order is accepted and one is pre-decrement while the other is post-increment, set order to be high order word first. That will force the pre-decrement to be turned into a pointer adjust, then offset addressing. Otherwise, if either operand uses pre-decrement, that means - the order is low order first. + the order is low order first. Otherwise, if both operands are registers and destination is higher than source and they overlap, do low order word (highest register number) first. */ @@ -512,7 +512,7 @@ pdp11_expand_operands (rtx *operands, rtx exops[][2], the push increases the offset to each source word. In theory there are other cases like this, for example dest == pop, but those don't occur in real life so ignore those. */ - if (GET_CODE (operands[0]) == MEM + if (GET_CODE (operands[0]) == MEM && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC && REGNO (XEXP (XEXP (operands[0], 0), 0)) == STACK_POINTER_REGNUM && reg_overlap_mentioned_p (stack_pointer_rtx, operands[1])) @@ -529,7 +529,7 @@ pdp11_expand_operands (rtx *operands, rtx exops[][2], else gcc_assert (useorder == either || useorder == order); - + for (op = 0; op < opcount; op++) { /* First classify the operand. */ @@ -553,10 +553,10 @@ pdp11_expand_operands (rtx *operands, rtx exops[][2], supposed to allow to happen. Return failure for such cases. */ if (optype == RNDOP) return false; - + if (action != NULL) action[op] = no_action; - + /* If the operand uses pre-decrement addressing but we want to get the parts high order first, decrement the former register explicitly @@ -569,7 +569,7 @@ pdp11_expand_operands (rtx *operands, rtx exops[][2], XEXP (XEXP (operands[op], 0), 0)); optype = OFFSOP; } - /* If the operand uses post-increment mode but we want + /* If the operand uses post-increment mode but we want to get the parts low order first, change the operand into ordinary indexing and remember to increment the register explicitly when we're done. */ @@ -588,7 +588,7 @@ pdp11_expand_operands (rtx *operands, rtx exops[][2], REAL_VALUE_TO_TARGET_DOUBLE (*CONST_DOUBLE_REAL_VALUE (operands[op]), sval); } - + for (i = 0; i < words; i++) { if (order == big) @@ -633,18 +633,18 @@ output_move_multiple (rtx *operands) rtx inops[2]; rtx exops[4][2]; rtx adjops[2]; - + pdp11_action action[2]; int i, words; - + words = GET_MODE_BITSIZE (GET_MODE (operands[0])) / 16; adjops[1] = gen_rtx_CONST_INT (HImode, words * 2); inops[0] = operands[0]; inops[1] = operands[1]; - + pdp11_expand_operands (inops, exops, 2, words, action, either); - + /* Check for explicit decrement before. */ if (action[0] == dec_before) { @@ -686,7 +686,7 @@ pdp11_gen_int_label (char *label, const char *prefix, int num) else sprintf (label, "*%s_%u", prefix, num); } - + /* Output an ascii string. */ void output_ascii (FILE *file, const char *p, int size) @@ -694,7 +694,7 @@ output_ascii (FILE *file, const char *p, int size) int i, c; const char *pseudo = "\t.ascii\t"; bool delim = false; - + if (TARGET_DEC_ASM) { if (p[size - 1] == '\0') @@ -769,7 +769,7 @@ pdp11_asm_output_var (FILE *file, const char *name, int size, assemble_name (file, name); fputs (":", file); ASM_OUTPUT_SKIP (file, size); - } + } } /* Special format operators handled here: @@ -782,7 +782,7 @@ static void pdp11_asm_print_operand (FILE *file, rtx x, int code) { long sval[2]; - + if (code == '#') { if (TARGET_DEC_ASM) @@ -955,7 +955,7 @@ pdp11_lra_p (void) /* Register to register moves are cheap if both are general registers. */ -static int +static int pdp11_register_move_cost (machine_mode mode ATTRIBUTE_UNUSED, reg_class_t c1, reg_class_t c2) { @@ -979,7 +979,7 @@ pdp11_rtx_costs (rtx x, machine_mode mode, int outer_code, const int asize = (mode == QImode) ? 2 : GET_MODE_SIZE (mode); rtx src, dest; const char *fmt; - + switch (code) { case CONST_INT: @@ -1026,7 +1026,7 @@ pdp11_rtx_costs (rtx x, machine_mode mode, int outer_code, if (GET_RTX_LENGTH (code) > 1) src = XEXP (x, 1); dest = XEXP (x, 0); - + /* If optimizing for size, claim everything costs 2 per word, plus whatever the operands require. */ if (!speed) @@ -1070,7 +1070,7 @@ pdp11_rtx_costs (rtx x, machine_mode mode, int outer_code, case DIV: *total = 10 * asize * asize; break; - + case MOD: /* Fake value because it's accounted for under DIV, since we use a divmod pattern. */ @@ -1085,14 +1085,14 @@ pdp11_rtx_costs (rtx x, machine_mode mode, int outer_code, case of a one bit shift. */ *total = asize; break; - + default: *total = asize; break; } } } - + /* Now see if we're looking at a SET. If yes, then look at the source to see if this is a move or an arithmetic operation, and continue accordingly to handle the operands. */ @@ -1142,7 +1142,7 @@ pdp11_addr_cost (rtx addr, machine_mode mode, addr_space_t as ATTRIBUTE_UNUSED, bool speed) { int cost = 0; - + if (GET_CODE (addr) != REG) { if (!simple_memory_operand (addr, mode)) @@ -1184,7 +1184,7 @@ pdp11_insn_cost (rtx_insn *insn, bool speed) the actual operation plus a clobber, or the implicit compare plus the actual operation. Find the actual operation. */ pat = PATTERN (insn); - + if (GET_CODE (pat) == PARALLEL) { set = XVECEXP (pat, 0, 0); @@ -1199,7 +1199,7 @@ pdp11_insn_cost (rtx_insn *insn, bool speed) if (GET_CODE (set) != SET) return 0; } - + /* Pick up the SET source and destination RTL. */ dest = XEXP (set, 0); src = XEXP (set, 1); @@ -1242,7 +1242,7 @@ pdp11_insn_cost (rtx_insn *insn, bool speed) src2 = XEXP (src, 1); base_cost += pdp11_addr_cost (src2, mode, ADDR_SPACE_GENERIC, speed); } - + return base_cost; } @@ -1354,7 +1354,7 @@ simple_memory_operand(rtx op, machine_mode mode ATTRIBUTE_UNUSED) /* Decode the address now. */ indirection: - + addr = XEXP (op, 0); switch (GET_CODE (addr)) @@ -1362,27 +1362,27 @@ simple_memory_operand(rtx op, machine_mode mode ATTRIBUTE_UNUSED) case REG: /* (R0) - no extra cost */ return 1; - + case PRE_DEC: case POST_INC: case PRE_MODIFY: case POST_MODIFY: /* -(R0), (R0)+ - cheap! */ return 1; - + case MEM: - /* cheap - is encoded in addressing mode info! + /* cheap - is encoded in addressing mode info! -- except for @(R0), which has to be @0(R0) !!! */ if (GET_CODE (XEXP (addr, 0)) == REG) return 0; - + op=addr; goto indirection; - + case CONST_INT: - case LABEL_REF: + case LABEL_REF: case CONST: case SYMBOL_REF: /* @#address - extra cost */ @@ -1395,7 +1395,7 @@ simple_memory_operand(rtx op, machine_mode mode ATTRIBUTE_UNUSED) default: break; } - + return FALSE; } @@ -1412,7 +1412,7 @@ no_side_effect_operand(rtx op, machine_mode mode ATTRIBUTE_UNUSED) /* Decode the address now. */ indirection: - + addr = XEXP (op, 0); switch (GET_CODE (addr)) @@ -1420,26 +1420,26 @@ no_side_effect_operand(rtx op, machine_mode mode ATTRIBUTE_UNUSED) case REG: /* (R0) - no extra cost */ return 1; - + case PRE_DEC: case POST_INC: case PRE_MODIFY: case POST_MODIFY: return 0; - + case MEM: - /* cheap - is encoded in addressing mode info! + /* cheap - is encoded in addressing mode info! -- except for @(R0), which has to be @0(R0) !!! */ if (GET_CODE (XEXP (addr, 0)) == REG) return 0; - + op=addr; goto indirection; - + case CONST_INT: - case LABEL_REF: + case LABEL_REF: case CONST: case SYMBOL_REF: /* @#address - extra cost */ @@ -1452,7 +1452,7 @@ no_side_effect_operand(rtx op, machine_mode mode ATTRIBUTE_UNUSED) default: break; } - + return FALSE; } @@ -1514,7 +1514,7 @@ pdp11_can_change_mode_class (machine_mode from, So we disallow all mode changes involving FPRs. */ if (FLOAT_MODE_P (from) != FLOAT_MODE_P (to)) return false; - + return !reg_classes_intersect_p (FPU_REGS, rclass); } @@ -1530,7 +1530,7 @@ pdp11_guard_type (void) Given an rtx X being reloaded into a reg required to be in class CLASS, return the class of reg to actually use. In general this is just CLASS; but on some machines - in some cases it is preferable to use a more restrictive class. + in some cases it is preferable to use a more restrictive class. loading is easier into LOAD_FPU_REGS than FPU_REGS! */ @@ -1554,7 +1554,7 @@ pdp11_preferred_reload_class (rtx x, reg_class_t rclass) Given an rtx X being reloaded into a reg required to be in class CLASS, return the class of reg to actually use. In general this is just CLASS; but on some machines - in some cases it is preferable to use a more restrictive class. + in some cases it is preferable to use a more restrictive class. loading is easier into LOAD_FPU_REGS than FPU_REGS! */ @@ -1576,10 +1576,10 @@ pdp11_preferred_output_reload_class (rtx x, reg_class_t rclass) /* TARGET_SECONDARY_RELOAD. - FPU registers AC4 and AC5 (class NO_LOAD_FPU_REGS) require an + FPU registers AC4 and AC5 (class NO_LOAD_FPU_REGS) require an intermediate register (AC0-AC3: LOAD_FPU_REGS). Everything else can be loaded/stored directly. */ -static reg_class_t +static reg_class_t pdp11_secondary_reload (bool in_p ATTRIBUTE_UNUSED, rtx x, reg_class_t reload_class, @@ -1589,7 +1589,7 @@ pdp11_secondary_reload (bool in_p ATTRIBUTE_UNUSED, if (reload_class != NO_LOAD_FPU_REGS || GET_CODE (x) != REG || REGNO_REG_CLASS (REGNO (x)) == LOAD_FPU_REGS) return NO_REGS; - + return LOAD_FPU_REGS; } @@ -1600,11 +1600,11 @@ pdp11_secondary_reload (bool in_p ATTRIBUTE_UNUSED, static bool pdp11_secondary_memory_needed (machine_mode, reg_class_t c1, reg_class_t c2) { - int fromfloat = (c1 == LOAD_FPU_REGS || c1 == NO_LOAD_FPU_REGS || + int fromfloat = (c1 == LOAD_FPU_REGS || c1 == NO_LOAD_FPU_REGS || c1 == FPU_REGS); - int tofloat = (c2 == LOAD_FPU_REGS || c2 == NO_LOAD_FPU_REGS || + int tofloat = (c2 == LOAD_FPU_REGS || c2 == NO_LOAD_FPU_REGS || c2 == FPU_REGS); - + return (fromfloat != tofloat); } @@ -1624,13 +1624,13 @@ pdp11_legitimate_address_p (machine_mode mode, rtx operand, bool strict, /* accept @#address */ if (CONSTANT_ADDRESS_P (operand)) return true; - + switch (GET_CODE (operand)) { case REG: /* accept (R0) */ return !strict || REGNO_OK_FOR_BASE_P (REGNO (operand)); - + case PLUS: /* accept X(R0) */ return GET_CODE (XEXP (operand, 0)) == REG @@ -1672,11 +1672,11 @@ pdp11_legitimate_address_p (machine_mode mode, rtx operand, bool strict, xfoob = XEXP (operand, 0); /* (MEM:xx (MEM:xx ())) is not valid for SI, DI and currently - also forbidden for float, because we have to handle this + also forbidden for float, because we have to handle this in output_move_double and/or output_move_quad() - we could - do it, but currently it's not worth it!!! - now that DFmode cannot go into CPU register file, - maybe I should allow float ... + do it, but currently it's not worth it!!! + now that DFmode cannot go into CPU register file, + maybe I should allow float ... but then I have to handle memory-to-memory moves in movdf ?? */ if (GET_MODE_BITSIZE(mode) > 16) return false; @@ -1722,7 +1722,7 @@ pdp11_legitimate_address_p (machine_mode mode, rtx operand, bool strict, reg number REGNO. */ enum reg_class pdp11_regno_reg_class (int regno) -{ +{ if (regno == ARG_POINTER_REGNUM) return NOTSP_REG; else if (regno == CC_REGNUM || regno == FCC_REGNUM) @@ -1759,9 +1759,9 @@ pdp11_reg_save_size (void) for (regno = AC0_REGNUM; regno <= AC5_REGNUM; regno++) if (pdp11_saved_regno (regno)) offset += 8; - + return offset; -} +} /* Return the offset between two registers, one to be eliminated, and the other its replacement, at the start of a routine. */ @@ -1791,7 +1791,7 @@ output_addr_const_pdp11 (FILE *file, rtx x) { char buf[256]; int i; - + restart: switch (GET_CODE (x)) { @@ -1891,7 +1891,7 @@ pdp11_return_in_memory (const_tree type, const_tree fntype ATTRIBUTE_UNUSED) On the pdp11 the value is found in R0 (or ac0??? not without FPU!!!! ) */ static rtx -pdp11_function_value (const_tree valtype, +pdp11_function_value (const_tree valtype, const_tree fntype_or_decl ATTRIBUTE_UNUSED, bool outgoing ATTRIBUTE_UNUSED) { @@ -1935,7 +1935,7 @@ pdp11_expand_shift (rtx *operands, rtx (*shift_sc) (rtx, rtx, rtx), { rtx r, test; rtx_code_label *lb; - + if (CONST_INT_P (operands[2]) && pdp11_small_shift (INTVAL (operands[2]))) emit_insn ((*shift_sc) (operands[0], operands[1], operands[2])); else if (TARGET_40_PLUS) @@ -1988,7 +1988,7 @@ pdp11_assemble_shift (rtx *operands, machine_mode m, int code) inops[0] = operands[0]; pdp11_expand_operands (inops, exops, 1, 2, action, either); } - + if (!small) { /* Loop case, generate the top of loop label. */ @@ -2154,8 +2154,8 @@ pdp11_md_asm_adjust (vec<rtx> & /*outputs*/, vec<rtx> & /*inputs*/, /* Worker function for TARGET_TRAMPOLINE_INIT. - trampoline - how should i do it in separate i+d ? - have some allocate_trampoline magic??? + trampoline - how should i do it in separate i+d ? + have some allocate_trampoline magic??? the following should work for shared I/D: @@ -2252,7 +2252,7 @@ static void pdp11_output_ident (const char *ident) if (!startswith (ident, "GCC:")) fprintf (asm_out_file, "\t.ident\t\"%s\"\n", ident); } - + } /* This emits a (user) label, which gets a "_" prefix except for DEC @@ -2281,7 +2281,7 @@ pdp11_output_def (FILE *file, const char *label1, const char *label2) assemble_name (file, label1); putc (',', file); assemble_name (file, label2); - } + } putc ('\n', file); } @@ -2314,7 +2314,7 @@ pdp11_asm_named_section (const char *name, unsigned int flags, { const char *rwro = (flags & SECTION_WRITE) ? "rw" : "ro"; const char *insdat = (flags & SECTION_CODE) ? "i" : "d"; - + gcc_assert (TARGET_DEC_ASM); fprintf (asm_out_file, "\t.psect\t%s,con,%s,%s\n", name, insdat, rwro); } @@ -2333,12 +2333,12 @@ pdp11_asm_init_sections (void) ".bss"); } } - + static void pdp11_file_start (void) { default_file_start (); - + if (TARGET_DEC_ASM) fprintf (asm_out_file, "\t.enabl\tlsb,reg\n\n"); } diff --git a/gcc/config/pdp11/pdp11.h b/gcc/config/pdp11/pdp11.h index 6c8e045..f6997b6 100644 --- a/gcc/config/pdp11/pdp11.h +++ b/gcc/config/pdp11/pdp11.h @@ -69,7 +69,7 @@ along with GCC; see the file COPYING3. If not see #define SHORT_TYPE_SIZE 16 #define INT_TYPE_SIZE (TARGET_INT16 ? 16 : 32) #define LONG_TYPE_SIZE 32 -#define LONG_LONG_TYPE_SIZE 64 +#define LONG_LONG_TYPE_SIZE 64 /* machine types from ansi */ #define SIZE_TYPE "short unsigned int" /* definition of size_t */ @@ -93,7 +93,7 @@ along with GCC; see the file COPYING3. If not see /* Define that floats are in VAX order, not high word first as for ints. */ #define FLOAT_WORDS_BIG_ENDIAN 0 -/* Width of a word, in units (bytes). +/* Width of a word, in units (bytes). UNITS OR BYTES - seems like units */ #define UNITS_PER_WORD 2 @@ -107,7 +107,7 @@ extern const struct real_format pdp11_f_format; extern const struct real_format pdp11_d_format; /* Maximum sized of reasonable data type -- DImode ...*/ -#define MAX_FIXED_MODE_SIZE 64 +#define MAX_FIXED_MODE_SIZE 64 /* Allocation boundary (in *bits*) for storing pointers in memory. */ #define POINTER_BOUNDARY 16 @@ -144,7 +144,7 @@ extern const struct real_format pdp11_d_format; All registers that the compiler knows about must be given numbers, even those that are not normally considered general registers. - we have 8 integer registers, plus 6 float + we have 8 integer registers, plus 6 float (don't use scratch float !) */ /* 1 for registers that have pervasive standard uses @@ -153,7 +153,7 @@ extern const struct real_format pdp11_d_format; On the pdp, these are: Reg 7 = pc; reg 6 = sp; - reg 5 = fp; not necessarily! + reg 5 = fp; not necessarily! */ #define FIXED_REGISTERS \ @@ -203,7 +203,7 @@ extern const struct real_format pdp11_d_format; For any two classes, it is very desirable that there be another class that represents their union. */ - + /* The pdp has a couple of classes: MUL_REGS are used for odd numbered regs, to use in 16-bit multiplication @@ -211,7 +211,7 @@ MUL_REGS are used for odd numbered regs, to use in 16-bit multiplication GENERAL_REGS is all cpu LOAD_FPU_REGS is the first four cpu regs, they are easier to load NO_LOAD_FPU_REGS is ac4 and ac5, currently - difficult to load them -FPU_REGS is all fpu regs +FPU_REGS is all fpu regs CC_REGS is the condition codes (CPU and FPU) */ @@ -292,7 +292,7 @@ enum reg_class /* Return TRUE if the class is a CPU register. */ #define CPU_REG_CLASS(CLASS) \ (CLASS >= NOTR0_REG && CLASS <= GENERAL_REGS) - + /* Return the maximum number of consecutive registers needed to represent mode MODE in a register of class CLASS. */ #define CLASS_MAX_NREGS(CLASS, MODE) \ @@ -316,7 +316,7 @@ enum reg_class #define PUSH_ROUNDING(BYTES) pdp11_push_rounding (BYTES) -/* current_first_parm_offset stores the # of registers pushed on the +/* current_first_parm_offset stores the # of registers pushed on the stack */ extern int current_first_parm_offset; @@ -328,7 +328,7 @@ extern int current_first_parm_offset; If the precise function being called is known, FUNC is its FUNCTION_DECL; otherwise, FUNC is 0. */ #define BASE_RETURN_VALUE_REG(MODE) \ - (FLOAT_MODE_P (MODE) ? AC0_REGNUM : RETVAL_REGNUM) + (FLOAT_MODE_P (MODE) ? AC0_REGNUM : RETVAL_REGNUM) /* 1 if N is a possible register number for function argument passing. - not used on pdp */ @@ -462,7 +462,7 @@ extern int current_first_parm_offset; #define DEFAULT_SIGNED_CHAR 1 /* Max number of bytes we can move from memory to memory - in one reasonably fast instruction. + in one reasonably fast instruction. */ #define MOVE_MAX 2 diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc b/gcc/config/riscv/riscv-vector-builtins-bases.cc index 193392f..fcc1bf9 100644 --- a/gcc/config/riscv/riscv-vector-builtins-bases.cc +++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc @@ -2247,7 +2247,7 @@ public: { return (CODE == CLZ || CODE == CTZ) ? false : true; } - + rtx expand (function_expander &e) const override { switch (e.op_info->op) diff --git a/gcc/config/riscv/riscv-vector-builtins-shapes.cc b/gcc/config/riscv/riscv-vector-builtins-shapes.cc index 3339541..22cbbc2 100644 --- a/gcc/config/riscv/riscv-vector-builtins-shapes.cc +++ b/gcc/config/riscv/riscv-vector-builtins-shapes.cc @@ -1268,7 +1268,7 @@ struct crypto_vv_no_op_type_def : public build_base if (overloaded_p && !instance.base->can_be_overloaded_p (instance.pred)) return nullptr; b.append_base_name (instance.base_name); - + if (!overloaded_p) { b.append_name (operand_suffixes[instance.op_info->op]); diff --git a/gcc/config/rl78/rl78.cc b/gcc/config/rl78/rl78.cc index 25f6606..8ce9331 100644 --- a/gcc/config/rl78/rl78.cc +++ b/gcc/config/rl78/rl78.cc @@ -1675,7 +1675,7 @@ static void rl78_start_function (FILE *file) { int i; - + add_vector_labels (file, "interrupt"); add_vector_labels (file, "vector"); diff --git a/gcc/config/rs6000/aix.h b/gcc/config/rs6000/aix.h index 03d39b1..7f6c45e 100644 --- a/gcc/config/rs6000/aix.h +++ b/gcc/config/rs6000/aix.h @@ -182,7 +182,7 @@ Don't do this until the fixed IBM assembler is more generally available. When this becomes permanently defined, the ASM_OUTPUT_EXTERNAL, ASM_OUTPUT_EXTERNAL_LIBCALL, and RS6000_OUTPUT_BASENAME macros will no - longer be needed. Also, the extern declaration of mcount in + longer be needed. Also, the extern declaration of mcount in rs6000_xcoff_file_start will no longer be needed. */ /* #define ASM_SPEC "-u %(asm_cpu)" */ diff --git a/gcc/config/rs6000/aix71.h b/gcc/config/rs6000/aix71.h index 41037b3..4350dcd 100644 --- a/gcc/config/rs6000/aix71.h +++ b/gcc/config/rs6000/aix71.h @@ -125,7 +125,7 @@ do { \ %{mpe: -I%R/usr/lpp/ppe.poe/include} \ %{pthread: -D_THREAD_SAFE}" -/* The GNU C++ standard library requires that these macros be +/* The GNU C++ standard library requires that these macros be defined. Synchronize with libstdc++ os_defines.h. */ #define CPLUSPLUS_CPP_SPEC_COMMON \ "-D_ALL_SOURCE -D__COMPATMATH__ \ @@ -257,7 +257,7 @@ do { \ #define LD_INIT_SWITCH "-binitfini" #ifndef _AIX52 -extern long long int atoll(const char *); +extern long long int atoll(const char *); #endif /* This target uses the aix64.opt file. */ diff --git a/gcc/config/rs6000/altivec.h b/gcc/config/rs6000/altivec.h index c9f9486..dcf0f28 100644 --- a/gcc/config/rs6000/altivec.h +++ b/gcc/config/rs6000/altivec.h @@ -35,7 +35,7 @@ #endif /* If __APPLE_ALTIVEC__ is defined, the compiler supports 'vector', - 'pixel' and 'bool' as context-sensitive AltiVec keywords (in + 'pixel' and 'bool' as context-sensitive AltiVec keywords (in non-AltiVec contexts, they revert to their original meanings, if any), so we do not need to define them as macros. Also, avoid defining them as macros for C++ with strict ANSI, as diff --git a/gcc/config/rs6000/darwin.h b/gcc/config/rs6000/darwin.h index e8b1949..bd5a016 100644 --- a/gcc/config/rs6000/darwin.h +++ b/gcc/config/rs6000/darwin.h @@ -487,14 +487,14 @@ default, as kernel code doesn't save/restore those registers. */ #define OS_MISSING_ALTIVEC (flag_mkernel || flag_apple_kext) -/* Darwin has support for section anchors on powerpc*. +/* Darwin has support for section anchors on powerpc*. It is disabled for any section containing a "zero-sized item" (because these are re-written as size=1 to be compatible with the OSX ld64). The re-writing would interfere with the computation of anchor offsets. Therefore, we place zero-sized items in their own sections and make such sections unavailable to section anchoring. */ -#undef TARGET_ASM_OUTPUT_ANCHOR +#undef TARGET_ASM_OUTPUT_ANCHOR #define TARGET_ASM_OUTPUT_ANCHOR darwin_asm_output_anchor #undef TARGET_USE_ANCHORS_FOR_SYMBOL_P diff --git a/gcc/config/rs6000/driver-rs6000.cc b/gcc/config/rs6000/driver-rs6000.cc index fd457e7..a054827 100644 --- a/gcc/config/rs6000/driver-rs6000.cc +++ b/gcc/config/rs6000/driver-rs6000.cc @@ -629,7 +629,7 @@ host_detect_local_cpu (int argc, const char **argv) arch = strcmp (argv[0], "cpu") == 0; if (!arch && strcmp (argv[0], "tune")) return NULL; - + if (arch) cpu = "powerpc"; diff --git a/gcc/config/rs6000/freebsd.h b/gcc/config/rs6000/freebsd.h index 0f42dc1..0c83e9e 100644 --- a/gcc/config/rs6000/freebsd.h +++ b/gcc/config/rs6000/freebsd.h @@ -50,7 +50,7 @@ /************************[ Target stuff ]***********************************/ -/* Define the actual types of some ANSI-mandated types. +/* Define the actual types of some ANSI-mandated types. Needs to agree with <machine/ansi.h>. GCC defaults come from c-decl.cc, c-common.cc, and config/<arch>/<arch>.h. */ diff --git a/gcc/config/rs6000/freebsd64.h b/gcc/config/rs6000/freebsd64.h index 6740170..627fd42 100644 --- a/gcc/config/rs6000/freebsd64.h +++ b/gcc/config/rs6000/freebsd64.h @@ -237,7 +237,7 @@ extern int dot_symbols; /************************[ Target stuff ]***********************************/ -/* Define the actual types of some ANSI-mandated types. +/* Define the actual types of some ANSI-mandated types. Needs to agree with <machine/ansi.h>. GCC defaults come from c-decl.cc, c-common.cc, and config/<arch>/<arch>.h. */ diff --git a/gcc/config/rs6000/host-darwin.cc b/gcc/config/rs6000/host-darwin.cc index 15c40b1..fa9140d 100644 --- a/gcc/config/rs6000/host-darwin.cc +++ b/gcc/config/rs6000/host-darwin.cc @@ -93,7 +93,7 @@ segv_handler (int sig ATTRIBUTE_UNUSED, || (faulting_insn & 0xFC1F8000) == 0xBC018000 /* stmw xxx, -yyy(%r1) */) { char *shell_name; - + fnotice (stderr, "Out of stack space.\n"); shell_name = getenv ("SHELL"); if (shell_name != NULL) @@ -110,23 +110,23 @@ segv_handler (int sig ATTRIBUTE_UNUSED, { "zsh", "limit stacksize 32m" } }; size_t i; - + for (i = 0; i < ARRAY_SIZE (shell_commands); i++) if (strcmp (shell_commands[i][0], shell_name + 1) == 0) { - fnotice (stderr, + fnotice (stderr, "Try running '%s' in the shell to raise its limit.\n", shell_commands[i][1]); } } - + if (global_dc->m_abort_on_error) fancy_abort (__FILE__, __LINE__, __FUNCTION__); exit (FATAL_EXIT_CODE); } - fprintf (stderr, "[address=%08lx pc=%08x]\n", + fprintf (stderr, "[address=%08lx pc=%08x]\n", uc->uc_mcontext->MC_FLD(es).MC_FLD(dar), uc->uc_mcontext->MC_FLD(ss).MC_FLD(srr0)); internal_error ("segmentation fault"); @@ -148,7 +148,7 @@ darwin_rs6000_extra_signals (void) sigemptyset(&sact.sa_mask); sact.sa_flags = SA_ONSTACK | SA_SIGINFO; sact.sa_sigaction = segv_handler; - if (sigaction (SIGSEGV, &sact, 0) < 0) + if (sigaction (SIGSEGV, &sact, 0) < 0) fatal_error (input_location, "While setting up signal handler: %m"); } diff --git a/gcc/config/rs6000/linux.h b/gcc/config/rs6000/linux.h index 5f6cede..d247f41 100644 --- a/gcc/config/rs6000/linux.h +++ b/gcc/config/rs6000/linux.h @@ -116,7 +116,7 @@ /* We are 32-bit all the time, so optimize a little. */ #undef TARGET_64BIT #define TARGET_64BIT 0 - + /* We don't need to generate entries in .fixup, except when -mrelocatable or -mrelocatable-lib is given. */ #undef RELOCATABLE_NEEDS_FIXUP diff --git a/gcc/config/rs6000/ppu_intrinsics.h b/gcc/config/rs6000/ppu_intrinsics.h index 4d91c72..9ac1caf 100644 --- a/gcc/config/rs6000/ppu_intrinsics.h +++ b/gcc/config/rs6000/ppu_intrinsics.h @@ -34,7 +34,7 @@ #ifdef __cplusplus extern "C" { -#endif +#endif /* * unsigned int __cntlzw(unsigned int) @@ -113,7 +113,7 @@ extern "C" { * void __mtfsb1(int) * double __setflm(double) * - * dcbt intrinsics + * dcbt intrinsics * void __protected_unlimited_stream_set (unsigned int direction, const void *add, unsigned int ID) * void __protected_stream_set (unsigned int direction, const void *add, unsigned int ID) * void __protected_stream_stop_all (void) @@ -178,7 +178,7 @@ typedef int __V4SI __attribute__((vector_size(16))); #ifdef __powerpc64__ #define __mtspr(spr, value) \ __asm__ volatile ("mtspr %0,%1" : : "n" (spr), "r" (value)) - + #define __mfspr(spr) __extension__ \ ({ unsigned long long result; \ __asm__ volatile ("mfspr %0,%1" : "=r" (result) : "n" (spr)); \ @@ -211,7 +211,7 @@ typedef int __V4SI __attribute__((vector_size(16))); #define __dcbf(base) \ __asm__ volatile ("dcbf %y0" : "=Z" (*(__V4SI*) (base)) : : "memory") - + #define __dcbz(base) \ __asm__ volatile ("dcbz %y0" : "=Z" (*(__V4SI*) (base)) : : "memory") @@ -226,7 +226,7 @@ typedef int __V4SI __attribute__((vector_size(16))); #define __icbi(base) \ __asm__ volatile ("icbi %y0" : "=Z" (*(__V4SI*) (base)) : : "memory") - + #define __dcbt_TH1000(EATRUNC, D, UG, ID) \ __asm__ volatile ("dcbt %y0,8" \ : "=Z" (*(__V4SI*) (__SIZE_TYPE__)((((__SIZE_TYPE__) (EATRUNC)) & ~0x7F) \ @@ -390,7 +390,7 @@ typedef int __V4SI __attribute__((vector_size(16))); #define __mtfsf(mask,value) \ __asm__ volatile ("mtfsf %0,%1" : : "n" (mask), "d" ((double) (value))) - + #define __mtfsfi(bits,field) \ __asm__ volatile ("mtfsfi %0,%1" : : "n" (bits), "n" (field)) @@ -406,10 +406,10 @@ typedef int __V4SI __attribute__((vector_size(16))); /* __builtin_fabs may perform unnecessary rounding. */ -/* Rename __fabs and __fabsf to work around internal prototypes defined - in bits/mathcalls.h with some glibc versions. */ -#define __fabs __ppu_fabs -#define __fabsf __ppu_fabsf +/* Rename __fabs and __fabsf to work around internal prototypes defined + in bits/mathcalls.h with some glibc versions. */ +#define __fabs __ppu_fabs +#define __fabsf __ppu_fabsf static __inline__ double __fabs(double x) __attribute__((always_inline)); static __inline__ double diff --git a/gcc/config/rs6000/rs6000-c.cc b/gcc/config/rs6000/rs6000-c.cc index 5ff346e..4dc80e5 100644 --- a/gcc/config/rs6000/rs6000-c.cc +++ b/gcc/config/rs6000/rs6000-c.cc @@ -809,7 +809,7 @@ is_float128_p (tree t) && TARGET_LONG_DOUBLE_128 && t == long_double_type_node)); } - + /* Return true iff ARGTYPE can be compatibly passed as PARMTYPE. */ static bool diff --git a/gcc/config/rs6000/rs6000-call.cc b/gcc/config/rs6000/rs6000-call.cc index a039ff7..549fa57 100644 --- a/gcc/config/rs6000/rs6000-call.cc +++ b/gcc/config/rs6000/rs6000-call.cc @@ -407,15 +407,15 @@ rs6000_discover_homogeneous_aggregate (machine_mode mode, const_tree type, The AIX ABI for the RS/6000 specifies that all structures are returned in memory. The Darwin ABI does the same. - + For the Darwin 64 Bit ABI, a function result can be returned in registers or in memory, depending on the size of the return data type. If it is returned in registers, the value occupies the same registers as it would if it were the first and only function argument. Otherwise, the function places its result in memory at the location pointed to by GPR3. - - The SVR4 ABI specifies that structures <= 8 bytes are returned in r3/r4, + + The SVR4 ABI specifies that structures <= 8 bytes are returned in r3/r4, but a draft put them in memory, and GCC used to implement the draft instead of the final standard. Therefore, aix_struct_return controls this instead of DEFAULT_ABI; V.4 targets needing backward @@ -1045,10 +1045,10 @@ int rs6000_darwin64_struct_check_p (machine_mode mode, const_tree type) { return rs6000_darwin64_abi - && ((mode == BLKmode - && TREE_CODE (type) == RECORD_TYPE + && ((mode == BLKmode + && TREE_CODE (type) == RECORD_TYPE && int_size_in_bytes (type) > 0) - || (type && TREE_CODE (type) == RECORD_TYPE + || (type && TREE_CODE (type) == RECORD_TYPE && int_size_in_bytes (type) == 8)) ? 1 : 0; } @@ -1178,7 +1178,7 @@ rs6000_function_arg_advance_1 (CUMULATIVE_ARGS *cum, machine_mode mode, { fprintf (stderr, "function_adv: words = %2d, align=%d, size=%d", cum->words, TYPE_ALIGN (type), size); - fprintf (stderr, + fprintf (stderr, "nargs = %4d, proto = %d, mode = %4s (darwin64 abi)\n", cum->nargs_prototype, cum->prototype, GET_MODE_NAME (mode)); @@ -2568,9 +2568,9 @@ rs6000_gimplify_va_arg (tree valist, tree type, gimple_seq *pre_p, /* We need to deal with the fact that the darwin ppc64 ABI is defined by an earlier version of gcc, with the property that it always applied alignment adjustments to the va-args (even for zero-sized types). The cheapest way - to deal with this is to replicate the effect of the part of - std_gimplify_va_arg_expr that carries out the align adjust, for the case - of relevance. + to deal with this is to replicate the effect of the part of + std_gimplify_va_arg_expr that carries out the align adjust, for the case + of relevance. We don't need to check for pass-by-reference because of the test above. We can return a simplifed answer, since we know there's no offset to add. */ diff --git a/gcc/config/rs6000/rs6000-internal.h b/gcc/config/rs6000/rs6000-internal.h index 3a6cc31..0f6e1fd 100644 --- a/gcc/config/rs6000/rs6000-internal.h +++ b/gcc/config/rs6000/rs6000-internal.h @@ -149,7 +149,7 @@ extern machine_mode rs6000_promote_function_mode (const_tree type ATTRIBUTE_UNUS machine_mode mode, int *punsignedp ATTRIBUTE_UNUSED, const_tree, int); -extern bool rs6000_return_in_memory (const_tree type, +extern bool rs6000_return_in_memory (const_tree type, const_tree fntype ATTRIBUTE_UNUSED); extern bool rs6000_return_in_msb (const_tree valtype); extern bool rs6000_pass_by_reference (cumulative_args_t, diff --git a/gcc/config/rs6000/rs6000-logue.cc b/gcc/config/rs6000/rs6000-logue.cc index fdb6414..c87058b 100644 --- a/gcc/config/rs6000/rs6000-logue.cc +++ b/gcc/config/rs6000/rs6000-logue.cc @@ -1376,7 +1376,7 @@ rs6000_emit_eh_reg_restore (rtx source, rtx scratch) /* Freeze lr_save_p. We've just emitted rtl that depends on the state of lr_save_p so any change from here on would be a bug. In particular, stop rs6000_ra_ever_killed from considering the SET - of lr we may have added just above. */ + of lr we may have added just above. */ cfun->machine->lr_save_state = info->lr_save_p + 1; } @@ -1462,7 +1462,7 @@ rs6000_emit_stack_tie (rtx fp, bool hard_frame_needed) /* Allocate SIZE_INT bytes on the stack using a store with update style insn and set the appropriate attributes for the generated insn. Return the first insn which adjusts the stack pointer or the last insn before - the stack adjustment loop. + the stack adjustment loop. SIZE_INT is used to create the CFI note for the allocation. @@ -1487,7 +1487,7 @@ rs6000_emit_allocate_stack_1 (HOST_WIDE_INT size_int, rtx orig_sp) try_split (PATTERN (insn), insn, 0); size_rtx = tmp_reg; } - + if (TARGET_32BIT) insn = emit_insn (gen_movsi_update_stack (stack_pointer_rtx, stack_pointer_rtx, @@ -4689,7 +4689,7 @@ rs6000_emit_epilogue (enum epilogue_type epilogue_type) if (newptr_regno != 1 && REGNO (frame_reg_rtx) != newptr_regno) frame_reg_rtx = gen_rtx_REG (Pmode, newptr_regno); - + if (end_save + ptr_off != 0) { rtx offset = GEN_INT (end_save + ptr_off); diff --git a/gcc/config/rs6000/rs6000-p8swap.cc b/gcc/config/rs6000/rs6000-p8swap.cc index 05fb760..614cecc 100644 --- a/gcc/config/rs6000/rs6000-p8swap.cc +++ b/gcc/config/rs6000/rs6000-p8swap.cc @@ -133,7 +133,7 @@ already in a register. In some cases, this mask may be a constant that we can discover with ud-chains, in which case the above transformation is ok. However, the common usage here is for the - mask to be produced by an UNSPEC_LVSL, in which case the mask + mask to be produced by an UNSPEC_LVSL, in which case the mask cannot be known at compile time. In such a case we would have to generate several instructions to compute M' as above at run time, and a cost model is needed again. @@ -634,7 +634,7 @@ v2df_reduction_p (rtx op) { if (GET_MODE (op) != V2DFmode) return false; - + enum rtx_code code = GET_CODE (op); if (code != PLUS && code != SMIN && code != SMAX) return false; @@ -913,7 +913,7 @@ insn_is_swappable_p (swap_web_entry *insn_entry, rtx insn, return 0; if (GET_CODE (XEXP (lhs, 0)) == AND) return 0; - + *special = SH_NOSWAP_ST; return 1; } @@ -1355,7 +1355,7 @@ adjust_vperm (rtx_insn *insn) break; } gcc_assert (swap_insn); - + /* Find the load. */ insn_info = DF_INSN_INFO_GET (swap_insn); rtx_insn *load_insn = 0; @@ -2094,7 +2094,7 @@ alignment_with_canonical_addr (rtx align) return gen_rtx_AND (GET_MODE (align), canon, GEN_INT (-16)); } -/* Check whether an rtx is an alignment mask, and if so, return +/* Check whether an rtx is an alignment mask, and if so, return a fully-expanded rtx for the masking operation. */ static rtx alignment_mask (rtx_insn *insn) @@ -2397,7 +2397,7 @@ recombine_lvx_stvx_patterns (function *fun) remove_insn (to_delete[i].replace_insn); to_delete[i].replace_insn->set_deleted (); } - + free (to_delete); } diff --git a/gcc/config/rs6000/rs6000-string.cc b/gcc/config/rs6000/rs6000-string.cc index 55b4133..de618da 100644 --- a/gcc/config/rs6000/rs6000-string.cc +++ b/gcc/config/rs6000/rs6000-string.cc @@ -1337,7 +1337,7 @@ expand_compare_loop (rtx operands[]) { /* If remainder length < word length, branch to final cleanup compare. */ - + if (!bytes_is_const) { do_ifelse (CCmode, LT, cmp_rem, GEN_INT (load_mode_size), @@ -2695,7 +2695,7 @@ gen_lvx_v4si_move (rtx dest, rtx src) if (MEM_P (dest)) return gen_altivec_stvx_v4si_internal (dest, src); - else + else return gen_altivec_lvx_v4si_internal (dest, src); } @@ -2918,7 +2918,7 @@ expand_block_move (rtx operands[], bool might_overlap) emit_insn (stores[i]); num_reg = 0; } - + } return 1; diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc index 0bf8bae..950fd94 100644 --- a/gcc/config/rs6000/rs6000.cc +++ b/gcc/config/rs6000/rs6000.cc @@ -4318,10 +4318,10 @@ rs6000_option_override_internal (bool global_init_p) } } - /* Set the Darwin64 ABI as default for 64-bit Darwin. + /* Set the Darwin64 ABI as default for 64-bit Darwin. So far, the only darwin64 targets are also MACH-O. */ if (TARGET_MACHO - && DEFAULT_ABI == ABI_DARWIN + && DEFAULT_ABI == ABI_DARWIN && TARGET_64BIT) { if (main_target_opt != NULL && !main_target_opt->x_rs6000_darwin64_abi) @@ -4946,7 +4946,7 @@ rs6000_vector_alignment_reachable (const_tree type ATTRIBUTE_UNUSED, bool is_pac } /* Return true if the vector misalignment factor is supported by the - target. */ + target. */ static bool rs6000_builtin_support_vector_misalignment (machine_mode mode, const_tree type, @@ -8074,7 +8074,7 @@ rs6000_split_vec_extract_var (rtx dest, rtx src, rtx element, rtx tmp_gpr, /* Return alignment of TYPE. Existing alignment is ALIGN. HOW selects whether the alignment is abi mandated, optional, or both abi and optional alignment. */ - + unsigned int rs6000_data_alignment (tree type, unsigned int align, enum data_align how) { @@ -8699,7 +8699,7 @@ virtual_stack_registers_memory_p (rtx op) to determine whether -mcmodel=medium code can use TOC pointer relative addressing for OP. This means the alignment of the TOC pointer must also be taken into account, and unfortunately that is - only 8 bytes. */ + only 8 bytes. */ #ifndef POWERPC64_TOC_POINTER_ALIGNMENT #define POWERPC64_TOC_POINTER_ALIGNMENT 8 @@ -8847,8 +8847,8 @@ static const_rtx tocrel_base_oac, tocrel_offset_oac; /* Return true if OP is a toc pointer relative address (the output of create_TOC_reference). If STRICT, do not match non-split - -mcmodel=large/medium toc pointer relative addresses. If the pointers - are non-NULL, place base and offset pieces in TOCREL_BASE_RET and + -mcmodel=large/medium toc pointer relative addresses. If the pointers + are non-NULL, place base and offset pieces in TOCREL_BASE_RET and TOCREL_OFFSET_RET respectively. */ bool @@ -9575,7 +9575,7 @@ rs6000_legitimize_tls_address_aix (rtx addr, enum tls_model model) tocref = create_TOC_reference (modaddr, NULL_RTX); rtx modmem = gen_const_mem (Pmode, tocref); set_mem_alias_set (modmem, get_TOC_alias_set ()); - + rtx modreg = gen_reg_rtx (Pmode); emit_insn (gen_rtx_SET (modreg, modmem)); @@ -10139,13 +10139,13 @@ rs6000_offsettable_memref_p (rtx op, machine_mode reg_mode, bool strict) This takes into account how many parallel operations we can actually do of a given type, and also the latency. P8: - int add/sub 6/cycle + int add/sub 6/cycle mul 2/cycle vect add/sub/mul 2/cycle fp add/sub/mul 2/cycle dfp 1/cycle */ - + static int rs6000_reassociation_width (unsigned int opc ATTRIBUTE_UNUSED, machine_mode mode) @@ -10160,7 +10160,7 @@ rs6000_reassociation_width (unsigned int opc ATTRIBUTE_UNUSED, return 1; if (VECTOR_MODE_P (mode)) return 4; - if (INTEGRAL_MODE_P (mode)) + if (INTEGRAL_MODE_P (mode)) return 1; if (FLOAT_MODE_P (mode)) return 4; @@ -14481,7 +14481,7 @@ print_operand (FILE *file, rtx x, int code) ? reg - 32 : reg - FIRST_ALTIVEC_REGNO + 32); -#ifdef TARGET_REGNAMES +#ifdef TARGET_REGNAMES if (TARGET_REGNAMES) fprintf (file, "%%vs%d", vsx_reg); else @@ -21227,7 +21227,7 @@ rs6000_darwin_file_start (void) darwin_file_start (); /* Determine the argument to -mcpu=. Default to G3 if not specified. */ - + if (rs6000_default_cpu != 0 && rs6000_default_cpu[0] != '\0') cpu_id = rs6000_default_cpu; @@ -22510,7 +22510,7 @@ rs6000_rtx_costs (rtx x, machine_mode mode, int outer_code, return false; } /* fall through */ - + case ASHIFTRT: case LSHIFTRT: case ROTATE: @@ -23083,7 +23083,7 @@ rs6000_emit_swdiv (rtx dst, rtx n, rtx d, bool note_p) for (i = 0, xprev = x1, eprev = e0; i < passes - 2; ++i, xprev = xnext, eprev = enext) { - + /* enext = eprev * eprev */ enext = gen_reg_rtx (mode); emit_insn (gen_mul (enext, eprev, eprev)); @@ -23350,7 +23350,7 @@ rs6000_emit_parity (rtx dst, rtx src) vperm 9,10,11,12 - places the desired result in vr9. However, in LE mode the + places the desired result in vr9. However, in LE mode the vector contents will be vr10 = 00000003 00000002 00000001 00000000 @@ -23567,7 +23567,7 @@ altivec_expand_vec_perm_const (rtx target, rtx op0, rtx op1, one_vec = true; break; } - + /* Look for splat patterns. */ if (one_vec) { @@ -23969,7 +23969,7 @@ rs6000_function_value (const_tree valtype, int n_elts; /* Special handling for structs in darwin64. */ - if (TARGET_MACHO + if (TARGET_MACHO && rs6000_darwin64_struct_check_p (TYPE_MODE (valtype), valtype)) { CUMULATIVE_ARGS valcum; @@ -24826,7 +24826,7 @@ rs6000_valid_attribute_p (tree fndecl, IDENTIFIER_POINTER (tname)); else fprintf (stderr, "function: unknown\n"); - + fprintf (stderr, "args:"); rs6000_debug_target_options (args, " "); fprintf (stderr, "\n"); @@ -25095,7 +25095,7 @@ static void rs6000_function_specific_restore (struct gcc_options *opts, struct gcc_options */* opts_set */, struct cl_target_option *ptr) - + { opts->x_rs6000_isa_flags = ptr->x_rs6000_isa_flags; opts->x_rs6000_isa_flags_explicit = ptr->x_rs6000_isa_flags_explicit; @@ -26749,7 +26749,7 @@ is_lfs_stfs_insn (rtx_insn *insn) rtx set = XVECEXP (pattern, 0, 0); if (GET_CODE (set) != SET) return false; - + rtx clobber = XVECEXP (pattern, 0, 1); if (GET_CODE (clobber) != CLOBBER) return false; diff --git a/gcc/config/rs6000/si2vmx.h b/gcc/config/rs6000/si2vmx.h index d0a1a28..fb03bdc 100644 --- a/gcc/config/rs6000/si2vmx.h +++ b/gcc/config/rs6000/si2vmx.h @@ -3,7 +3,7 @@ This file is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free - Software Foundation; either version 3 of the License, or (at your option) + Software Foundation; either version 3 of the License, or (at your option) any later version. This file is distributed in the hope that it will be useful, but WITHOUT @@ -30,7 +30,7 @@ /* Specify a default halt action for spu_hcmpeq and spu_hcmpgt intrinsics. - * Users can override the action by defining it prior to including this + * Users can override the action by defining it prior to including this * header file. */ #ifndef SPU_HALT_ACTION @@ -38,7 +38,7 @@ #endif /* Specify a default stop action for the spu_stop intrinsic. - * Users can override the action by defining it prior to including this + * Users can override the action by defining it prior to including this * header file. */ #ifndef SPU_STOP_ACTION @@ -47,7 +47,7 @@ /* Specify a default action for unsupported intrinsic. - * Users can override the action by defining it prior to including this + * Users can override the action by defining it prior to including this * header file. */ #ifndef SPU_UNSUPPORTED_ACTION @@ -55,7 +55,7 @@ #endif -/* Casting intrinsics - from scalar to quadword +/* Casting intrinsics - from scalar to quadword */ static __inline qword si_from_uchar(unsigned char c) { @@ -274,7 +274,7 @@ static __inline qword si_absdb(qword a, qword b) return ((qword)(dc)); } -/* Add intrinsics +/* Add intrinsics */ #define si_a(_a, _b) ((qword)(vec_add((vec_uint4)(_a), (vec_uint4)(_b)))) @@ -282,14 +282,14 @@ static __inline qword si_absdb(qword a, qword b) static __inline qword si_ai(qword a, int b) { - return ((qword)(vec_add((vec_int4)(a), + return ((qword)(vec_add((vec_int4)(a), vec_splat((vec_int4)(si_from_int(b)), 0)))); } static __inline qword si_ahi(qword a, short b) { - return ((qword)(vec_add((vec_short8)(a), + return ((qword)(vec_add((vec_short8)(a), vec_splat((vec_short8)(si_from_short(b)), 1)))); } @@ -325,13 +325,13 @@ static __inline qword si_dfa(qword a, qword b) static __inline qword si_andbi(qword a, signed char b) { - return ((qword)(vec_and((vec_char16)(a), + return ((qword)(vec_and((vec_char16)(a), vec_splat((vec_char16)(si_from_char(b)), 3)))); } static __inline qword si_andhi(qword a, signed short b) { - return ((qword)(vec_and((vec_short8)(a), + return ((qword)(vec_and((vec_short8)(a), vec_splat((vec_short8)(si_from_short(b)), 1)))); } @@ -373,8 +373,8 @@ static __inline qword si_andi(qword a, signed int b) static __inline qword si_fcmeq(qword a, qword b) { vec_float4 msb = (vec_float4)((vec_uint4){0x80000000, 0x80000000, 0x80000000, 0x80000000}); - - return ((qword)(vec_cmpeq(vec_andc((vec_float4)(a), msb), + + return ((qword)(vec_cmpeq(vec_andc((vec_float4)(a), msb), vec_andc((vec_float4)(b), msb)))); } @@ -408,11 +408,11 @@ static __inline qword si_dfcmeq(qword a, qword b) biteq = (vec_uint4) vec_cmpeq((vec_uint4)aabs,(vec_uint4)babs); biteq = vec_and(biteq,(vec_uint4)vec_slo((vec_uchar16)biteq,x.v)); - /* + /* B) Check if a is NaN, store in high word - + B1) If the high word is greater than max_exp (indicates a NaN) - B2) If the low word is greater than 0 + B2) If the low word is greater than 0 */ a_gt = (vec_uint4)vec_cmpgt(aabs,nan_mask); @@ -435,7 +435,7 @@ static __inline qword si_dfcmeq(qword a, qword b) static __inline qword si_fcmgt(qword a, qword b) { vec_float4 msb = (vec_float4)((vec_uint4){0x80000000, 0x80000000, 0x80000000, 0x80000000}); - + return ((qword)(vec_cmpgt(vec_andc((vec_float4)(a), msb), vec_andc((vec_float4)(b), msb)))); } @@ -454,7 +454,7 @@ static __inline qword si_dfcmgt(qword a, qword b) /* Shift 4 bytes */ x.i[3] = 4 << 3; - // absolute value of a,b + // absolute value of a,b vec_uint4 aabs = vec_and((vec_uint4)a, sign_mask); vec_uint4 babs = vec_and((vec_uint4)b, sign_mask); @@ -470,7 +470,7 @@ static __inline qword si_dfcmgt(qword a, qword b) b_nan = vec_or(b_nan, vec_and((vec_uint4)vec_slo((vec_uchar16)b_nan,x.v),b_inf)); b_nan = (vec_uint4)vec_perm((vec_uchar16)b_nan, (vec_uchar16)b_nan, splat_hi); - // A) Check if the exponents are different + // A) Check if the exponents are different vec_uint4 gt_hi = (vec_uint4)vec_cmpgt(aabs,babs); // B) Check if high word equal, and low word greater @@ -478,7 +478,7 @@ static __inline qword si_dfcmgt(qword a, qword b) vec_uint4 eq = (vec_uint4)vec_cmpeq(aabs, babs); vec_uint4 eqgt = vec_and(eq,vec_slo(gt_lo,x.v)); - // If either A or B is true, return true (unless NaNs detected) + // If either A or B is true, return true (unless NaNs detected) vec_uint4 r = vec_or(gt_hi, eqgt); // splat the high words of the comparison step @@ -513,19 +513,19 @@ static __inline qword si_fceq(qword a, qword b) static __inline qword si_ceqbi(qword a, signed char b) { - return ((qword)(vec_cmpeq((vec_char16)(a), + return ((qword)(vec_cmpeq((vec_char16)(a), vec_splat((vec_char16)(si_from_char(b)), 3)))); } static __inline qword si_ceqhi(qword a, signed short b) { - return ((qword)(vec_cmpeq((vec_short8)(a), + return ((qword)(vec_cmpeq((vec_short8)(a), vec_splat((vec_short8)(si_from_short(b)), 1)))); } static __inline qword si_ceqi(qword a, signed int b) { - return ((qword)(vec_cmpeq((vec_int4)(a), + return ((qword)(vec_cmpeq((vec_int4)(a), vec_splat((vec_int4)(si_from_int(b)), 0)))); } @@ -560,11 +560,11 @@ static __inline qword si_dfceq(qword a, qword b) aabs = vec_and((vec_uint4)a,sign_mask); babs = vec_and((vec_uint4)b,sign_mask); - /* + /* B) Check if a is NaN, store in high word - + B1) If the high word is greater than max_exp (indicates a NaN) - B2) If the low word is greater than 0 + B2) If the low word is greater than 0 */ a_gt = (vec_uint4)vec_cmpgt(aabs,nan_mask); @@ -583,7 +583,7 @@ static __inline qword si_dfceq(qword a, qword b) result = vec_andc(result, anan); /* Promote high words to 64 bits and return */ - return ((qword)(vec_perm((vec_uchar16)result, (vec_uchar16)result, hihi_promote))); + return ((qword)(vec_perm((vec_uchar16)result, (vec_uchar16)result, hihi_promote))); } @@ -639,7 +639,7 @@ static __inline qword si_dfcgt(qword a, qword b) /* Shift 4 bytes */ x.i[3] = 4 << 3; - // absolute value of a,b + // absolute value of a,b vec_uint4 aabs = vec_and((vec_uint4)a, sign_mask); vec_uint4 babs = vec_and((vec_uint4)b, sign_mask); @@ -680,7 +680,7 @@ static __inline qword si_dfcgt(qword a, qword b) // pick the one we want vec_int4 bval=(vec_int4)vec_sel((vec_uchar16)babs, (vec_uchar16)bneg, (vec_uchar16)bsel); - // A) Check if the exponents are different + // A) Check if the exponents are different vec_uint4 gt_hi = (vec_uint4)vec_cmpgt(aval,bval); // B) Check if high word equal, and low word greater @@ -688,7 +688,7 @@ static __inline qword si_dfcgt(qword a, qword b) vec_uint4 eq = (vec_uint4)vec_cmpeq(aval, bval); vec_uint4 eqgt = vec_and(eq,vec_slo(gt_lo,x.v)); - // If either A or B is true, return true (unless NaNs detected) + // If either A or B is true, return true (unless NaNs detected) vec_uint4 r = vec_or(gt_hi, eqgt); // splat the high words of the comparison step @@ -700,25 +700,25 @@ static __inline qword si_dfcgt(qword a, qword b) static __inline qword si_cgtbi(qword a, signed char b) { - return ((qword)(vec_cmpgt((vec_char16)(a), + return ((qword)(vec_cmpgt((vec_char16)(a), vec_splat((vec_char16)(si_from_char(b)), 3)))); } static __inline qword si_cgthi(qword a, signed short b) { - return ((qword)(vec_cmpgt((vec_short8)(a), + return ((qword)(vec_cmpgt((vec_short8)(a), vec_splat((vec_short8)(si_from_short(b)), 1)))); } static __inline qword si_cgti(qword a, signed int b) { - return ((qword)(vec_cmpgt((vec_int4)(a), + return ((qword)(vec_cmpgt((vec_int4)(a), vec_splat((vec_int4)(si_from_int(b)), 0)))); } static __inline qword si_clgtbi(qword a, unsigned char b) { - return ((qword)(vec_cmpgt((vec_uchar16)(a), + return ((qword)(vec_cmpgt((vec_uchar16)(a), vec_splat((vec_uchar16)(si_from_uchar(b)), 3)))); } @@ -730,7 +730,7 @@ static __inline qword si_clgthi(qword a, unsigned short b) static __inline qword si_clgti(qword a, unsigned int b) { - return ((qword)(vec_cmpgt((vec_uint4)(a), + return ((qword)(vec_cmpgt((vec_uint4)(a), vec_splat((vec_uint4)(si_from_uint(b)), 0)))); } @@ -742,7 +742,7 @@ static __inline qword si_dftsv(qword a, char b) vec_uint4 sign = (vec_uint4)vec_sra((vec_int4)(a), (vec_uint4)vec_splat(((vec_uint4)si_from_int(31)), 0)); sign = (vec_uint4)vec_perm((vec_uchar16)sign,(vec_uchar16)sign,splat_hi); vec_uint4 aabs = vec_and((vec_uint4)a,sign_mask); - + union { vec_uchar16 v; int i[4]; @@ -750,7 +750,7 @@ static __inline qword si_dftsv(qword a, char b) /* Shift 4 bytes */ x.i[3] = 4 << 3; - + /* Nan or +inf or -inf */ if (b & 0x70) { @@ -761,21 +761,21 @@ static __inline qword si_dftsv(qword a, char b) { vec_uint4 a_nan = (vec_uint4)vec_cmpgt(aabs, nan_mask); a_nan = vec_or(a_nan, vec_and((vec_uint4)vec_slo((vec_uchar16)a_nan,x.v),a_inf)); - a_nan = (vec_uint4)vec_perm((vec_uchar16)a_nan, (vec_uchar16)a_nan, splat_hi); + a_nan = (vec_uint4)vec_perm((vec_uchar16)a_nan, (vec_uchar16)a_nan, splat_hi); result = vec_or(result, a_nan); } - /* inf */ + /* inf */ if (b & 0x30) { a_inf = vec_and((vec_uint4)vec_slo((vec_uchar16)a_inf,x.v), a_inf); - a_inf = (vec_uint4)vec_perm((vec_uchar16)a_inf, (vec_uchar16)a_inf, splat_hi); + a_inf = (vec_uint4)vec_perm((vec_uchar16)a_inf, (vec_uchar16)a_inf, splat_hi); /* +inf */ if (b & 0x20) result = vec_or(vec_andc(a_inf, sign), result); /* -inf */ if (b & 0x10) result = vec_or(vec_and(a_inf, sign), result); - } + } } /* 0 or denorm */ if (b & 0xF) @@ -860,7 +860,7 @@ static __inline qword si_clz(qword a) cnt = vec_add(cnt, vec_and(tmp1, vec_cmpeq(cnt, eight))); cnt = vec_add(cnt, vec_and(tmp2, vec_cmpeq(cnt, sixteen))); cnt = vec_add(cnt, vec_and(tmp3, vec_cmpeq(cnt, twentyfour))); - + return (qword)((vec_sr((vec_uint4)(cnt), (vec_uint4)(twentyfour)))); } @@ -901,7 +901,7 @@ static __inline qword si_xsbh(qword a) vec_char16 av; av = (vec_char16)(a); - return ((qword)(vec_unpackh(vec_perm(av, av, ((vec_uchar16){1, 3, 5, 7, 9,11,13,15, + return ((qword)(vec_unpackh(vec_perm(av, av, ((vec_uchar16){1, 3, 5, 7, 9,11,13,15, 0, 0, 0, 0, 0, 0, 0, 0}))))); } @@ -910,9 +910,9 @@ static __inline qword si_xshw(qword a) vec_short8 av; av = (vec_short8)(a); - return ((qword)(vec_unpackh(vec_perm(av, av, ((vec_uchar16){2, 3, 6, 7, + return ((qword)(vec_unpackh(vec_perm(av, av, ((vec_uchar16){2, 3, 6, 7, 10,11,14,15, - 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0}))))); } @@ -921,10 +921,10 @@ static __inline qword si_xswd(qword a) vec_int4 av; av = (vec_int4)(a); - return ((qword)(vec_perm(av, vec_sra(av, ((vec_uint4){31,31,31,31})), - ((vec_uchar16){20, 21, 22, 23, - 4, 5, 6, 7, - 28, 29, 30, 31, + return ((qword)(vec_perm(av, vec_sra(av, ((vec_uint4){31,31,31,31})), + ((vec_uchar16){20, 21, 22, 23, + 4, 5, 6, 7, + 28, 29, 30, 31, 12, 13, 14, 15})))); } @@ -984,7 +984,7 @@ static __inline qword si_gb(qword a) } -/* Compare and halt +/* Compare and halt */ static __inline void si_heq(qword a, qword b) { @@ -1066,8 +1066,8 @@ static __inline void si_hlgti(qword a, unsigned int b) */ static __inline qword si_mpya(qword a, qword b, qword c) { - return ((qword)(vec_msum(vec_and((vec_short8)(a), - ((vec_short8){0, -1, 0, -1, 0, -1, 0, -1})), + return ((qword)(vec_msum(vec_and((vec_short8)(a), + ((vec_short8){0, -1, 0, -1, 0, -1, 0, -1})), (vec_short8)(b), (vec_int4)(c)))); } @@ -1116,7 +1116,7 @@ static __inline qword si_fsmh(qword a) in = (vec_uchar16)(a); mask = (vec_short8)(vec_splat(in, 3)); - return ((qword)(vec_sra(vec_sl(mask, ((vec_ushort8){0, 1, 2, 3, 4, 5, 6, 7})), + return ((qword)(vec_sra(vec_sl(mask, ((vec_ushort8){0, 1, 2, 3, 4, 5, 6, 7})), vec_splat_u16(15)))); } @@ -1155,7 +1155,7 @@ static __inline qword si_mpyhhau(qword a, qword b, qword c) */ static __inline qword si_fms(qword a, qword b, qword c) { - return ((qword)(vec_madd((vec_float4)(a), (vec_float4)(b), + return ((qword)(vec_madd((vec_float4)(a), (vec_float4)(b), vec_sub(((vec_float4){0.0f}), (vec_float4)(c))))); } @@ -1231,13 +1231,13 @@ static __inline qword si_mpyu(qword a, qword b) static __inline qword si_mpyi(qword a, short b) { - return ((qword)(vec_mulo((vec_short8)(a), + return ((qword)(vec_mulo((vec_short8)(a), vec_splat((vec_short8)(si_from_short(b)), 1)))); } static __inline qword si_mpyui(qword a, unsigned short b) { - return ((qword)(vec_mulo((vec_ushort8)(a), + return ((qword)(vec_mulo((vec_ushort8)(a), vec_splat((vec_ushort8)(si_from_ushort(b)), 1)))); } @@ -1313,19 +1313,19 @@ static __inline qword si_or(qword a, qword b) static __inline qword si_orbi(qword a, unsigned char b) { - return ((qword)(vec_or((vec_uchar16)(a), + return ((qword)(vec_or((vec_uchar16)(a), vec_splat((vec_uchar16)(si_from_uchar(b)), 3)))); } static __inline qword si_orhi(qword a, unsigned short b) { - return ((qword)(vec_or((vec_ushort8)(a), + return ((qword)(vec_or((vec_ushort8)(a), vec_splat((vec_ushort8)(si_from_ushort(b)), 1)))); } static __inline qword si_ori(qword a, unsigned int b) { - return ((qword)(vec_or((vec_uint4)(a), + return ((qword)(vec_or((vec_uint4)(a), vec_splat((vec_uint4)(si_from_uint(b)), 0)))); } @@ -1384,13 +1384,13 @@ static __inline qword si_rot(qword a, qword b) static __inline qword si_rothi(qword a, int b) { - return ((qword)(vec_rl((vec_ushort8)(a), + return ((qword)(vec_rl((vec_ushort8)(a), vec_splat((vec_ushort8)(si_from_int(b)), 1)))); } static __inline qword si_roti(qword a, int b) { - return ((qword)(vec_rl((vec_uint4)(a), + return ((qword)(vec_rl((vec_uint4)(a), vec_splat((vec_uint4)(si_from_int(b)), 0)))); } @@ -1526,7 +1526,7 @@ static __inline qword si_rotqbyi(qword a, int count) vec_uchar16 v; int i[4]; } left, right; - + count <<= 3; left.i[3] = count; right.i[3] = 0 - count; @@ -1536,7 +1536,7 @@ static __inline qword si_rotqbyi(qword a, int count) static __inline qword si_rotqby(qword a, qword count) { vec_uchar16 left, right; - + left = vec_sl(vec_splat((vec_uchar16)(count), 3), vec_splat_u8(3)); right = vec_sub(vec_splat_u8(0), left); return ((qword)(vec_or(vec_slo((vec_uchar16)(a), left), vec_sro((vec_uchar16)(a), right)))); @@ -1560,7 +1560,7 @@ static __inline qword si_rotqbii(qword a, int count) { vec_uchar16 x, y; vec_uchar16 result; - + x = vec_splat((vec_uchar16)(si_from_int(count & 7)), 3); y = (vec_uchar16)(vec_sr((vec_uint4)vec_sro((vec_uchar16)(a), ((vec_uchar16)((vec_uint4){0,0,0,120}))), (vec_uint4)vec_sub(vec_splat_u8(8), x))); @@ -1572,11 +1572,11 @@ static __inline qword si_rotqbi(qword a, qword count) { vec_uchar16 x, y; vec_uchar16 result; - + x = vec_and(vec_splat((vec_uchar16)(count), 3), vec_splat_u8(7)); y = (vec_uchar16)(vec_sr((vec_uint4)vec_sro((vec_uchar16)(a), ((vec_uchar16)((vec_uint4){0,0,0,120}))), (vec_uint4)vec_sub(vec_splat_u8(8), x))); - + result = vec_or(vec_sll((qword)(a), x), y); return ((qword)(result)); } @@ -1652,10 +1652,10 @@ static __inline qword si_shufb(qword a, qword b, qword pattern) { vec_uchar16 pat; - pat = vec_sel(((vec_uchar16){0, 1, 2, 3, 4, 5, 6, 7, 8, 9,10,11,12,13,14,15}), + pat = vec_sel(((vec_uchar16){0, 1, 2, 3, 4, 5, 6, 7, 8, 9,10,11,12,13,14,15}), vec_sr((vec_uchar16)(pattern), vec_splat_u8(3)), vec_sra((vec_uchar16)(pattern), vec_splat_u8(7))); - return ((qword)(vec_perm(vec_perm(a, b, pattern), + return ((qword)(vec_perm(vec_perm(a, b, pattern), ((vec_uchar16){0, 0, 0, 0, 0, 0, 0, 0, 0xFF, 0xFF, 0xFF, 0xFF, 0x80, 0x80, 0x80, 0x80}), pat))); @@ -1831,7 +1831,7 @@ static __inline qword si_sumb(qword a, qword b) { vec_uint4 zero = (vec_uint4){0}; vec_ushort8 sum_a, sum_b; - + sum_a = (vec_ushort8)vec_sum4s((vec_uchar16)(a), zero); sum_b = (vec_ushort8)vec_sum4s((vec_uchar16)(b), zero); @@ -1848,19 +1848,19 @@ static __inline qword si_xor(qword a, qword b) static __inline qword si_xorbi(qword a, unsigned char b) { - return ((qword)(vec_xor((vec_uchar16)(a), + return ((qword)(vec_xor((vec_uchar16)(a), vec_splat((vec_uchar16)(si_from_uchar(b)), 3)))); } static __inline qword si_xorhi(qword a, unsigned short b) { - return ((qword)(vec_xor((vec_ushort8)(a), + return ((qword)(vec_xor((vec_ushort8)(a), vec_splat((vec_ushort8)(si_from_ushort(b)), 1)))); } static __inline qword si_xori(qword a, unsigned int b) { - return ((qword)(vec_xor((vec_uint4)(a), + return ((qword)(vec_xor((vec_uint4)(a), vec_splat((vec_uint4)(si_from_uint(b)), 0)))); } @@ -2038,7 +2038,7 @@ static __inline void si_stqr(qword a, unsigned int imm) static __inline void si_stqx(qword a, qword b, qword c) { - vec_st((vec_uchar16)(a), + vec_st((vec_uchar16)(a), si_to_uint((qword)(vec_add((vec_uint4)(b), (vec_uint4)(c)))), (vector unsigned char *)(0)); } diff --git a/gcc/config/rs6000/spu2vmx.h b/gcc/config/rs6000/spu2vmx.h index b2573a9..7550dd9 100644 --- a/gcc/config/rs6000/spu2vmx.h +++ b/gcc/config/rs6000/spu2vmx.h @@ -3,7 +3,7 @@ This file is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free - Software Foundation; either version 3 of the License, or (at your option) + Software Foundation; either version 3 of the License, or (at your option) any later version. This file is distributed in the hope that it will be useful, but WITHOUT @@ -202,7 +202,7 @@ static __inline vec_int4 spu_and(vec_int4 a, signed int b) * ======= */ #define spu_avg(_a, _b) vec_avg(_a, _b) - + /* spu_bisled * spu_bisled_d @@ -1070,12 +1070,12 @@ static __inline vec_float4 spu_nand(vec_float4 a, vec_float4 b) static __inline vec_ullong2 spu_nand(vec_ullong2 a, vec_ullong2 b) { - return ((vec_ullong2)(si_nand((qword)(a), (qword)(b)))); + return ((vec_ullong2)(si_nand((qword)(a), (qword)(b)))); } static __inline vec_llong2 spu_nand(vec_llong2 a, vec_llong2 b) { - return ((vec_llong2)(si_nand((qword)(a), (qword)(b)))); + return ((vec_llong2)(si_nand((qword)(a), (qword)(b)))); } static __inline vec_double2 spu_nand(vec_double2 a, vec_double2 b) @@ -1653,7 +1653,7 @@ static __inline vec_double2 spu_rlmaskqwbytebc(vec_double2 a, int count) static __inline vec_uchar16 spu_rlqwbyte(vec_uchar16 a, int count) { return ((vec_uchar16)(si_rotqby((qword)(a), si_from_int(count)))); -} +} static __inline vec_char16 spu_rlqwbyte(vec_char16 a, int count) { @@ -1663,7 +1663,7 @@ static __inline vec_char16 spu_rlqwbyte(vec_char16 a, int count) static __inline vec_ushort8 spu_rlqwbyte(vec_ushort8 a, int count) { return ((vec_ushort8)(si_rotqby((qword)(a), si_from_int(count)))); -} +} static __inline vec_short8 spu_rlqwbyte(vec_short8 a, int count) { @@ -2304,7 +2304,7 @@ static __inline vec_int4 spu_subx(vec_int4 a, vec_int4 b, vec_int4 c) static __inline vec_ushort8 spu_sumb(vec_uchar16 a, vec_uchar16 b) { return ((vec_ushort8)(si_sumb((qword)(a), (qword)(b)))); -} +} /* spu_sync diff --git a/gcc/config/rs6000/vec_types.h b/gcc/config/rs6000/vec_types.h index 6d629cc..e24dc26 100644 --- a/gcc/config/rs6000/vec_types.h +++ b/gcc/config/rs6000/vec_types.h @@ -3,7 +3,7 @@ This file is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free - Software Foundation; either version 3 of the License, or (at your option) + Software Foundation; either version 3 of the License, or (at your option) any later version. This file is distributed in the hope that it will be useful, but WITHOUT @@ -20,7 +20,7 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see <http://www.gnu.org/licenses/>. */ -/* Single token vector data types for the PowerPC SIMD/Vector Multi-media +/* Single token vector data types for the PowerPC SIMD/Vector Multi-media eXtension */ #ifndef _VEC_TYPES_H_ diff --git a/gcc/config/rs6000/xcoff.h b/gcc/config/rs6000/xcoff.h index c22edd7..89bd462 100644 --- a/gcc/config/rs6000/xcoff.h +++ b/gcc/config/rs6000/xcoff.h @@ -28,11 +28,11 @@ #define OBJECT_FORMAT_COFF /* Define the magic numbers that we recognize as COFF. - + AIX 4.3 adds U803XTOCMAGIC (0757) for 64-bit objects and AIX V5 adds U64_TOCMAGIC (0767), but collect2.cc does not include files in the correct order to conditionally define the symbolic name in this macro. - + The AIX linker accepts import/export files as object files, so accept "#!" (0x2321) magic number. */ #define MY_ISCOFF(magic) \ @@ -233,7 +233,7 @@ /* This is how we tell the assembler that two symbols have the same value. */ #define SET_ASM_OP "\t.set " -/* This is how we tell the assembler to equate two values. +/* This is how we tell the assembler to equate two values. The semantic of AIX assembler's .set do not correspond to middle-end expectations. We output aliases as alternative symbols in the front of the definition via DECLARE_FUNCTION_NAME and DECLARE_OBJECT_NAME. diff --git a/gcc/config/rtems.h b/gcc/config/rtems.h index cd5db38..3eca9b5 100644 --- a/gcc/config/rtems.h +++ b/gcc/config/rtems.h @@ -1,4 +1,4 @@ -/* Configuration common to all targets running RTEMS. +/* Configuration common to all targets running RTEMS. Copyright (C) 2000-2024 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/rx/rx.cc b/gcc/config/rx/rx.cc index c84e139..00242e8 100644 --- a/gcc/config/rx/rx.cc +++ b/gcc/config/rx/rx.cc @@ -156,7 +156,7 @@ rx_legitimize_address (rtx x, if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 0)) == PLUS - && REG_P (XEXP (XEXP (x, 0), 0)) + && REG_P (XEXP (XEXP (x, 0), 0)) && REG_P (XEXP (x, 1))) return force_reg (SImode, x); @@ -232,7 +232,7 @@ rx_is_legitimate_address (machine_mode mode, rtx x, switch (GET_MODE_SIZE (mode)) { - default: + default: case 4: factor = 4; break; case 2: factor = 2; break; case 1: factor = 1; break; @@ -299,7 +299,7 @@ rx_is_restricted_memory_address (rtx mem, machine_mode mode) case PLUS: { rtx base, index; - + /* Only allow REG+INT addressing. */ base = XEXP (mem, 0); index = XEXP (mem, 1); @@ -688,7 +688,7 @@ rx_print_operand (FILE * file, rtx op, int letter) fprintf (file, "#"); /* Trickery to avoid problems with shifting 32 bits at a time. */ v = v >> 16; - v = v >> 16; + v = v >> 16; rx_print_integer (file, v); break; } @@ -1002,14 +1002,14 @@ rx_gen_move_template (rtx * operands, bool is_movu) { gcc_assert (GET_MODE (src) != DImode); gcc_assert (GET_MODE (src) != DFmode); - + src_template = "(%A1 - __pid_base)[%P1]"; } else if (MEM_P (src) && rx_small_data_operand (XEXP (src, 0))) { gcc_assert (GET_MODE (src) != DImode); gcc_assert (GET_MODE (src) != DFmode); - + src_template = "%%gp(%A1)[%G1]"; } else @@ -1019,7 +1019,7 @@ rx_gen_move_template (rtx * operands, bool is_movu) { gcc_assert (GET_MODE (dest) != DImode); gcc_assert (GET_MODE (dest) != DFmode); - + dst_template = "%%gp(%A0)[%G0]"; } else @@ -1151,7 +1151,7 @@ rx_function_value (const_tree ret_type, && ! VECTOR_MODE_P (mode) ) return gen_rtx_REG (SImode, FUNC_RETURN_REGNUM); - + return gen_rtx_REG (mode, FUNC_RETURN_REGNUM); } @@ -1279,7 +1279,7 @@ rx_conditional_register_usage (void) /* This is for fast interrupt handlers. Any register in the range r10 to r13 (inclusive) that is currently - marked as fixed is now a viable, call-used register. */ + marked as fixed is now a viable, call-used register. */ for (r = 10; r <= 13; r++) if (fixed_regs[r]) { @@ -1363,7 +1363,7 @@ rx_set_current_function (tree fndecl) current_is_fast_interrupt = fndecl ? is_fast_interrupt_func (fndecl) : false; - + if (prev_was_fast_interrupt != current_is_fast_interrupt) { use_fixed_regs = current_is_fast_interrupt; @@ -1790,7 +1790,7 @@ rx_expand_prologue (void) break; } } - + /* We have assumed that there are at least two registers pushed... */ gcc_assert (acc_high != 0); @@ -1939,7 +1939,7 @@ rx_emit_stack_popm (rtx * operands, bool is_popm) gcc_assert (CONST_INT_P (operands[0])); stack_adjust = INTVAL (operands[0]); - + gcc_assert (GET_CODE (operands[1]) == PARALLEL); last_reg = XVECLEN (operands[1], 0) - (is_popm ? 2 : 3); @@ -1987,13 +1987,13 @@ gen_rx_rtsd_vector (unsigned int adjust, unsigned int low, unsigned int high) return vector; } - + /* Generate a PARALLEL which will satisfy the rx_load_multiple_vector predicate. */ static rtx gen_rx_popm_vector (unsigned int low, unsigned int high) { - unsigned int i; + unsigned int i; unsigned int count = (high - low) + 2; rtx vector; @@ -2877,7 +2877,7 @@ rx_func_attr_inlinable (const_tree decl) { return ! is_fast_interrupt_func (decl) && ! is_interrupt_func (decl) - && ! is_naked_func (decl); + && ! is_naked_func (decl); } static bool @@ -2961,7 +2961,7 @@ rx_is_legitimate_constant (machine_mode mode ATTRIBUTE_UNUSED, rtx x) gcc_unreachable (); } break; - + case LABEL_REF: case SYMBOL_REF: return true; @@ -3001,7 +3001,7 @@ rx_address_cost (rtx addr, machine_mode mode ATTRIBUTE_UNUSED, && ((INTVAL (b) > 128) || INTVAL (b) < -127)) /* Try to discourage REG + <large OFF> when optimizing for size. */ return COSTS_N_INSNS (2); - + return COSTS_N_INSNS (1); } @@ -3421,7 +3421,7 @@ rx_adjust_insn_length (rtx_insn *insn, int current_length) zero = false; factor = 2; break; - + case CODE_FOR_plussi3_zero_extendqi: case CODE_FOR_andsi3_zero_extendqi: case CODE_FOR_iorsi3_zero_extendqi: @@ -3436,7 +3436,7 @@ rx_adjust_insn_length (rtx_insn *insn, int current_length) zero = true; factor = 1; break; - + case CODE_FOR_plussi3_sign_extendqi: case CODE_FOR_andsi3_sign_extendqi: case CODE_FOR_iorsi3_sign_extendqi: @@ -3451,7 +3451,7 @@ rx_adjust_insn_length (rtx_insn *insn, int current_length) zero = false; factor = 1; break; - } + } /* We are expecting: (SET (REG) (<OP> (REG) (<EXTEND> (MEM)))). */ extend = single_set (insn); @@ -3466,7 +3466,7 @@ rx_adjust_insn_length (rtx_insn *insn, int current_length) gcc_assert ((zero && (GET_CODE (extend) == ZERO_EXTEND)) || (! zero && (GET_CODE (extend) == SIGN_EXTEND))); - + mem = XEXP (extend, 0); gcc_checking_assert (MEM_P (mem)); if (REG_P (XEXP (mem, 0))) diff --git a/gcc/config/sh/elf.h b/gcc/config/sh/elf.h index 505c5d6..33a6906 100644 --- a/gcc/config/sh/elf.h +++ b/gcc/config/sh/elf.h @@ -33,7 +33,7 @@ along with GCC; see the file COPYING3. If not see #undef WCHAR_TYPE #define WCHAR_TYPE SH_ELF_WCHAR_TYPE - + #undef WCHAR_TYPE_SIZE #define WCHAR_TYPE_SIZE 32 diff --git a/gcc/config/sh/embed-elf.h b/gcc/config/sh/embed-elf.h index fef16de..844aff9 100644 --- a/gcc/config/sh/embed-elf.h +++ b/gcc/config/sh/embed-elf.h @@ -1,4 +1,4 @@ -/* Definitions of target machine for GNU compiler for Renesas / SuperH SH +/* Definitions of target machine for GNU compiler for Renesas / SuperH SH non-Linux embedded targets. Copyright (C) 2002-2024 Free Software Foundation, Inc. Contributed by J"orn Rennecke <joern.rennecke@superh.com> diff --git a/gcc/config/sh/netbsd-elf.h b/gcc/config/sh/netbsd-elf.h index f195710..b937155 100644 --- a/gcc/config/sh/netbsd-elf.h +++ b/gcc/config/sh/netbsd-elf.h @@ -62,7 +62,7 @@ along with GCC; see the file COPYING3. If not see /* Define because we use the label and we do not need them. */ #define NO_PROFILE_COUNTERS 1 - + #undef FUNCTION_PROFILER #define FUNCTION_PROFILER(STREAM,LABELNO) \ do \ diff --git a/gcc/config/sh/sh.cc b/gcc/config/sh/sh.cc index f69ede0..663c9908 100644 --- a/gcc/config/sh/sh.cc +++ b/gcc/config/sh/sh.cc @@ -377,7 +377,7 @@ TARGET_GNU_ATTRIBUTES (sh_attribute_table, #define TARGET_PRINT_OPERAND_PUNCT_VALID_P sh_print_operand_punct_valid_p #undef TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA #define TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA sh_asm_output_addr_const_extra - + #undef TARGET_ASM_FUNCTION_EPILOGUE #define TARGET_ASM_FUNCTION_EPILOGUE sh_output_function_epilogue @@ -814,7 +814,7 @@ register_sh_passes (void) PASS_POS_INSERT_BEFORE, "sched2", 1); } -/* Implement TARGET_OPTION_OVERRIDE macro. Validate and override +/* Implement TARGET_OPTION_OVERRIDE macro. Validate and override various options, and do some machine dependent initialization. */ static void sh_option_override (void) @@ -1012,7 +1012,7 @@ sh_override_options_after_change (void) fetched as a pair from a longword boundary. For size use 16 bit alignment to get more compact code. Aligning all jumps increases the code size, even if it might - result in slightly faster code. Thus, it is set to the smallest + result in slightly faster code. Thus, it is set to the smallest alignment possible if not specified by the user. */ if (flag_align_loops && !str_align_loops) str_align_loops = optimize_size ? "2" : "4"; @@ -2265,7 +2265,7 @@ sh_eval_treg_value (rtx op) t = 1; else return -1; - + return t ^ (cmpval == cmpop); } @@ -2543,7 +2543,7 @@ output_movedouble (rtx insn ATTRIBUTE_UNUSED, rtx operands[], We punt for now, since this is likely very rare. */ gcc_assert (!REG_P (XEXP (inside, 1))); break; - + case LABEL_REF: return "mov.l %1,%0" "\n" " mov.l %1+4,%T0"; @@ -3016,7 +3016,7 @@ bool sh_ashlsi_clobbers_t_reg_p (rtx shift_amount) { gcc_assert (CONST_INT_P (shift_amount)); - + const int shift_amount_i = INTVAL (shift_amount) & 31; /* Special case for shift count of 31: use and-rotl sequence. */ @@ -3036,7 +3036,7 @@ sh_lshrsi_clobbers_t_reg_p (rtx shift_amount) /* For right shifts the constant might be negative. */ const int shift_amount_i = std::abs (INTVAL (shift_amount)) & 31; - + /* Special case for shift count of 31: use shll-movt sequence. */ if (shift_amount_i == 31) return true; @@ -3046,7 +3046,7 @@ sh_lshrsi_clobbers_t_reg_p (rtx shift_amount) } /* Return true if it is potentially beneficial to use a dynamic shift - instruction (shad / shar) instead of a combination of 1/2/8/16 + instruction (shad / shar) instead of a combination of 1/2/8/16 shift instructions for the specified shift count. If dynamic shifts are not available, always return false. */ bool @@ -3240,7 +3240,7 @@ sh_rtx_costs (rtx x, machine_mode mode ATTRIBUTE_UNUSED, int outer_code, /* The lower-subreg pass decides whether to split multi-word regs into individual regs by looking at the cost for a SET of certain modes with the following patterns: - (set (reg) (reg)) + (set (reg) (reg)) (set (reg) (const_int 0)) On machines that support vector-move operations a multi-word move is the same cost as individual reg move. On SH there is no @@ -3336,8 +3336,8 @@ sh_rtx_costs (rtx x, machine_mode mode ATTRIBUTE_UNUSED, int outer_code, || GET_MODE (XEXP (x, 0)) == HImode)) { /* Handle SH2A's movu.b and movu.w insn. */ - *total = sh_address_cost (XEXP (XEXP (x, 0), 0), - GET_MODE (XEXP (x, 0)), + *total = sh_address_cost (XEXP (XEXP (x, 0), 0), + GET_MODE (XEXP (x, 0)), MEM_ADDR_SPACE (XEXP (x, 0)), speed) + COSTS_N_INSNS (1); return true; @@ -3352,7 +3352,7 @@ sh_rtx_costs (rtx x, machine_mode mode ATTRIBUTE_UNUSED, int outer_code, rtx xx = XVECEXP (x, 0, i); if (GET_CODE (xx) == SET && MEM_P (XEXP (xx, 0))) { - *total = sh_address_cost (XEXP (XEXP (xx, 0), 0), + *total = sh_address_cost (XEXP (XEXP (xx, 0), 0), GET_MODE (XEXP (xx, 0)), MEM_ADDR_SPACE (XEXP (xx, 0)), speed) + COSTS_N_INSNS (1); @@ -3581,7 +3581,7 @@ sh_max_mov_insn_displacement (machine_mode mode, bool consider_sh2a) const int mov_insn_sz = mov_insn_size (mode, consider_sh2a); const int mode_sz = GET_MODE_SIZE (mode); int r = 15 * mov_insn_sz * disp_scale; - + /* If the mov insn will be split into multiple loads/stores, the maximum possible displacement is a bit smaller. */ if (mode_sz > mov_insn_sz) @@ -3651,7 +3651,7 @@ sh_address_cost (rtx x, machine_mode mode, return 3; } - /* 'reg + reg' addressing. Account a slightly higher cost because of + /* 'reg + reg' addressing. Account a slightly higher cost because of increased pressure on R0. */ if (GET_CODE (x) == PLUS && ! CONSTANT_P (XEXP (x, 1))) return 3; @@ -5231,7 +5231,7 @@ find_barrier (int num_mova, rtx_insn *mova, rtx_insn *from) from = PREV_INSN (from); /* Don't emit a constant table int the middle of global pointer setting, - since that that would move the addressing base GOT into another table. + since that that would move the addressing base GOT into another table. We need the first mov instruction before the _GLOBAL_OFFSET_TABLE_ in the pool anyway, so just move up the whole constant pool. @@ -6065,7 +6065,7 @@ sh_reorg (void) later insn. */ /* ??? We shouldn't have to use FOUNDINSN here. - This dates back to when we used LOG_LINKS to find + This dates back to when we used LOG_LINKS to find the most recent insn which sets the register. */ if (foundinsn @@ -6765,7 +6765,7 @@ output_stack_adjust (int size, rtx reg, int epilogue_p, if (temp < 0) { rtx adj_reg, tmp_reg, mem; - + /* If we reached here, the most likely case is the (sibcall) epilogue. Put a special push/pop sequence for such case as the last resort. This looks lengthy but would not be problem @@ -6776,7 +6776,7 @@ output_stack_adjust (int size, rtx reg, int epilogue_p, r5 have been reserved as fixed registers or assigned as global registers, and they change during an interrupt. There are possible ways to handle this: - + - If we are adjusting the frame pointer (r14), we can do with a single temp register and an ordinary push / pop on the stack. @@ -7274,7 +7274,7 @@ sh_expand_epilogue (bool sibcall_p) /* For an ISR with RESBANK attribute assigned, don't pop PR register. */ if (TEST_HARD_REG_BIT (live_regs_mask, PR_REG) - && !sh_cfun_resbank_handler_p ()) + && !sh_cfun_resbank_handler_p ()) { if (!frame_pointer_needed) emit_insn (gen_blockage ()); @@ -7334,7 +7334,7 @@ sh_expand_epilogue (bool sibcall_p) fpscr_deferred = true; /* For an ISR with RESBANK attribute assigned, don't pop following registers, R0-R14, MACH, MACL and GBR. */ - else if (j != PR_REG && TEST_HARD_REG_BIT (live_regs_mask, j) + else if (j != PR_REG && TEST_HARD_REG_BIT (live_regs_mask, j) && ! (sh_cfun_resbank_handler_p () && ((j >= FIRST_GENERAL_REG && j < LAST_GENERAL_REG) @@ -9195,7 +9195,7 @@ legitimize_pic_address (rtx orig, machine_mode mode ATTRIBUTE_UNUSED, rtx reg) In some cases it is possible that a requested offset might seem unaligned or inappropriate for the mode size, like offset = 2 and mode size = 4. This is compensated by adjusting the base address so that the effective - address of the displacement move insn will be aligned. + address of the displacement move insn will be aligned. This is not the best possible way of rebasing the base address, as it does not look at other present displacement addressings around it. @@ -10411,7 +10411,7 @@ sh_vector_mode_supported_p (machine_mode mode ATTRIBUTE_UNUSED) bool sh_frame_pointer_required (void) { -/* If needed override this in other tm.h files to cope with various OS +/* If needed override this in other tm.h files to cope with various OS lossage requiring a frame pointer. */ if (SUBTARGET_FRAME_POINTER_REQUIRED) return true; @@ -11399,14 +11399,14 @@ sh_secondary_reload (bool in_p, rtx x, reg_class_t rclass_i, <= sh_max_mov_insn_displacement (mode, false)) return R0_REGS; - /* When reload is trying to address a QImode or HImode subreg on the stack, + /* When reload is trying to address a QImode or HImode subreg on the stack, force any subreg byte into R0_REGS, as this is going to become a displacement address. We could restrict this to SUBREG_BYTE (x) > 0, but if the actual reg is on the stack, the memref to it might already require a displacement and that has to be added to the final address. At this point we don't know the cumulative displacement so we assume the worst case. */ - if ((mode == QImode || mode == HImode) && rclass != R0_REGS + if ((mode == QImode || mode == HImode) && rclass != R0_REGS && GET_CODE (x) == SUBREG && true_regnum (x) == -1) return R0_REGS; @@ -11445,7 +11445,7 @@ sh_legitimize_address_displacement (rtx *offset1, rtx *offset2, *offset2 = adj.mov_disp; return true; } - + return false; } @@ -11595,7 +11595,7 @@ base_reg_disp::base_reg_disp (rtx br, disp_t d) : reg_ (br), disp_ (d) { } - + inline bool base_reg_disp::is_reg (void) const { @@ -11940,7 +11940,7 @@ sh_is_logical_t_store_expr (rtx op, rtx_insn* insn) op_is_t_count++; } } - + return op_is_t_count == 2; } diff --git a/gcc/config/sh/sh.h b/gcc/config/sh/sh.h index 53cad85..e0ac35c 100644 --- a/gcc/config/sh/sh.h +++ b/gcc/config/sh/sh.h @@ -293,7 +293,7 @@ extern int code_for_indirect_jump_scratch; #else #define IS_LITTLE_ENDIAN_OPTION "%{!mb:" #endif - + #if TARGET_CPU_DEFAULT & MASK_HARD_SH2A #define UNSUPPORTED_SH2A IS_LITTLE_ENDIAN_OPTION \ "%{m2a*|!m1:%{!m2*:%{!m3*:%{!m4*:%eSH2a does not support little-endian}}}}}" @@ -1490,7 +1490,7 @@ extern bool current_function_interrupt; return X << (Y & 31); else return X >> (-Y) & 31); - + The dynamic shift library routines in lib1funcs.S do not use the sign bit like the hardware dynamic shifts and truncate the shift count to 31. We define SHIFT_COUNT_TRUNCATED to 0 and express the implied shift count diff --git a/gcc/config/sh/sh_treg_combine.cc b/gcc/config/sh/sh_treg_combine.cc index a26fcfb..db40573 100644 --- a/gcc/config/sh/sh_treg_combine.cc +++ b/gcc/config/sh/sh_treg_combine.cc @@ -634,7 +634,7 @@ sh_treg_combine::sh_treg_combine (gcc::context* ctx, bool split_insns, m_split_insns (split_insns), m_ccreg (NULL_RTX) { - // Overwrite default name in pass_data base class. + // Overwrite default name in pass_data base class. this->name = name; } diff --git a/gcc/config/sh/vxworks.h b/gcc/config/sh/vxworks.h index 7a07ce9..15786b2 100644 --- a/gcc/config/sh/vxworks.h +++ b/gcc/config/sh/vxworks.h @@ -1,8 +1,8 @@ /* Definitions of target machine for GCC, - for SuperH with targeting the VXWorks run time environment. + for SuperH with targeting the VXWorks run time environment. Copyright (C) 2003-2024 Free Software Foundation, Inc. Contributed by CodeSourcery, LLC. - + This file is part of GCC. GCC is free software; you can redistribute it and/or modify diff --git a/gcc/config/sol2.cc b/gcc/config/sol2.cc index 4efa693..1cc525a 100644 --- a/gcc/config/sol2.cc +++ b/gcc/config/sol2.cc @@ -226,7 +226,7 @@ solaris_elf_asm_comdat_section (const char *name, unsigned int flags, tree decl) directive since Sun as treats undeclared sections as @progbits, which conflicts with .bss* sections which are @nobits. */ targetm.asm_out.named_section (section, flags & ~SECTION_LINKONCE, decl); - + /* Sun as separates declaration of a group section and of the group itself, using the .group directive and the #comdat flag. */ fprintf (asm_out_file, "\t.group\t%s," SECTION_NAME_FORMAT ",#comdat\n", diff --git a/gcc/config/sparc/freebsd.h b/gcc/config/sparc/freebsd.h index 5396b32..ee2a210 100644 --- a/gcc/config/sparc/freebsd.h +++ b/gcc/config/sparc/freebsd.h @@ -55,7 +55,7 @@ along with GCC; see the file COPYING3. If not see /************************[ Target stuff ]***********************************/ -/* Define the actual types of some ANSI-mandated types. +/* Define the actual types of some ANSI-mandated types. Needs to agree with <machine/ansi.h>. GCC defaults come from c-decl.cc, c-common.cc, and config/<arch>/<arch>.h. */ @@ -111,7 +111,7 @@ along with GCC; see the file COPYING3. If not see /* DWARF bits. */ -/* Follow Irix 6 and not the Dwarf2 draft in using 64-bit offsets. +/* Follow Irix 6 and not the Dwarf2 draft in using 64-bit offsets. Obviously the Dwarf2 folks havn't tried to actually build systems with their spec. On a 64-bit system, only 64-bit relocs become RELATIVE relocations. */ diff --git a/gcc/config/sparc/linux.h b/gcc/config/sparc/linux.h index 8cc5389..538845e 100644 --- a/gcc/config/sparc/linux.h +++ b/gcc/config/sparc/linux.h @@ -56,13 +56,13 @@ extern const char *host_detect_local_cpu (int argc, const char **argv); #undef SIZE_TYPE #define SIZE_TYPE "unsigned int" - + #undef PTRDIFF_TYPE #define PTRDIFF_TYPE "int" - + #undef WCHAR_TYPE #define WCHAR_TYPE "int" - + #undef WCHAR_TYPE_SIZE #define WCHAR_TYPE_SIZE 32 diff --git a/gcc/config/sparc/linux64.h b/gcc/config/sparc/linux64.h index 63543f9..dc6b408 100644 --- a/gcc/config/sparc/linux64.h +++ b/gcc/config/sparc/linux64.h @@ -254,7 +254,7 @@ do { \ /* DWARF bits. */ -/* Follow Irix 6 and not the Dwarf2 draft in using 64-bit offsets. +/* Follow Irix 6 and not the Dwarf2 draft in using 64-bit offsets. Obviously the Dwarf2 folks haven't tried to actually build systems with their spec. On a 64-bit system, only 64-bit relocs become RELATIVE relocations. */ diff --git a/gcc/config/sparc/sparc-protos.h b/gcc/config/sparc/sparc-protos.h index 399458a..bc30608 100644 --- a/gcc/config/sparc/sparc-protos.h +++ b/gcc/config/sparc/sparc-protos.h @@ -99,7 +99,7 @@ extern int register_ok_for_ldd (rtx); extern int memory_ok_for_ldd (rtx); extern int v9_regcmp_p (enum rtx_code); /* Function used for V8+ code generation. Returns 1 if the high - 32 bits of REG are 0 before INSN. */ + 32 bits of REG are 0 before INSN. */ extern int sparc_check_64 (rtx, rtx_insn *); extern rtx gen_df_reg (rtx, int); extern void sparc_expand_compare_and_swap (rtx op[]); diff --git a/gcc/config/sparc/sparc.cc b/gcc/config/sparc/sparc.cc index 353837d..3935a97 100644 --- a/gcc/config/sparc/sparc.cc +++ b/gcc/config/sparc/sparc.cc @@ -2170,7 +2170,7 @@ sparc_option_override (void) || sparc_cpu == PROCESSOR_M8) ? 128 : (sparc_cpu == PROCESSOR_NIAGARA7 ? 256 : 512))); - + /* Disable save slot sharing for call-clobbered registers by default. The IRA sharing algorithm works on single registers only and this @@ -10144,7 +10144,7 @@ supersparc_adjust_cost (rtx_insn *insn, int dep_type, rtx_insn *dep_insn, if (insn_type == TYPE_IALU || insn_type == TYPE_SHIFT) return 0; } - + return cost; } @@ -10386,7 +10386,7 @@ sparc_branch_cost (bool speed_p, bool predictable_p) return cost; } } - + static int set_extends (rtx_insn *insn) { @@ -11008,7 +11008,7 @@ enum sparc_builtins SPARC_BUILTIN_FPCMPUR16SHL, SPARC_BUILTIN_FPCMPUR32SHL, SPARC_BUILTIN_LAST_FPCMPSHL = SPARC_BUILTIN_FPCMPUR32SHL, - + SPARC_BUILTIN_MAX }; @@ -11555,7 +11555,7 @@ sparc_vis_init_builtins (void) def_builtin_const ("__builtin_vis_fpcmpugt32", CODE_FOR_fpcmpugt32si_vis, SPARC_BUILTIN_FPCMPUGT32, di_ftype_v2si_v2si); } - + def_builtin_const ("__builtin_vis_fpmax8", CODE_FOR_maxv8qi3, SPARC_BUILTIN_FPMAX8, v8qi_ftype_v8qi_v8qi); def_builtin_const ("__builtin_vis_fpmax16", CODE_FOR_maxv4hi3, @@ -11610,7 +11610,7 @@ sparc_vis_init_builtins (void) tree di_ftype_v2si_v2si_si = build_function_type_list (intDI_type_node, v2si, v2si, intSI_type_node, 0); - + def_builtin_const ("__builtin_vis_fpcmple8shl", CODE_FOR_fpcmple8dishl, SPARC_BUILTIN_FPCMPLE8SHL, di_ftype_v8qi_v8qi_si); def_builtin_const ("__builtin_vis_fpcmpgt8shl", CODE_FOR_fpcmpgt8dishl, @@ -11680,7 +11680,7 @@ sparc_vis_init_builtins (void) tree si_ftype_v2si_v2si_si = build_function_type_list (intSI_type_node, v2si, v2si, intSI_type_node, 0); - + def_builtin_const ("__builtin_vis_fpcmple8shl", CODE_FOR_fpcmple8sishl, SPARC_BUILTIN_FPCMPLE8SHL, si_ftype_v8qi_v8qi_si); def_builtin_const ("__builtin_vis_fpcmpgt8shl", CODE_FOR_fpcmpgt8sishl, @@ -13022,7 +13022,7 @@ sparc_expand_vec_perm_bmask (machine_mode vmode, rtx sel) t_1 = force_reg (SImode, GEN_INT (0x01010101)); /* sel = { A*2, A*2+1, B*2, B*2+1, ... } */ break; - + case E_V8QImode: /* input = xAxBxCxDxExFxGxH */ sel = expand_simple_binop (DImode, AND, sel, diff --git a/gcc/config/sparc/sparc.h b/gcc/config/sparc/sparc.h index 8612832..deb6c1c 100644 --- a/gcc/config/sparc/sparc.h +++ b/gcc/config/sparc/sparc.h @@ -429,7 +429,7 @@ along with GCC; see the file COPYING3. If not see (MASK_FPU + MASK_HARD_QUAD + MASK_VIS + MASK_VIS2 + MASK_VIS3 \ + MASK_VIS4 + MASK_CBCOND + MASK_FMAF + MASK_FSMULD \ + MASK_POPC + MASK_SUBXC) - + /* TARGET_HARD_MUL: Use 32-bit hardware multiply instructions but not %y. */ #define TARGET_HARD_MUL \ (TARGET_SPARCLITE || TARGET_SPARCLET \ diff --git a/gcc/config/sparc/sysv4.h b/gcc/config/sparc/sysv4.h index 391d9b1..fb43e3f 100644 --- a/gcc/config/sparc/sysv4.h +++ b/gcc/config/sparc/sysv4.h @@ -90,7 +90,7 @@ do { ASM_OUTPUT_ALIGN ((FILE), Pmode == SImode ? 2 : 3); \ #define FINI_SECTION_ASM_OP "\t.section\t\".fini\"" /* Define the pseudo-ops used to switch to the .ctors and .dtors sections. - + Note that we want to give these sections the SHF_WRITE attribute because these sections will actually contain data (i.e. tables of addresses of functions in the current root executable or shared library @@ -103,7 +103,7 @@ do { ASM_OUTPUT_ALIGN ((FILE), Pmode == SImode ? 2 : 3); \ use the `-z text' option when building a shared library, you will get errors unless the .ctors and .dtors sections are marked as writable via the SHF_WRITE attribute.) */ - + #undef CTORS_SECTION_ASM_OP #define CTORS_SECTION_ASM_OP "\t.section\t\".ctors\",#alloc,#write" #undef DTORS_SECTION_ASM_OP diff --git a/gcc/config/stormy16/stormy16-protos.h b/gcc/config/stormy16/stormy16-protos.h index 1d3a8cf..4396616 100644 --- a/gcc/config/stormy16/stormy16-protos.h +++ b/gcc/config/stormy16/stormy16-protos.h @@ -55,13 +55,13 @@ extern void xstormy16_expand_andqi3 (rtx *); extern void xstormy16_split_cbranch (machine_mode, rtx, rtx, rtx); extern int short_memory_operand (rtx, machine_mode); extern bool nonimmediate_nonstack_operand (rtx, machine_mode); -extern enum reg_class xstormy16_secondary_reload_class +extern enum reg_class xstormy16_secondary_reload_class (enum reg_class, machine_mode, rtx); extern void xstormy16_split_move (machine_mode, rtx, rtx); extern void xstormy16_expand_move (machine_mode, rtx, rtx); -extern void xstormy16_expand_arith (machine_mode, enum rtx_code, +extern void xstormy16_expand_arith (machine_mode, enum rtx_code, rtx, rtx, rtx); -extern const char * xstormy16_output_shift (machine_mode, enum rtx_code, +extern const char * xstormy16_output_shift (machine_mode, enum rtx_code, rtx, rtx, rtx); extern bool xstormy16_below100_symbol (rtx, machine_mode); extern bool xstormy16_splittable_below100_operand (rtx, machine_mode); diff --git a/gcc/config/stormy16/stormy16.cc b/gcc/config/stormy16/stormy16.cc index 1016913..d04af9a 100644 --- a/gcc/config/stormy16/stormy16.cc +++ b/gcc/config/stormy16/stormy16.cc @@ -150,7 +150,7 @@ xstormy16_rtx_costs (rtx x, machine_mode mode, *total = COSTS_N_INSNS (speed_p ? 18 + 5 : 6); else if (mode == SImode) *total = COSTS_N_INSNS (speed_p ? 3 * 18 + 14 : 17); - else + else *total = COSTS_N_INSNS (speed_p ? 18 + 3 : 4); return false; diff --git a/gcc/config/stormy16/stormy16.h b/gcc/config/stormy16/stormy16.h index 3d5e21d..dbcb897 100644 --- a/gcc/config/stormy16/stormy16.h +++ b/gcc/config/stormy16/stormy16.h @@ -292,7 +292,7 @@ enum reg_class /* This declaration must be present, but it can be an abort if profiling is not implemented. */ - + #define FUNCTION_PROFILER(FILE, LABELNO) xstormy16_function_profiler () diff --git a/gcc/config/v850/v850-c.cc b/gcc/config/v850/v850-c.cc index bafd6d9..b808710 100644 --- a/gcc/config/v850/v850-c.cc +++ b/gcc/config/v850/v850-c.cc @@ -90,7 +90,7 @@ static void mark_current_function_as_interrupt (void) { tree name; - + if (current_function_decl == NULL_TREE) { warning (0, "cannot set interrupt attribute: no current function"); @@ -104,7 +104,7 @@ mark_current_function_as_interrupt (void) warning (0, "cannot set interrupt attribute: no such identifier"); return; } - + decl_attributes (¤t_function_decl, tree_cons (name, NULL_TREE, NULL_TREE), 0); } @@ -125,9 +125,9 @@ ghs_pragma_section (cpp_reader * pfile ATTRIBUTE_UNUSED) tree sect_ident; const char *sect, *alias; enum GHS_section_kind kind; - + type = pragma_lex (&x); - + if (type == CPP_EOF && !repeat) goto reset; else if (type == CPP_NAME) @@ -138,20 +138,20 @@ ghs_pragma_section (cpp_reader * pfile ATTRIBUTE_UNUSED) else goto bad; repeat = 0; - + if (pragma_lex (&x) != CPP_EQ) goto bad; if (pragma_lex (&x) != CPP_NAME) goto bad; - + alias = IDENTIFIER_POINTER (x); - + type = pragma_lex (&x); if (type == CPP_COMMA) repeat = 1; else if (type != CPP_EOF) warning (OPT_Wpragmas, "junk at end of %<#pragma%> ghs section"); - + if (streq (sect, "data")) kind = GHS_SECTION_KIND_DATA; else if (streq (sect, "text")) kind = GHS_SECTION_KIND_TEXT; else if (streq (sect, "rodata")) kind = GHS_SECTION_KIND_RODATA; @@ -170,7 +170,7 @@ ghs_pragma_section (cpp_reader * pfile ATTRIBUTE_UNUSED) warning (0, "unrecognized section name %qE", sect_ident); return; } - + if (streq (alias, "default")) GHS_current_section_names [kind] = NULL; else @@ -188,7 +188,7 @@ ghs_pragma_section (cpp_reader * pfile ATTRIBUTE_UNUSED) /* #pragma ghs section \n: Reset all section names back to their defaults. */ { int i; - + for (i = COUNT_OF_GHS_SECTION_KINDS; i--;) GHS_current_section_names [i] = NULL; } @@ -198,10 +198,10 @@ void ghs_pragma_interrupt (cpp_reader * pfile ATTRIBUTE_UNUSED) { tree x; - + if (pragma_lex (&x) != CPP_EOF) warning (OPT_Wpragmas, "junk at end of %<#pragma%> ghs interrupt"); - + mark_current_function_as_interrupt (); } @@ -209,10 +209,10 @@ void ghs_pragma_starttda (cpp_reader * pfile ATTRIBUTE_UNUSED) { tree x; - + if (pragma_lex (&x) != CPP_EOF) warning (OPT_Wpragmas, "junk at end of %<#pragma%> ghs starttda"); - + push_data_area (DATA_AREA_TDA); } @@ -220,10 +220,10 @@ void ghs_pragma_startsda (cpp_reader * pfile ATTRIBUTE_UNUSED) { tree x; - + if (pragma_lex (&x) != CPP_EOF) warning (OPT_Wpragmas, "junk at end of %<#pragma%> ghs startsda"); - + push_data_area (DATA_AREA_SDA); } @@ -231,10 +231,10 @@ void ghs_pragma_startzda (cpp_reader * pfile ATTRIBUTE_UNUSED) { tree x; - + if (pragma_lex (&x) != CPP_EOF) warning (OPT_Wpragmas, "junk at end of %<#pragma%> ghs startzda"); - + push_data_area (DATA_AREA_ZDA); } @@ -242,10 +242,10 @@ void ghs_pragma_endtda (cpp_reader * pfile ATTRIBUTE_UNUSED) { tree x; - + if (pragma_lex (&x) != CPP_EOF) warning (OPT_Wpragmas, "junk at end of %<#pragma%> ghs endtda"); - + pop_data_area (DATA_AREA_TDA); } @@ -253,10 +253,10 @@ void ghs_pragma_endsda (cpp_reader * pfile ATTRIBUTE_UNUSED) { tree x; - + if (pragma_lex (&x) != CPP_EOF) warning (OPT_Wpragmas, "junk at end of %<#pragma%> ghs endsda"); - + pop_data_area (DATA_AREA_SDA); } @@ -264,9 +264,9 @@ void ghs_pragma_endzda (cpp_reader * pfile ATTRIBUTE_UNUSED) { tree x; - + if (pragma_lex (&x) != CPP_EOF) warning (OPT_Wpragmas, "junk at end of %<#pragma%> ghs endzda"); - + pop_data_area (DATA_AREA_ZDA); } diff --git a/gcc/config/v850/v850.cc b/gcc/config/v850/v850.cc index 35fa6b5..b39343c 100644 --- a/gcc/config/v850/v850.cc +++ b/gcc/config/v850/v850.cc @@ -60,7 +60,7 @@ static void v850_print_operand_address (FILE *, machine_mode, rtx); const char * GHS_default_section_names [(int) COUNT_OF_GHS_SECTION_KINDS]; const char * GHS_current_section_names [(int) COUNT_OF_GHS_SECTION_KINDS]; -/* Track the current data area set by the data area pragma (which +/* Track the current data area set by the data area pragma (which can be nested). Tested by check_default_data_area. */ data_area_stack_element * data_area_stack = NULL; @@ -193,7 +193,7 @@ v850_arg_partial_bytes (cumulative_args_t cum_v, const function_arg_info &arg) size = arg.promoted_size_in_bytes (); if (size < 1) size = 1; - + if (!TARGET_GCC_ABI) align = UNITS_PER_WORD; else if (arg.type) @@ -449,7 +449,7 @@ v850_print_operand (FILE * file, rtx x, int code) case CONST_INT: fprintf (file, "%d", (INTVAL (x) >= 0) ? 0 : -1); break; - + case CONST_DOUBLE: const_double_split (x, &high, &low); fprintf (file, "%ld", (long) high); @@ -465,7 +465,7 @@ v850_print_operand (FILE * file, rtx x, int code) case CONST_INT: fprintf (file, "%ld", (long) INTVAL (x)); break; - + case CONST_DOUBLE: const_double_split (x, &high, &low); fprintf (file, "%ld", (long) low); @@ -483,12 +483,12 @@ v850_print_operand (FILE * file, rtx x, int code) break; case 'O': gcc_assert (special_symbolref_operand (x, VOIDmode)); - + if (GET_CODE (x) == CONST) x = XEXP (XEXP (x, 0), 0); else gcc_assert (GET_CODE (x) == SYMBOL_REF); - + if (SYMBOL_REF_ZDA_P (x)) fprintf (file, "zdaoff"); else if (SYMBOL_REF_SDA_P (x)) @@ -504,12 +504,12 @@ v850_print_operand (FILE * file, rtx x, int code) break; case 'Q': gcc_assert (special_symbolref_operand (x, VOIDmode)); - + if (GET_CODE (x) == CONST) x = XEXP (XEXP (x, 0), 0); else gcc_assert (GET_CODE (x) == SYMBOL_REF); - + if (SYMBOL_REF_ZDA_P (x)) fprintf (file, "r0"); else if (SYMBOL_REF_SDA_P (x)) @@ -534,7 +534,7 @@ v850_print_operand (FILE * file, rtx x, int code) fprintf (file, "[r0]"); } break; - + case CONST_INT: { unsigned HOST_WIDE_INT v = INTVAL (x); @@ -542,7 +542,7 @@ v850_print_operand (FILE * file, rtx x, int code) /* Trickery to avoid problems with shifting 32-bits at a time on a 32-bit host. */ v = v >> 16; - v = v >> 16; + v = v >> 16; fprintf (file, HOST_WIDE_INT_PRINT_HEX, v); break; } @@ -622,7 +622,7 @@ v850_print_operand (FILE * file, rtx x, int code) case CONST_DOUBLE: fprintf (file, HOST_WIDE_INT_PRINT_HEX, CONST_DOUBLE_LOW (x)); break; - + case CONST_INT: case SYMBOL_REF: case CONST: @@ -756,7 +756,7 @@ v850_print_operand_punct_valid_p (unsigned char code) output_addr_const will normally barf at this, but it is OK to omit the truncate and just emit the difference of the two labels. The .hword directive will automatically handle the truncation for us. - + Returns true if rtx was handled, false otherwise. */ static bool @@ -852,7 +852,7 @@ output_move_single (rtx * operands) || GET_CODE (src) == SYMBOL_REF || GET_CODE (src) == CONST) { - if (TARGET_V850E_UP) + if (TARGET_V850E_UP) return "mov hilo(%1),%0"; else return "movhi hi(%1),%.,%0\n\tmovea lo(%1),%0,%0"; @@ -1018,7 +1018,7 @@ ep_memory_offset (machine_mode mode, int unsignedp ATTRIBUTE_UNUSED) case E_SFmode: max_offset = (1 << 8); break; - + default: break; } @@ -1472,7 +1472,7 @@ compute_register_save_size (long * p_reg_saved) registers that need to be saved. To detect this we note that the helper functions always push at least register r29 (provided that the function is not an interrupt handler). */ - + if (TARGET_PROLOG_FUNCTION && (i == 2 || ((i >= 20) && (i < 30)))) { @@ -1510,7 +1510,7 @@ compute_register_save_size (long * p_reg_saved) } } } - + if (p_reg_saved) *p_reg_saved = reg_saved; @@ -1640,7 +1640,7 @@ expand_prologue (void) emit_insn (gen_save_interrupt ()); actual_fsize -= INTERRUPT_FIXED_SAVE_SIZE; - + if (((1L << LINK_POINTER_REGNUM) & reg_saved) != 0) actual_fsize -= INTERRUPT_ALL_SAVE_SIZE; @@ -1724,7 +1724,7 @@ expand_prologue (void) rtx insn = emit_insn (save_all); INSN_CODE (insn) = code; actual_fsize -= alloc_stack; - + } else save_all = NULL_RTX; @@ -1753,13 +1753,13 @@ expand_prologue (void) init_stack_alloc = compute_register_save_size (NULL); else init_stack_alloc = actual_fsize; - + /* Save registers at the beginning of the stack frame. */ offset = init_stack_alloc - 4; - + if (init_stack_alloc) increment_stack (- (signed) init_stack_alloc, true); - + /* Save the return pointer first. */ if (num_save > 0 && REGNO (save_regs[num_save-1]) == LINK_POINTER_REGNUM) { @@ -1770,7 +1770,7 @@ expand_prologue (void) save_regs[--num_save])); offset -= 4; } - + for (i = 0; i < num_save; i++) { F (emit_move_insn (gen_rtx_MEM (SImode, @@ -1865,7 +1865,7 @@ expand_epilogue (void) } code = recog (restore_all, NULL, NULL); - + if (code >= 0) { rtx insn; @@ -1967,10 +1967,10 @@ v850_get_data_area (tree decl) { if (lookup_attribute ("sda", DECL_ATTRIBUTES (decl)) != NULL_TREE) return DATA_AREA_SDA; - + if (lookup_attribute ("tda", DECL_ATTRIBUTES (decl)) != NULL_TREE) return DATA_AREA_TDA; - + if (lookup_attribute ("zda", DECL_ATTRIBUTES (decl)) != NULL_TREE) return DATA_AREA_ZDA; @@ -1983,7 +1983,7 @@ static void v850_set_data_area (tree decl, v850_data_area data_area) { tree name; - + switch (data_area) { case DATA_AREA_SDA: name = get_identifier ("sda"); break; @@ -2036,7 +2036,7 @@ v850_handle_data_area_attribute (tree *node, tree name, data_area = DATA_AREA_ZDA; else gcc_unreachable (); - + switch (TREE_CODE (decl)) { case VAR_DECL: @@ -2059,7 +2059,7 @@ v850_handle_data_area_attribute (tree *node, tree name, *no_add_attrs = true; } break; - + default: break; } @@ -2113,7 +2113,7 @@ v850_encode_data_area (tree decl, rtx symbol) if (DECL_SECTION_NAME (decl)) { const char *name = DECL_SECTION_NAME (decl); - + if (streq (name, ".zdata") || streq (name, ".zbss")) v850_set_data_area (decl, DATA_AREA_ZDA); @@ -2140,7 +2140,7 @@ v850_encode_data_area (tree decl, rtx symbol) else if (size <= small_memory_max [(int) SMALL_MEMORY_ZDA]) v850_set_data_area (decl, DATA_AREA_ZDA); } - + if (v850_get_data_area (decl) == DATA_AREA_NORMAL) return; } @@ -2182,7 +2182,7 @@ construct_restore_jr (rtx op) unsigned long int last; int i; static char buff [256]; /* XXX */ - + if (count <= 2) { error ("bogus JR construction: %d", count); @@ -2194,7 +2194,7 @@ construct_restore_jr (rtx op) gcc_assert (GET_CODE (XVECEXP (op, 0, 1)) == SET); gcc_assert (GET_CODE (SET_SRC (XVECEXP (op, 0, 1))) == PLUS); gcc_assert (GET_CODE (XEXP (SET_SRC (XVECEXP (op, 0, 1)), 1)) == CONST_INT); - + stack_bytes = INTVAL (XEXP (SET_SRC (XVECEXP (op, 0, 1)), 1)); /* Each pop will remove 4 bytes from the stack.... */ @@ -2212,12 +2212,12 @@ construct_restore_jr (rtx op) for (i = 2; i < count; i++) { rtx vector_element = XVECEXP (op, 0, i); - + gcc_assert (GET_CODE (vector_element) == SET); gcc_assert (GET_CODE (SET_DEST (vector_element)) == REG); gcc_assert (register_is_ok_for_epilogue (SET_DEST (vector_element), SImode)); - + mask |= 1 << REGNO (SET_DEST (vector_element)); } @@ -2239,7 +2239,7 @@ construct_restore_jr (rtx op) { gcc_assert (!stack_bytes); gcc_assert (mask & (1 << 29)); - + last = 29; } @@ -2247,16 +2247,16 @@ construct_restore_jr (rtx op) We ignore this here, and generate a JR anyway. We will be popping more registers than is strictly necessary, but it does save code space. */ - + if (TARGET_LONG_CALLS) { char name[40]; - + if (first == last) sprintf (name, "__return_%s", reg_names [first]); else sprintf (name, "__return_%s_%s", reg_names [first], reg_names [last]); - + sprintf (buff, "movhi hi(%s), r0, r6\n\tmovea lo(%s), r6, r6\n\tjmp r6", name, name); } @@ -2267,7 +2267,7 @@ construct_restore_jr (rtx op) else sprintf (buff, "jr __return_%s_%s", reg_names [first], reg_names [last]); } - + return buff; } @@ -2287,8 +2287,8 @@ construct_save_jarl (rtx op) unsigned long int last; int i; static char buff [255]; /* XXX */ - - if (count <= (TARGET_LONG_CALLS ? 3 : 2)) + + if (count <= (TARGET_LONG_CALLS ? 3 : 2)) { error ("bogus JARL construction: %d", count); return NULL; @@ -2299,7 +2299,7 @@ construct_save_jarl (rtx op) gcc_assert (GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) == PLUS); gcc_assert (GET_CODE (XEXP (SET_SRC (XVECEXP (op, 0, 0)), 0)) == REG); gcc_assert (GET_CODE (XEXP (SET_SRC (XVECEXP (op, 0, 0)), 1)) == CONST_INT); - + /* Work out how many bytes to push onto the stack after storing the registers. */ stack_bytes = INTVAL (XEXP (SET_SRC (XVECEXP (op, 0, 0)), 1)); @@ -2319,16 +2319,16 @@ construct_save_jarl (rtx op) for (i = 1; i < count - (TARGET_LONG_CALLS ? 3 : 2); i++) { rtx vector_element = XVECEXP (op, 0, i); - + gcc_assert (GET_CODE (vector_element) == SET); gcc_assert (GET_CODE (SET_SRC (vector_element)) == REG); gcc_assert (register_is_ok_for_epilogue (SET_SRC (vector_element), SImode)); - + mask |= 1 << REGNO (SET_SRC (vector_element)); } - /* Scan for the first register to push. */ + /* Scan for the first register to push. */ for (first = 0; first < 32; first++) { if (mask & (1 << first)) @@ -2346,7 +2346,7 @@ construct_save_jarl (rtx op) { gcc_assert (!stack_bytes); gcc_assert (mask & (1 << 29)); - + last = 29; } @@ -2354,16 +2354,16 @@ construct_save_jarl (rtx op) We ignore this here, and generate a JARL anyway. We will be pushing more registers than is strictly necessary, but it does save code space. */ - + if (TARGET_LONG_CALLS) { char name[40]; - + if (first == last) sprintf (name, "__save_%s", reg_names [first]); else sprintf (name, "__save_%s_%s", reg_names [first], reg_names [last]); - + if (TARGET_V850E3V5_UP) sprintf (buff, "mov hilo(%s), r11\n\tjarl [r11], r10", name); else @@ -2404,12 +2404,12 @@ v850_output_aligned_bss (FILE * file, case DATA_AREA_TDA: switch_to_section (tdata_section); break; - + default: switch_to_section (bss_section); break; } - + ASM_OUTPUT_ALIGN (file, floor_log2 (align / BITS_PER_UNIT)); #ifdef ASM_DECLARE_OBJECT_NAME last_assemble_variable_decl = decl; @@ -2448,13 +2448,13 @@ v850_output_common (FILE * file, case DATA_AREA_TDA: fprintf (file, "%s", TCOMMON_ASM_OP); break; - + default: fprintf (file, "%s", COMMON_ASM_OP); break; } } - + assemble_name (file, name); fprintf (file, ",%u,%u\n", size, align / BITS_PER_UNIT); } @@ -2470,7 +2470,7 @@ v850_output_local (FILE * file, fprintf (file, "%s", LOCAL_ASM_OP); assemble_name (file, name); fprintf (file, "\n"); - + ASM_OUTPUT_ALIGNED_DECL_COMMON (file, decl, name, size, align); } @@ -2488,7 +2488,7 @@ v850_insert_attributes (tree decl, tree * attr_ptr ATTRIBUTE_UNUSED ) /* Initialize the default names of the v850 specific sections, if this has not been done before. */ - + if (GHS_default_section_names [(int) GHS_SECTION_KIND_SDATA] == NULL) { GHS_default_section_names [(int) GHS_SECTION_KIND_SDATA] @@ -2499,14 +2499,14 @@ v850_insert_attributes (tree decl, tree * attr_ptr ATTRIBUTE_UNUSED ) GHS_default_section_names [(int) GHS_SECTION_KIND_TDATA] = ".tdata"; - + GHS_default_section_names [(int) GHS_SECTION_KIND_ZDATA] = ".zdata"; GHS_default_section_names [(int) GHS_SECTION_KIND_ROZDATA] = ".rozdata"; } - + if (current_function_decl == NULL_TREE && (VAR_P (decl) || TREE_CODE (decl) == CONST_DECL @@ -2526,23 +2526,23 @@ v850_insert_attributes (tree decl, tree * attr_ptr ATTRIBUTE_UNUSED ) { default: gcc_unreachable (); - + case DATA_AREA_SDA: kind = ((TREE_READONLY (decl)) ? GHS_SECTION_KIND_ROSDATA : GHS_SECTION_KIND_SDATA); break; - + case DATA_AREA_TDA: kind = GHS_SECTION_KIND_TDATA; break; - + case DATA_AREA_ZDA: kind = ((TREE_READONLY (decl)) ? GHS_SECTION_KIND_ROZDATA : GHS_SECTION_KIND_ZDATA); break; - + case DATA_AREA_NORMAL: /* default data area */ if (TREE_READONLY (decl)) kind = GHS_SECTION_KIND_RODATA; @@ -2585,7 +2585,7 @@ construct_dispose_instruction (rtx op) int i; static char buff[ 120 ]; /* XXX */ int use_callt = 0; - + if (count <= 2) { error ("bogus DISPOSE construction: %d", count); @@ -2597,7 +2597,7 @@ construct_dispose_instruction (rtx op) gcc_assert (GET_CODE (XVECEXP (op, 0, 1)) == SET); gcc_assert (GET_CODE (SET_SRC (XVECEXP (op, 0, 1))) == PLUS); gcc_assert (GET_CODE (XEXP (SET_SRC (XVECEXP (op, 0, 1)), 1)) == CONST_INT); - + stack_bytes = INTVAL (XEXP (SET_SRC (XVECEXP (op, 0, 1)), 1)); /* Each pop will remove 4 bytes from the stack.... */ @@ -2617,7 +2617,7 @@ construct_dispose_instruction (rtx op) for (i = 2; i < count; i++) { rtx vector_element = XVECEXP (op, 0, i); - + gcc_assert (GET_CODE (vector_element) == SET); gcc_assert (GET_CODE (SET_DEST (vector_element)) == REG); gcc_assert (register_is_ok_for_epilogue (SET_DEST (vector_element), @@ -2642,7 +2642,7 @@ construct_dispose_instruction (rtx op) for (i = 20; i < 32; i++) if (mask & (1 << i)) break; - + if (i == 31) sprintf (buff, "callt ctoff(__callt_return_r31c)"); else @@ -2654,31 +2654,31 @@ construct_dispose_instruction (rtx op) { static char regs [100]; /* XXX */ int done_one; - + /* Generate the DISPOSE instruction. Note we could just issue the bit mask as a number as the assembler can cope with this, but for the sake of our readers we turn it into a textual description. */ regs[0] = 0; done_one = 0; - + for (i = 20; i < 32; i++) { if (mask & (1 << i)) { int first; - + if (done_one) strcat (regs, ", "); else done_one = 1; - + first = i; strcat (regs, reg_names[ first ]); - + for (i++; i < 32; i++) if ((mask & (1 << i)) == 0) break; - + if (i > first + 1) { strcat (regs, " - "); @@ -2686,10 +2686,10 @@ construct_dispose_instruction (rtx op) } } } - + sprintf (buff, "dispose %d {%s}, r31", stack_bytes / 4, regs); } - + return buff; } @@ -2706,7 +2706,7 @@ construct_prepare_instruction (rtx op) int i; static char buff[ 120 ]; /* XXX */ int use_callt = 0; - + if (XVECLEN (op, 0) <= 1) { error ("bogus PREPEARE construction: %d", XVECLEN (op, 0)); @@ -2718,7 +2718,7 @@ construct_prepare_instruction (rtx op) gcc_assert (GET_CODE (XVECEXP (op, 0, 0)) == SET); gcc_assert (GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) == PLUS); gcc_assert (GET_CODE (XEXP (SET_SRC (XVECEXP (op, 0, 0)), 1)) == CONST_INT); - + stack_bytes = INTVAL (XEXP (SET_SRC (XVECEXP (op, 0, 0)), 1)); @@ -2736,10 +2736,10 @@ construct_prepare_instruction (rtx op) for (i = 1; i < XVECLEN (op, 0); i++) { rtx vector_element = XVECEXP (op, 0, i); - + if (GET_CODE (vector_element) == CLOBBER) continue; - + gcc_assert (GET_CODE (vector_element) == SET); gcc_assert (GET_CODE (SET_SRC (vector_element)) == REG); gcc_assert (register_is_ok_for_epilogue (SET_SRC (vector_element), @@ -2762,7 +2762,7 @@ construct_prepare_instruction (rtx op) sprintf (buff, "callt ctoff(__callt_save_r2_r%d)", (mask & (1 << 31)) ? 31 : 29 ); return buff; } - + for (i = 20; i < 32; i++) if (mask & (1 << i)) break; @@ -2778,31 +2778,31 @@ construct_prepare_instruction (rtx op) static char regs [100]; /* XXX */ int done_one; - + /* Generate the PREPARE instruction. Note we could just issue the bit mask as a number as the assembler can cope with this, but for - the sake of our readers we turn it into a textual description. */ + the sake of our readers we turn it into a textual description. */ regs[0] = 0; done_one = 0; - + for (i = 20; i < 32; i++) { if (mask & (1 << i)) { int first; - + if (done_one) strcat (regs, ", "); else done_one = 1; - + first = i; strcat (regs, reg_names[ first ]); - + for (i++; i < 32; i++) if ((mask & (1 << i)) == 0) break; - + if (i > first + 1) { strcat (regs, " - "); @@ -2810,10 +2810,10 @@ construct_prepare_instruction (rtx op) } } } - + sprintf (buff, "prepare {%s}, %d", regs, (- stack_bytes) / 4); } - + return buff; } @@ -2914,7 +2914,7 @@ v850_return_in_memory (const_tree type, const_tree fntype ATTRIBUTE_UNUSED) /* Worker function for TARGET_FUNCTION_VALUE. */ static rtx -v850_function_value (const_tree valtype, +v850_function_value (const_tree valtype, const_tree fn_decl_or_type ATTRIBUTE_UNUSED, bool outgoing ATTRIBUTE_UNUSED) { @@ -3064,7 +3064,7 @@ v850_legitimate_address_p (machine_mode mode, rtx x, bool strict_p, + (GET_MODE_NUNITS (mode) * UNITS_PER_WORD)))) return true; - return false; + return false; } static int @@ -3176,7 +3176,7 @@ v850_gen_movdi (rtx * operands) if (REGNO (operands[1]) & 1) /* Use two store word instructions to synthesise a store double. */ return "st.w %1, %0 ; st.w %R1, %R0 "; - + return "st.dw %1, %0"; } diff --git a/gcc/config/v850/v850.h b/gcc/config/v850/v850.h index 2b31dd1..2721ea0 100644 --- a/gcc/config/v850/v850.h +++ b/gcc/config/v850/v850.h @@ -63,7 +63,7 @@ #if TARGET_CPU_DEFAULT == TARGET_CPU_v850e1 #undef MASK_DEFAULT -#define MASK_DEFAULT MASK_V850E /* No practical difference. */ +#define MASK_DEFAULT MASK_V850E /* No practical difference. */ #undef SUBTARGET_ASM_SPEC #define SUBTARGET_ASM_SPEC "%{!mv*:-mv850e1}" #undef SUBTARGET_CPP_SPEC @@ -72,7 +72,7 @@ #if TARGET_CPU_DEFAULT == TARGET_CPU_v850e2 #undef MASK_DEFAULT -#define MASK_DEFAULT MASK_V850E2 +#define MASK_DEFAULT MASK_V850E2 #undef SUBTARGET_ASM_SPEC #define SUBTARGET_ASM_SPEC "%{!mv*:-mv850e2}" #undef SUBTARGET_CPP_SPEC @@ -99,7 +99,7 @@ #define TARGET_VERSION fprintf (stderr, " (Renesas V850E3V5)"); #endif -#define TARGET_V850E3V5_UP ((TARGET_V850E3V5)) +#define TARGET_V850E3V5_UP ((TARGET_V850E3V5)) #define TARGET_V850E2V3_UP ((TARGET_V850E2V3) || TARGET_V850E3V5_UP) #define TARGET_V850E2_UP ((TARGET_V850E2) || TARGET_V850E2V3_UP) #define TARGET_V850E_UP ((TARGET_V850E) || TARGET_V850E2_UP) @@ -127,7 +127,7 @@ #define EXTRA_SPECS \ { "subtarget_asm_spec", SUBTARGET_ASM_SPEC }, \ - { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC } + { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC } /* Macro to decide when FPU instructions can be used. */ @@ -308,7 +308,7 @@ For any two classes, it is very desirable that there be another class that represents their union. */ - + enum reg_class { NO_REGS, EVEN_REGS, GENERAL_REGS, ALL_REGS, LIM_REG_CLASSES @@ -353,7 +353,7 @@ enum reg_class Since they use reg_renumber, they are safe only once reg_renumber has been allocated, which happens in reginfo.cc during register allocation. */ - + #define REGNO_OK_FOR_BASE_P(regno) \ (((regno) < FIRST_PSEUDO_REGISTER \ && (regno) != CC_REGNUM \ @@ -412,7 +412,7 @@ enum reg_class /* Register containing return address from latest function call. */ #define LINK_POINTER_REGNUM LP_REGNUM - + /* On some machines the offset between the frame pointer and starting offset of the automatic variables is not known until after register allocation has been done (for example, because the saved registers @@ -432,7 +432,7 @@ enum reg_class Do not define this macro if it would be the same as `FRAME_POINTER_REGNUM'. */ -#undef HARD_FRAME_POINTER_REGNUM +#undef HARD_FRAME_POINTER_REGNUM #define HARD_FRAME_POINTER_REGNUM 29 /* Base register for access to arguments of the function. */ @@ -578,7 +578,7 @@ struct cum_arg { int nbytes; }; #define NO_FUNCTION_CSE 1 /* The four different data regions on the v850. */ -typedef enum +typedef enum { DATA_AREA_NORMAL, DATA_AREA_SDA, @@ -617,7 +617,7 @@ typedef enum #define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \ asm_output_aligned_bss ((FILE), (DECL), (NAME), (SIZE), (ALIGN)) -#undef ASM_OUTPUT_ALIGNED_BSS +#undef ASM_OUTPUT_ALIGNED_BSS #define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \ v850_output_aligned_bss (FILE, DECL, NAME, SIZE, ALIGN) @@ -634,7 +634,7 @@ typedef enum #undef ASM_OUTPUT_LOCAL #define ASM_OUTPUT_ALIGNED_DECL_LOCAL(FILE, DECL, NAME, SIZE, ALIGN) \ v850_output_local (FILE, DECL, NAME, SIZE, ALIGN) - + /* Globalizing directive for a label. */ #define GLOBAL_ASM_OP "\t.global " @@ -767,26 +767,26 @@ typedef enum can appear in the "ghs section" pragma. These names are used to index into the GHS_default_section_names[] and GHS_current_section_names[] that are defined in v850.cc, and so the ordering of each must remain - consistent. + consistent. - These arrays give the default and current names for each kind of + These arrays give the default and current names for each kind of section defined by the GHS pragmas. The current names can be changed - by the "ghs section" pragma. If the current names are null, use + by the "ghs section" pragma. If the current names are null, use the default names. Note that the two arrays have different types. For the *normal* section kinds (like .data, .text, etc.) we do not want to explicitly force the name of these sections, but would rather - let the linker (or at least the back end) choose the name of the + let the linker (or at least the back end) choose the name of the section, UNLESS the user has forced a specific name for these section kinds. To accomplish this set the name in ghs_default_section_names to null. */ enum GHS_section_kind -{ +{ GHS_SECTION_KIND_DEFAULT, GHS_SECTION_KIND_TEXT, - GHS_SECTION_KIND_DATA, + GHS_SECTION_KIND_DATA, GHS_SECTION_KIND_RODATA, GHS_SECTION_KIND_BSS, GHS_SECTION_KIND_SDATA, diff --git a/gcc/config/visium/visium.h b/gcc/config/visium/visium.h index afeb68f..c5cce1d 100644 --- a/gcc/config/visium/visium.h +++ b/gcc/config/visium/visium.h @@ -119,7 +119,7 @@ data area approach is no longer used, these pointers are no longer supported. - The macro and function pointers are described below. + The macro and function pointers are described below. INIT_EXPANDERS: @@ -1015,7 +1015,7 @@ struct visium_args A difficulty is setting the correct instruction parity at run time. - TRAMPOLINE_SIZE + TRAMPOLINE_SIZE A C expression for the size in bytes of the trampoline, as an integer. */ #define TRAMPOLINE_SIZE (visium_cpu == PROCESSOR_GR6 ? 24 : 20) diff --git a/gcc/config/vx-common.h b/gcc/config/vx-common.h index d727e85..98636e2 100644 --- a/gcc/config/vx-common.h +++ b/gcc/config/vx-common.h @@ -1,4 +1,4 @@ -/* Target-independent configuration for VxWorks and VxWorks AE. +/* Target-independent configuration for VxWorks and VxWorks AE. Copyright (C) 2005-2024 Free Software Foundation, Inc. Contributed by CodeSourcery, LLC. diff --git a/gcc/config/vxworks.cc b/gcc/config/vxworks.cc index fab92d3..80577e2 100644 --- a/gcc/config/vxworks.cc +++ b/gcc/config/vxworks.cc @@ -72,9 +72,9 @@ static tree vxworks_emutls_var_fields (tree type, tree *name) { tree field, next_field; - + *name = get_identifier ("__tls_var"); - + field = build_decl (BUILTINS_LOCATION, FIELD_DECL, get_identifier ("size"), unsigned_type_node); DECL_CONTEXT (field) = type; @@ -106,23 +106,23 @@ vxworks_emutls_var_init (tree var, tree decl, tree tmpl_addr) { vec<constructor_elt, va_gc> *v; vec_alloc (v, 3); - + tree type = TREE_TYPE (var); tree field = TYPE_FIELDS (type); - + constructor_elt elt = {field, fold_convert (TREE_TYPE (field), tmpl_addr)}; v->quick_push (elt); - + field = DECL_CHAIN (field); elt.index = field; elt.value = build_int_cst (TREE_TYPE (field), 0); v->quick_push (elt); - + field = DECL_CHAIN (field); elt.index = field; elt.value = fold_convert (TREE_TYPE (field), DECL_SIZE_UNIT (decl)); v->quick_push (elt); - + return build_constructor (type, v); } @@ -155,7 +155,7 @@ vxworks_override_options (void) the toolchain user is expected to provide whatever linker level glue is required to get things to operate properly. */ - targetm.have_ctors_dtors = + targetm.have_ctors_dtors = TARGET_VXWORKS_HAVE_CTORS_DTORS || HAVE_INITFINI_ARRAY_SUPPORT; /* PIC is only supported for RTPs. flags_pic might be < 0 here, in diff --git a/gcc/config/vxworksae.h b/gcc/config/vxworksae.h index b95f22d..2114928 100644 --- a/gcc/config/vxworksae.h +++ b/gcc/config/vxworksae.h @@ -45,7 +45,7 @@ along with GCC; see the file COPYING3. If not see #undef VXWORKS_LINK_SPEC #define VXWORKS_LINK_SPEC \ "-r %{v:-V}" - + #undef VXWORKS_LIBGCC_SPEC #define VXWORKS_LIBGCC_SPEC \ "-lgcc" |