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2007-07-14mips.c (mips_classify_symbol): Don't return SYMBOL_SMALL_DATA for constant ↵Sandra Loosemore1-1/+2
pool addresses if... 2007-07-14 Sandra Loosemore <sandra@codesourcery.com> Nigel Stephens <nigel@mips.com> gcc/ * config/mips/mips.c (mips_classify_symbol): Don't return SYMBOL_SMALL_DATA for constant pool addresses if TARGET_EMBEDDED_DATA is true. Co-Authored-By: Nigel Stephens <nigel@mips.com> From-SVN: r126643
2007-07-14* config/i386/i386.c: Fix fallout from my previous commit.Uros Bizjak1-1/+1
From-SVN: r126640
2007-07-14i386.c (init_mmx_sse_builtins): Define all builtins except ↵Uros Bizjak1-122/+122
__builtin_ia32_emms... * config/i386/i386.c (init_mmx_sse_builtins): Define all builtins except __builtin_ia32_emms, __builtin_ia32_ldmxcsr, __builtin_ia32_stmxcsr, __builtin_ia32_maskmovq, __builtin_ia32_loadups, __builtin_ia32_storeups, __builtin_ia32_loadhps, __builtin_ia32_loadlps, __builtin_ia32_storehps, __builtin_ia32_storelps, __builtin_ia32_movntps, __builtin_ia32_movntq, __builtin_ia32_sfence, __builtin_ia32_femms, __builtin_ia32_maskmovdqu, __builtin_ia32_loadupd, __builtin_ia32_storeupd, __builtin_ia32_loadhpd, __builtin_ia32_loadlpd, __builtin_ia32_movnti, __builtin_ia32_movntpd, __builtin_ia32_movntdq, __builtin_ia32_clflush, __builtin_ia32_lfence, __builtin_ia32_mfence, __builtin_ia32_loaddqu, __builtin_ia32_storedqu, __builtin_ia32_monitor, __builtin_ia32_mwait, __builtin_ia32_lddqu, __builtin_ia32_movntdqa, __builtin_ia32_movntsd and __builtin_ia32_movntss as const builtins using def_builtin_const. From-SVN: r126639
2007-07-13spe.md (SPE_ACC_REGNO): Delete definition.David Edelsohn8-138/+160
* config/rs6000/spe.md (SPE_ACC_REGNO): Delete definition. (SPEFSCR_REGNO): Delete definition. * config/rs6000/rs6000.c: LINK_REGISTER_REGNUM -> LR_REGNO. COUNT_REGISTER_REGNUM -> CTR_REGNO. * config/rs6000/rs6000.h: Do not define *_REGNO. LINK_REGISTER_REGNUM -> LR_REGNO. COUNT_REGISTER_REGNUM -> CTR_REGNO. * config/rs6000/predicates.md: LINK_REGISTER_REGNUM -> LR_REGNO. COUNT_REGISTER_REGNUM -> CTR_REGNO. * config/rs6000/linux-unwind.h: Define R_LR, R_CR2, R_VR0, R_VRSAVE, R_VSCR. Use them. * config/rs6000/darwin-fallback.c: Define R_LR, R_CTR, R_CR2, R_XER, R_VR0, R_VRSAVE, R_VSCR, R_SPEFSCR. Use them. * config/rs6000/rs6000.md: Define REGNO constants. Use them. * config/rs6000/aix.h: Define R_LR. Use it. From-SVN: r126631
2007-07-13Add ability to track uninitialized variables, and mark uninitialized ↵Caroline Tice1-0/+3
variables in the Dwarf debug info. Add ability to track uninitialized variables, and mark uninitialized variables in the Dwarf debug info. Controlled by compile option -fvar-tracking-uninit From-SVN: r126630
2007-07-13config.gcc: Add options for arch and tune on SPU.Sa Liu10-61/+996
2007-07-13 Sa Liu <saliu@de.ibm.com> * config.gcc: Add options for arch and tune on SPU. * config/spu/predicates.md: Add constant operands 0 and 1. * config/spu/spu-builtins.def: Add builtins for double precision floating point comparison: si_dfceq, si_dfcmeq, si_dfcgt, si_dfcmgt, si_dftsv, spu_cmpeq_13, spu_cmpabseq_1, spu_cmpgt_13, spu_cmpabsgt_1, spu_testsv. * config/spu/spu-c.c: Define __SPU_EDP__ when builtins invoked with a CELLEDP target. * config/spu/spu-protos.h: Add new function prototypes. * config/spu/spu.c (spu_override_options): Check options -march and -mtune. (spu_comp_icode): Add comparison code for DFmode and vector mode. (spu_emit_branch_or_set): Use the new code for DFmode and vector mode comparison. (spu_const_from_int): New. Create a vector constant from 4 ints. (get_vec_cmp_insn): New. Get insn index of vector compare instruction. (spu_emit_vector_compare): New. Emit vector compare. (spu_emit_vector_cond_expr): New. Emit vector conditional expression. * config/spu/spu.h: Add options -march and -mtune. Define processor types PROCESSOR_CELL and PROCESSOR_CELLEDP. Define macro CANONICALIZE_COMPARISON. * config/spu/spu.md: Add new insns for double precision compare and double precision vector compare. Add vcond and smax/smin patterns to enable DFmode vector conditional expression. * config/spu/spu.opt: Add options -march and -mtune. * config/spu/spu_internals.h: Add builtins for CELLEDP target: si_dfceq, si_dfcmeq, si_dfcgt, si_dfcmgt, si_dftsv. Add builtin for both CELL and CELLEDP targets: spu_testsv. * config/spu/spu_intrinsics.h: Add flag mnemonics for test special values. testsuite/ * gcc.dg/vect/fast-math-vect-reduc-7.c: Switch on test for V2DFmode vector conditional expression. * gcc.target/spu/dfcmeq.c: New. Test combination of abs and dfceq patterns. * gcc.target/spu/dfcmgt.c: New. Test combination of abs and dfcgt patterns. * gcc.target/spu/intrinsics-2.c: New. Test intrinsics for V2DFmode comparison and test special values. * lib/target-supports.exp: Switch on test for V2DFmode vector conditional expression. From-SVN: r126626
2007-07-13linux-unwind.h (sh_fallback_frame_state): Use correct index when setting ↵Kaz Kojima1-3/+3
register save state for xd registers. * config/sh/linux-unwind.h (sh_fallback_frame_state): Use correct index when setting register save state for xd registers. From-SVN: r126612
2007-07-13sh.c (mark_use): Remove.Kaz Kojima1-81/+0
* config/sh/sh.c (mark_use): Remove. From-SVN: r126611
2007-07-12arm.c (thumb1_compute_save_reg_mask): Make sure scratch reg does not overlap ↵Paul Brook1-0/+4
return value. 2007-07-12 Paul Brook <paul@codesourcery.com> gcc/ * config/arm/arm.c (thumb1_compute_save_reg_mask): Make sure scratch reg does not overlap return value. From-SVN: r126604
2007-07-12sse.md (storentdf, storentsf): New.Zdenek Dvorak1-0/+14
* config/i386/sse.md (storentdf, storentsf): New. From-SVN: r126594
2007-07-12re PR target/25413 (wrong alignment or incorrect address computation in ↵Dorit Nuzman1-0/+35
vectorized code on Pentium 4 SSE) 2007-07-12 Dorit Nuzman <dorit@il.ibm.com> Devang Patel <dpatel@apple.com> PR tree-optimization/25413 * targhooks.c (default_builtin_vector_alignment_reachable): New. * targhooks.h (default_builtin_vector_alignment_reachable): New. * tree.h (contains_packed_reference): New. * expr.c (contains_packed_reference): New. * tree-vect-analyze.c (vector_alignment_reachable_p): New. (vect_enhance_data_refs_alignment): Call vector_alignment_reachable_p. * target.h (vector_alignment_reachable): New builtin. * target-def.h (TARGET_VECTOR_ALIGNMENT_REACHABLE): New. * config/rs6000/rs6000.c (rs6000_vector_alignment_reachable): New. (TARGET_VECTOR_ALIGNMENT_REACHABLE): Define. Co-Authored-By: Devang Patel <dpatel@apple.com> From-SVN: r126591
2007-07-12target.h (builtin_vectorization_cost): Add new target builtin.Dorit Nuzman2-0/+65
2007-07-12 Dorit Nuzman <dorit@il.ibm.com> * target.h (builtin_vectorization_cost): Add new target builtin. * target-def.h (TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST): New. * tree-vectorizer.h (TARG_SCALAR_STMT_COST): New. (TARG_SCALAR_LOAD_COST, TARG_SCALAR_STORE_COST): New. * tree-vect-analyze.c (vect_analyze_slp_instance): Initisliaze uninitialized variables. * tree-vect-transform.c (cost_for_stmt): New function. (vect_estimate_min_profitable_iters): Call cost_for_stmt instead of using cost 1 for all scalar stmts. Be less conservative when estimating the number of prologue/epulogue iterations. Call targetm.vectorize.builtin_vectorization_cost. Return min_profitable_iters-1. (vect_model_reduction_cost): Use TARG_SCALAR_TO_VEC_COST for initialization cost instead of TARG_VEC_STMT_COST. Use TARG_VEC_TO_SCALAR_COST instead of TARG_VEC_STMT_COST for reduction epilogue code. Fix epilogue cost computation. * config/spu/spu.c (spu_builtin_vectorization_cost): New. (TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST): Implement. * config/spu/spu.h (TARG_COND_BRANCH_COST, TARG_SCALAR_STMT_COST): (TARG_SCALAR_LOAD_COST, TARG_SCALAR_STORE_COST, TARG_VEC_STMT_COST): (TARG_VEC_TO_SCALAR_COST, TARG_SCALAR_TO_VEC, TARG_VEC_LOAD_COST): (TARG_VEC_UNALIGNED_LOAD_COST, TARG_VEC_STORE_COST): Define. 2007-07-12 Dorit Nuzman <dorit@il.ibm.com> * gcc.dg/vect/costmodel/ppc/costmodel-vect-reduc-1char.c: Loops now get vectorized. * gcc.dg/vect/costmodel/i386/costmodel-vect-reduc-1char.c: Loops now get vectorized. * gcc.dg/vect/costmodel/spu/spu-costmodel-vect.exp: New. * gcc.dg/vect/costmodel/spu/costmodel-fast-math-vect-pr29925.c: New. * gcc.dg/vect/costmodel/spu/costmodel-vect-31a.c: New. * gcc.dg/vect/costmodel/spu/costmodel-vect-31b.c: New. * gcc.dg/vect/costmodel/spu/costmodel-vect-31c.c: New. * gcc.dg/vect/costmodel/spu/costmodel-vect-31d.c: New. * gcc.dg/vect/costmodel/spu/costmodel-vect-iv-9.c: New. * gcc.dg/vect/costmodel/spu/costmodel-vect-33.c: New. * gcc.dg/vect/costmodel/spu/costmodel-vect-76a.c: New. * gcc.dg/vect/costmodel/spu/costmodel-vect-76b.c: New. * gcc.dg/vect/costmodel/spu/costmodel-vect-76c.c: New. * gcc.dg/vect/costmodel/spu/costmodel-vect-68a.c: New. * gcc.dg/vect/costmodel/spu/costmodel-vect-68b.c: New. * gcc.dg/vect/costmodel/spu/costmodel-vect-68c.c: New. * gcc.dg/vect/costmodel/spu/costmodel-vect-68d.c: New. * lib/target-supports.exp (check_effective_target_vect_int_mul): Add spu. From-SVN: r126584
2007-07-12sh.md (symGOTOFF2reg): Add missing parenthesis.Kaz Kojima1-2/+2
* config/sh/sh.md (symGOTOFF2reg): Add missing parenthesis. (symDTPOFF2reg): Likewise. From-SVN: r126571
2007-07-11re PR target/32661 (__builtin_ia32_vec_ext suboptimal for pointer/ref args)Uros Bizjak1-5/+26
PR target/32661 * config/i386/sse.md (*sse2_storeq_rex64): Handle 64bit mem->reg moves. (*vec_extractv2di_1_sse2): Disable for TARGET_64BIT. (*vec_extractv2di_1_rex64): New insn pattern. testsuite/ChangeLog: PR target/32661 * gcc.target/i386/pr32661-1.c: New test. From-SVN: r126557
2007-07-11linux-unwind.h (mips_fallback_frame_state): Rewrite return address calculation.David Daney2-13/+15
* config/mips/linux-unwind.h (mips_fallback_frame_state): Rewrite return address calculation. Substitute DWARF_ALT_FRAME_RETURN_COLUMN for SIGNAL_UNWIND_RETURN_COLUMN. * config/mips/mips.h (SIGNAL_UNWIND_RETURN_COLUMN): Remove. (DWARF_FRAME_REGNUM): Rewrite. (DWARF_ALT_FRAME_RETURN_COLUMN) Define. From-SVN: r126555
2007-07-11* config/m32r/m32r.h (INITIALIZE_TRAMPOLINE): Revert previous delta and use ↵Nick Clifton1-44/+12
gen_int_mode in place of GET_INT instead. From-SVN: r126552
2007-07-11spu.c (spu_optimization_options): Remove setting of parameter ↵Ulrich Weigand1-5/+6
PARAM_MAX_COMPLETELY_PEEL_TIMES. * config/spu/spu.c (spu_optimization_options): Remove setting of parameter PARAM_MAX_COMPLETELY_PEEL_TIMES. (spu_override_options): Move it here. From-SVN: r126549
2007-07-11mips.h (MIPS_ISA_LEVEL_SPEC): Handle -m4ksc and -m4ksd.Richard Sandiford2-3/+4
gcc/ * config/mips/mips.h (MIPS_ISA_LEVEL_SPEC): Handle -m4ksc and -m4ksd. * config/mips/mips.c (mips_cpu_info_table): Mention MIPS_ISA_LEVEL_SPEC in the comment. From-SVN: r126548
2007-07-11cygming.h (PREFERRED_DEBUGGING_TYPE): Define to DWARF2_DEBUG on 32 bit ↵Danny Smith1-16/+10
target too. * config/i386/cygming.h (PREFERRED_DEBUGGING_TYPE): Define to DWARF2_DEBUG on 32 bit target too. (DWARF2_UNWIND_INFO): Reorganize 64-bit vs 32-bit definition. From-SVN: r126544
2007-07-11* config/m32r/m32r.h (INITIALIZE_TRAMPOLINE): Provide alternative version ↵Nick Clifton1-0/+32
for 64-bit hosts. From-SVN: r126539
2007-07-11mips.h (ISA_HAS_SYNCI): New target capability predicate.David Daney4-11/+105
2007-07-10 David Daney <ddaney@avtrex.com> * config/mips/mips.h (ISA_HAS_SYNCI): New target capability predicate. (INITIALIZE_TRAMPOLINE): Emit clear_cache insn instead of library call. * config/mips/mips.c (mips_expand_synci_loop): New function. * config/mips/mips.md (UNSPEC_CLEAR_HAZARD): New constant. (UNSPEC_RDHWR): Same. (UNSPEC_SYNCI): Same. (UNSPEC_SYNC): Same. (clear_cache): New expand. (sync): New insn. (synci): Same. (rdhwr): Same. (clear_hazard): Same. * config/mips/mips-protos.h (mips_expand_synci_loop): Declare function. * testsuite/gcc.target/mips/clear-cache-1.c: New test. * testsuite/gcc.target/mips/clear-cache-2.c: New test. From-SVN: r126537
2007-07-11* config/cris/cris.md ("movsi"): Fix typo in last change.Hans-Peter Nilsson1-1/+1
From-SVN: r126534
2007-07-10re PR target/32708 (_mm_cvtsi64x_si128() and _mm_cvtsi128_si64x() inefficient)Uros Bizjak1-1/+18
PR target/32708 * config/i386/sse.md (vec_concatv2di): Disable for TARGET_64BIT. (*vec_concatv2di_rex): New insn pattern. testsuite/ChangeLog: PR target/32708 * gcc.target/i386/pr32708-1.c: New test. * gcc.target/i386/pr32708-2.c: Ditto. * gcc.target/i386/pr32708-3.c: Ditto. From-SVN: r126523
2007-07-10re PR target/32538 (All libgomp tests fail to link on IRIX 6: copysignl ↵Rainer Orth1-3/+4
undefined) PR target/32538 * config/mips/iris6.h (LIBGCC_SPEC): Add libm. From-SVN: r126520
2007-07-10Replace no_new_pseudos in backends.Ian Lance Taylor31-194/+221
* rtl.h (can_create_pseudo_p): Define. * config/darwin.c (machopic_indirect_data_reference): Use can_create_pseudo_p () instead of no_new_pseudos. (machopic_indirect_data_reference): Likewise. (machopic_legitimize_pic_address): Likewise. * config/alpha/alpha.c (alpha_legitimize_address): Likewise. (alpha_emit_set_const_1): Likewise. (alpha_emit_set_const): Likewise. (alpha_emit_conditional_move): Likewise. (alpha_split_conditional_move): Likewise. * config/alpha/alpha.md (various splitters): Likewise. (movti): Likewise. * config/arm/arm.c (legitimize_pic_address): Likewise. (arm_load_pic_register): Likewise. * config/arm/arm.md (addsi3, subsi3, andsi3, iorsi3): Likewise. (movdi, movsi, movhi, movqi, movsf, movdf): Likewise. * config/bfin/bfin.c (legitimize_pic_address): Likewise. * config/cris/cris.c (cris_expand_pic_call_address): Likewise. * config/cris/cris.md (movsi): Likewise. * config/frv/frv.md (symGOT2reg_hilo): Likewise. (symGOTOFF2reg_hilo): Likewise. (symGPREL2reg, symGPREL2reg_hilo): Likewise. * config/h8300/h8300.md (insv, extzv): Likewise. * config/i386/i386.c (ix86_expand_move): Likewise. (ix86_expand_vector_move): Likewise. (ix86_prepare_fp_compare_args): Likewise. (ix86_expand_carry_flag_compare): Likewise. * config/i386/i386.md (tls_dynamic_gnu2_32): Likewise. (tls_dynamic_gnu2_combine_32): Likewise. (tls_dynamic_gnu2_64, tls_dynamic_gnu2_combine_64): Likewise. * config/ia64/ia64.c (ia64_expand_move): Likewise. (ia64_expand_movxf_movrf): Likewise. * config/m32c/m32c.c (m32c_prepare_move): Likewise. (m32c_split_move): Likewise. (m32c_expand_insv): Likewise. * config/m68k/m68k.md (movsi): Likewise. * config/mips/mips.c (mips_force_temporary): Likewise. (mips_split_symbol): Likewise. (mips_move_integer): Likewise. (mips_legitimize_const_move): Likewise. * config/mn10300/mn10300.md (movsi): Likewise. * config/pa/pa.c (emit_move_sequence): Likewise. * config/rs6000/rs6000.c (rs6000_emit_move): Likewise. (rs6000_got_register): Likewise. (create_TOC_reference): Likewise. (rs6000_machopic_legitimize_pic_address): Likewise. * config/rs6000/rs6000.md (add<mode>3): Likewise. (various splitters): Likewise. (iorsi3, xorsi3, iordi3, xordi3): Likewise. (movsi_got): Likewise. * config/s390/s390.c (emit_symbolic_move): Likewise. * config/s390/s390.md (movhi, movqi): Likewise. (load_multiple, store_multiple): Likewise. * config/score/score.c (score_force_temporary): Likewise. * config/sh/sh.c (prepare_move_operands): Likewise. (prepare_cbranch_operands): Likewise. (emit_fpu_switch): Likewise. (fpscr_set_from_mem): Likewise. * config/sh/sh.md (movdicc, movsicc, movsicc_umin): Likewise. (adddi3, subsi3): Likewise. (various splitters): Likewise. (divsi_inv_fp_combine): Likewise. (symGOT_load, symGOTOFF2reg, symDTPOFF2reg): Likewise. (seq, slt, sle, sgt, sge, sgtu, sltu, sleu, sgeu): Likewise. (sne): Likewise. * config/sh/predicates.md (xor_operand): Likewise. * config/sparc/sparc.c (legitimize_tls_address): Likewise. * config/sparc/sparc.md (movsi_pic_label_ref): Likewise. (movdi_pic_label_ref): Likewise. * config/spu/spu.c (spu_split_immediate): Likewise. * config/alpha/alpha.md (various splitters): Remove test !no_new_pseudos || reload_completed. * config/ia64/ia64.c (ia64_output_mi_thunk): Don't set no_new_pseudos. * config/m68k/m68k.c (m68k_output_mi_thunk): Likewise. * config/mips/mips.c (mips_output_mi_thunk): Likewise. * config/rs6000/rs6000.c (rs6000_output_mi_thunk): Likewise. * config/score/score.c (th_output_mi_thunk): Likewise. * config/sh/sh.c (sh_output_mi_thunk): Likewise. * config/sparc/sparc.c (sparc_output_mi_thunk): Likewise. From-SVN: r126517
2007-07-09optabs.h: Added declaration for signbit_optab.Wolfgang Gellerich2-0/+19
2007-07-09 Wolfgang Gellerich <gellerich@de.ibm.com> * optabs.h: Added declaration for signbit_optab. * optabs.c: (init_optabs): Added initialization for signbit_optab. * genoptinit.c (optabs): Added entry for signbit insns. * builtins.c (expand_builtin_signbit): Added code to use a signbit insn, if available. * config/s390/s390.h (S390_TDC_SIGNBIT_SET): New constant. * config/s390/s390.md (signbit<mode>2): New expander. From-SVN: r126495
2007-07-07constraints.md (define_memory_constraint "Q"): Fix the constraint description.Eric Weddington1-1/+1
* config/avr/constraints.md (define_memory_constraint "Q"): Fix the constraint description. * doc/md.texi: Update documentation of AVR constraints. From-SVN: r126448
2007-07-07auto-inc-dec.c, [...]: Fix comment typos.Kazu Hirata4-6/+6
* auto-inc-dec.c, config/arm/arm.c, config/m32r/constraints.md, config/mips/mips.md, config/rs6000/rs6000.c, cselib.c, dce.c, df-core.c, df-problems.c, df-scan.c, df.h, dse.c, gimplify.c, tree-if-conv.c, tree-ssa-sccvn.c, tree-ssa.c: Fix comment typos. Follow spelling conventions. * doc/invoke.texi, doc/rtl.texi: Fix typos. From-SVN: r126439
2007-07-06sh.md (*prefetch_i4): Disable for TARGET_VXWORKS_RTP.Richard Sandiford1-2/+5
gcc/ * config/sh/sh.md (*prefetch_i4): Disable for TARGET_VXWORKS_RTP. (prefetch): Likewise if "pref" would be used. From-SVN: r126423
2007-07-06libgcc2.h (word_type): Type definition removed.Andreas Krebbel1-0/+18
2007-07-06 Andreas Krebbel <krebbel1@de.ibm.com> * libgcc2.h (word_type): Type definition removed. (cmp_return_type, shift_count_type): Type definitions added. (__lshrdi3, __ashldi3, __ashrdi3): word_type of second parameter replaced with shift_count_type. (__cmpdi2, __ucmpdi2): word_type of return type replaced with cmp_return_type. * libgcc2.c (__udivmoddi4, __moddi3): Type of local variable c changed from word_type to Wtype. (__lshrdi3, __ashldi3, __ashrdi3): word_type of second parameter replaced with shift_count_type. (__cmpdi2, __ucmpdi2): word_type of return type replaced with cmp_return_type. * c-common.c (handle_mode_attribute): Handling for libgcc_cmp_return and libgcc_shift_count attribute added. * target-def.h (TARGET_LIBGCC_CMP_RETURN_MODE, TARGET_LIBGCC_SHIFT_COUNT_MODE): New target hooks defined. (TARGET_INITIALIZER): New target hooks added. * targhooks.c (default_libgcc_cmp_return_mode, default_libgcc_shift_count_mode): Default implementations for the new target hooks added. * targhooks.h (default_libgcc_cmp_return_mode, default_libgcc_shift_count_mode): Function prototypes added. * target.h (struct gcc_target): Fields for the new target hooks added. * optabs.c (expand_binop): Use shift_count_mode when expanding shift as library call. (prepare_cmp_insn): Use cmp_return_mode when expanding comparison as library call. * doc/tm.texi (TARGET_LIBGCC_CMP_RETURN_MODE, TARGET_LIBGCC_SHIFT_COUNT_MODE): Documentation added. * config/s390/s390.c (s390_libgcc_cmp_return_mode, s390_libgcc_shift_count_mode): Functions added. (TARGET_LIBGCC_CMP_RETURN_MODE, TARGET_LIBGCC_SHIFT_COUNT_MODE): Target hooks defined. From-SVN: r126410
2007-07-06mips.c (compute_frame_size): Restore the original gp_sp_offset for ↵Richard Sandiford1-6/+10
!GENERATE_MIPS16E_SAVE_RESTORE and remove... gcc/ * config/mips/mips.c (compute_frame_size): Restore the original gp_sp_offset for !GENERATE_MIPS16E_SAVE_RESTORE and remove the fp_size term from the GENERATE_MIPS16E_SAVE_RESTORE calculation. Document why the difference is needed. From-SVN: r126406
2007-07-06mips.c (mips16e_save_restore_pattern_p): Check that the topmost argument ↵Richard Sandiford1-12/+20
register is not also included in the save mask. gcc/ * config/mips/mips.c (mips16e_save_restore_pattern_p): Check that the topmost argument register is not also included in the save mask. (mips16e_collect_argument_save_p): Take a pointer to the argument register, rather than a pointer to the number of arguments. (mips16e_collect_argument_saves): Only include argument saves that aren't in the register mask. gcc/testsuite/ * gcc.target/mips/save-restore-5.c: New test. From-SVN: r126404
2007-07-05arm.c (vfp3_const_double_index): Copy signed results of REAL_VALUE_TO_INT ↵Richard Earnshaw1-1/+4
into unsigned vars. * arm.c (vfp3_const_double_index): Copy signed results of REAL_VALUE_TO_INT into unsigned vars. From-SVN: r126390
2007-07-06avr.md (zero_extendqihi2, [...]): Change to define_insn_and_split.Anatoly Sokolov1-28/+84
* config/avr/avr.md (zero_extendqihi2, zero_extendqisi2, zero_extendhisi2): Change to define_insn_and_split. (zero_extendqidi2, zero_extendhidi2, zero_extendsidi2): New. From-SVN: r126387
2007-07-05Improve placement in previous commitRichard Sandiford1-5/+5
From-SVN: r126384
2007-07-05mips.c (mips_file_start): Avoid declaration after code.Richard Sandiford1-5/+5
gcc/ * config/mips/mips.c (mips_file_start): Avoid declaration after code. From-SVN: r126383
2007-07-05mips.c (mips_cpu_info): Add 4ksc and 4ksd processors.Sandra Loosemore1-0/+2
2007-07-05 Sandra Loosemore <sandra@codesourcery.com> David Ung <davidu@mips.com> gcc/ * config/mips/mips.c (mips_cpu_info): Add 4ksc and 4ksd processors. * doc/invoke.texi: (MIPS Options): Document them. Co-Authored-By: David Ung <davidu@mips.com> From-SVN: r126371
2007-07-05Add support for SmartMIPS ASE.Sandra Loosemore4-3/+58
2007-07-05 Sandra Loosemore <sandra@codesourcery.com> David Ung <davidu@mips.com> Add support for SmartMIPS ASE. gcc/ * optabs.c (expand_binop_directly): New, broken out from... (expand_binop): Here. Make it try rotating in the other direction even when the second operand isn't constant. * config/mips/mips.md (*lwxs): New. * config/mips/mips.opt (msmartmips): New. * config/mips/mips.c (mips_lwxs_address_p): New. (mips_rtx_costs): Make it recognize scaled indexed addressing. * config/mips/mips.h (TARGET_CPU_CPP_BUILTINS): Define __mips_smartmips when compiling for TARGET_SMARTMIPS. (ISA_HAS_ROR): Define for TARGET_SMARTMIPS. (ISA_HAS_LWXS): New. (ASM_SPEC): Add -msmartmips/-mno-smartmips. * doc/invoke.texi (MIPS Options): Document -msmartmips/-mno-smartmips. * testsuite/gcc.target/mips/smartmips-lwxs.c: New test case. * testsuite/gcc.target/mips/smartmips-ror-1.c: New test case. * testsuite/gcc.target/mips/smartmips-ror-2.c: New test case. * testsuite/gcc.target/mips/smartmips-ror-3.c: New test case. * testsuite/gcc.target/mips/smartmips-ror-4.c: New test case. Co-Authored-By: David Ung <davidu@mips.com> From-SVN: r126370
2007-07-05re PR testsuite/32014 (new gcc failures)Dorit Nuzman1-0/+60
PR testsuite/32014 * config/rs6000/altivec.md (UNSPEC_VUPKHS_V4SF, UNSPEC_VUPKLS_V4SF): (UNSPEC_VUPKHU_V4SF, UNSPEC_VUPKLU_V4SF): New. (vec_unpacks_float_hi_v8hi, vec_unpacks_float_lo_v8hi): New patterns. (vec_unpacku_float_hi_v8hi, vec_unpacku_float_lo_v8hi): New patterns. From-SVN: r126361
2007-07-05i386.c (ix86_address_cost): Do not consider more complex addressing modes ↵Zdenek Dvorak1-6/+0
cheaper. * config/i386/i386.c (ix86_address_cost): Do not consider more complex addressing modes cheaper. From-SVN: r126360
2007-07-05cygming-crtend.c: Remove svn:executable property.Uros Bizjak3-0/+0
* config/i386/cygming-crtend.c: Remove svn:executable property. * config/i386/cygming-crtbegin.c: Ditto. * config/i386/w32-unwinf.h: Ditto. From-SVN: r126355
2007-07-05re PR target/31331 ([avr] ICE on function attribute syntax for main())Anatoly Sokolov1-2/+19
PR target/31331 * config/avr/avr.c (avr_naked_function_p): Handle receiving a type rather than a decl. (avr_attribute_table): Make "naked" attribute apply to function types rather than to decls. (avr_handle_fntype_attribute): New function. From-SVN: r126337
2007-07-04mips.md (type): Add logical, signext and move.David Ung13-64/+110
2007-07-04 David Ung <davidu@mips.com> Joseph Myers <joseph@codesourcery.com> * config/mips/mips.md (type): Add logical, signext and move. (one_cmpl<mode>2, *and<mode>3, *and<mode>3_mips16, *ior<mode>3, *ior<mode>3_mips16, two unnamed insns after *ior<mode>3_mips16, *nor<mode>3, "Combiner patterns to optimize truncate/zero_extend combinations", *zero_extend<SHORT:mode><GPR:mode>2, *zero_extendqihi2, *extend<SHORT:mode><GPR:mode>2_mips16e, *extend<SHORT:mode><GPR:mode>2_se<SHORT:size>, *movdi_64bit, *movdi_64bit_mips16, *movsi_internal, *movsi_mips16, movcc, *movhi_internal, *movhi_mips16, *movqi_internal, *movqi_mips16, *movsf_hardfloat, *movsf_softfloat, *movsf_mips16, *movdf_hardfloat_64bit, *movdf_hardfloat_32bit, movv2sf_hardfloat_64bit): Use the new types. (*movdi_32bit, *movdi_gp32_fp64, *movdi_32bit_mips16, *movdf_softfloat, *movdf_mips16): Use "multi". (extendqihi2): Replace with a define_expand. (*extendqihi2_mips16e, *extendqihi2, *extendqihi2_seb): New. Based on extend<SHORT:mode><GPR:mode>2 patterns. * config/mips/74k.md (r74k_int_logical): New reservation and bypasses. (r74k_int_arith): Remove "slt". * config/mips/24k.md, config/mips/4130.md, config/mips/4k.md, config/mips/5400.md, config/mips/5500.md, config/mips/5k.md, config/mips/7000.md, config/mips/9000.md, config/mips/generic.md, config/mips/sb1.md, config/mips/sr71k.md: Add new types to reservations for "arith". Co-Authored-By: Joseph Myers <joseph@codesourcery.com> From-SVN: r126327
2007-07-04target.h (struct gcc_target): Add target_help field.Nick Clifton1-0/+89
* target.h (struct gcc_target): Add target_help field. * target-def.h (TARGET_HELP): New. (TARGET_INITIALIZER): Use TARGET_HELP. * opts.c (command_handle_option): Invoke target_help function, if defined, when the user has specified --target-help on the command line. * doc/invoke.texi: Mention that --target-help might print additional information. * doc/tm.texi: Document TARGET_HELP hook. * arm.c (TARGET_HELP): Override default definition. (arm_target_help): New - display a wrapped list of cores and architectures supported. From-SVN: r126323
2007-07-04v850.c (expand_prologue): Make sure GEN_INT() argument is sign extended ↵Rask Ingemann Lambertsen3-143/+7
rather than zero extended. * config/gcc/v850/v850.c (expand_prologue): Make sure GEN_INT() argument is sign extended rather than zero extended. (expand_epilogue): Likewise. (output_move_double): Delete. * config/gcc/v850/v850-protos.h (output_move_double): Delete. * config/gcc/v850/v850.md (movdi): Delete. (movdi_internal): Delete. (movdf): Delete. (movdf_internal): Delete. From-SVN: r126318
2007-07-04vxworks.h (SUBTARGET_OVERRIDE_OPTIONS): Reject -mrelax unless compiling RTP PIC.Richard Sandiford1-1/+14
gcc/ * config/sh/vxworks.h (SUBTARGET_OVERRIDE_OPTIONS): Reject -mrelax unless compiling RTP PIC. gcc/testsuite/ * gcc.dg/sh-relax.c: Skip for VxWorks if non-PIC. * gcc.dg/sh-relax-vxworks.c: New test. From-SVN: r126317
2007-07-04lib1funcs.asm (ic_invalidate): Align constant pool.Richard Sandiford1-0/+1
gcc/ * config/sh/lib1funcs.asm (ic_invalidate): Align constant pool. From-SVN: r126312
2007-07-04config.gcc (arm-wrs-vxworks): Don't include svr4.h.Richard Sandiford2-4/+12
gcc/ * config.gcc (arm-wrs-vxworks): Don't include svr4.h. * config/vxworks.h (PTRDIFF_TYPE, SIZE_TYPE, TARGET_POSIX_IO): Define. * config/arm/vxworks.h (ASM_SPEC): Delete. (SUBTARGET_EXTRA_ASM_SPEC): Define. From-SVN: r126310
2007-07-03configure.ac: Test for .dtprelword support on MIPS.Joseph Myers1-0/+28
* configure.ac: Test for .dtprelword support on MIPS. * configure, config.in: Regenerate. * config/mips/mips.c (mips_output_dwarf_dtprel): New. (TARGET_ASM_OUTPUT_DWARF_DTPREL): Define. From-SVN: r126273
2007-07-03config.gcc (with_fpu): Allow --with-fpu=vfp3.Julian Brown7-167/+422
gcc/ * config.gcc (with_fpu): Allow --with-fpu=vfp3. * config/arm/aout.h (REGISTER_NAMES): Add D16-D31. * config/arm/aof.h (REGISTER_NAMES): Add D16-D31. * config/arm/arm.c (FL_VFPV3): New flag for VFPv3 processor capability. (all_fpus): Add FPUTYPE_VFP3. (fp_model_for_fpu): Add VFPv3 field. (arm_rtx_costs_1): Give cost to VFPv3 constants. (vfp3_const_double_index): New function. Return integer index of VFPv3 constant suitable for fconst[sd] insns, or -1 if constant isn't suitable. (vfp3_const_double_rtx): New function. True if VFPv3 is enabled and argument represents a valid RTX for a VFPv3 constant. (vfp_output_fldmd): Split fldmd with > 16 registers in the list into two instructions. (vfp_emit_fstmd): Similar, for fstmd. (arm_print_operand): Implement new code 'G' for VFPv3 floating-point constants, represented as integer indices. (arm_hard_regno_mode_ok): Use VFP_REGNO_OK_FOR_SINGLE, VFP_REGNO_OK_FOR_DOUBLE macros. (arm_regno_class): Handle VFPv3 d0-d7, low, high register split. (arm_file_start): Set float-abi attribute for VFPv3, and output correct ".fpu" assembler directive. (arm_dbx_register_numbering): Add FIXME. * config/arm/arm.h (TARGET_VFP3): New macro. Target supports VFPv3. (fputype): Add FPUTYPE_VFP3. (FIXED_REGISTERS): Add 32 registers for D16-D31. (CALL_USED_REGISTERS): Likewise. (CONDITIONAL_REGISTER_USAGE): Add note about conditional definition of LAST_VFP_REGNUM. Make D16-D31 caller-saved, if present. (LAST_VFP_REGNUM): Extend available VFP registers for VFPv3. (D7_VFP_REGNUM): New. (LAST_LO_VFP_REGNUM, FIRST_HI_VFP_REGNUM, LAST_HI_VFP_REGNUM) (VFP_REGNO_OK_FOR_SINGLE, VFP_REGNO_OK_FOR_SINGLE) (VFP_REGNO_OK_FOR_DOUBLE): Define new macros. (FIRST_PSEUDO_REGISTER): Shift up to 128 to accommodate VFPv3. (REG_ALLOC_ORDER): Adjust for VFPv3. (reg_class): Add VFP_D0_D7_REGS, VFP_LO_REGS, VFP_HI_REGS. (REG_CLASS_NAMES): Add entries corresponding to VFP_D0_D7_REGS, VFP_LO_REGS, VFP_HI_REGS. (REG_CLASS_CONTENTS): Likewise. Extend contents for VFP_REGS. (IS_VFP_CLASS): Define macro. (SECONDARY_OUTPUT_RELOAD_CLASS, SECONDARY_INPUT_RELOAD_CLASS): Use IS_VFP_CLASS. (REGISTER_MOVE_COST): Likewise. * config/arm/arm-protos.h (vfp3_const_double_rtx): Add prototype. * config/arm/vfp.md (VFPCC_REGNUM): Redefine as 127. (*arm_movsi_vfp, *thumb2_movsi_vfp, *movsfcc_vfp) (*thumb2_movsfcc_vfp, *abssf2_vfp, *negsf2_vfp, *addsf3_vfp) (*subsf3_vfp, *divsf_vfp, *mulsf_vfp, *mulsf3negsf_vfp) (*mulsf3addsf_vfp, *mulsf3subsf_vfp, *mulsf3negsfaddsf_vfp) (*extendsfdf2_vfp, *truncdfsf2_vfp, *truncsisf2_vfp) (*truncsidf2_vfp, fixuns_truncsfsi2, fixuns_truncdfsi2) (*floatsisf2_vfp, *floatsidf2_vfp, floatunssisf2) (floatunssidf2, *sqrtsf2_vfp, *cmpsf_split_vfp) (*cmpsf_trap_split_vfp, *cmpsf_vfp, *cmpsf_trap_vfp): Use 't' where appropriate for single-word registers. (*movsf_vfp, *thumb2_movsf_vfp, *movdf_vfp, *thumb2_movdf_vfp): As above. Fix type attributes. * config/arm/constraints.md (register_contraint "t"): Define. (register_constraint "w"): Change to D0-D15, or D0-D31 for VFPv3/NEON. (register_constraint "x"): Define. (constraint "Dv"): Define. From-SVN: r126272
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