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| author | Anatoly Sokolov <aesok@post.ru> | 2007-07-06 00:41:29 +0400 |
|---|---|---|
| committer | Anatoly Sokolov <aesok@gcc.gnu.org> | 2007-07-06 00:41:29 +0400 |
| commit | 2d0c44e63f0de3f2b3ba05dc72f4965b99cb7036 (patch) | |
| tree | 0bb8291350a6e9a7e3f6adf3da6f9f08b7a1e185 /gcc/config | |
| parent | ec162f0dca286e595676101d0b080be5a6095cb9 (diff) | |
| download | gcc-2d0c44e63f0de3f2b3ba05dc72f4965b99cb7036.zip gcc-2d0c44e63f0de3f2b3ba05dc72f4965b99cb7036.tar.gz gcc-2d0c44e63f0de3f2b3ba05dc72f4965b99cb7036.tar.bz2 | |
avr.md (zero_extendqihi2, [...]): Change to define_insn_and_split.
* config/avr/avr.md (zero_extendqihi2, zero_extendqisi2,
zero_extendhisi2): Change to define_insn_and_split.
(zero_extendqidi2, zero_extendhidi2, zero_extendsidi2): New.
From-SVN: r126387
Diffstat (limited to 'gcc/config')
| -rw-r--r-- | gcc/config/avr/avr.md | 112 |
1 files changed, 84 insertions, 28 deletions
diff --git a/gcc/config/avr/avr.md b/gcc/config/avr/avr.md index 2a7c9c8..8c8afee 100644 --- a/gcc/config/avr/avr.md +++ b/gcc/config/avr/avr.md @@ -1685,39 +1685,95 @@ ;; xx<---x xx<---x xx<---x xx<---x xx<---x xx<---x xx<---x xx<---x xx<---x ;; zero extend -(define_insn "zero_extendqihi2" - [(set (match_operand:HI 0 "register_operand" "=r,r") - (zero_extend:HI (match_operand:QI 1 "register_operand" "0,*r")))] +(define_insn_and_split "zero_extendqihi2" + [(set (match_operand:HI 0 "register_operand" "=r") + (zero_extend:HI (match_operand:QI 1 "register_operand" "r")))] "" - "@ - clr %B0 - mov %A0,%A1\;clr %B0" - [(set_attr "length" "1,2") - (set_attr "cc" "set_n,set_n")]) + "#" + "reload_completed" + [(set (match_dup 2) (match_dup 1)) + (set (match_dup 3) (const_int 0))] + "unsigned int low_off = subreg_lowpart_offset (QImode, HImode); + unsigned int high_off = subreg_highpart_offset (QImode, HImode); + + operands[2] = simplify_gen_subreg (QImode, operands[0], HImode, low_off); + operands[3] = simplify_gen_subreg (QImode, operands[0], HImode, high_off); + ") -(define_insn "zero_extendqisi2" - [(set (match_operand:SI 0 "register_operand" "=r,r") - (zero_extend:SI (match_operand:QI 1 "register_operand" "0,*r")))] +(define_insn_and_split "zero_extendqisi2" + [(set (match_operand:SI 0 "register_operand" "=r") + (zero_extend:SI (match_operand:QI 1 "register_operand" "r")))] "" - "@ - clr %B0\;clr %C0\;clr %D0 - mov %A0,%A1\;clr %B0\;clr %C0\;clr %D0" - [(set_attr "length" "3,4") - (set_attr "cc" "set_n,set_n")]) + "#" + "reload_completed" + [(set (match_dup 2) (zero_extend:HI (match_dup 1))) + (set (match_dup 3) (const_int 0))] + "unsigned int low_off = subreg_lowpart_offset (HImode, SImode); + unsigned int high_off = subreg_highpart_offset (HImode, SImode); + + operands[2] = simplify_gen_subreg (HImode, operands[0], SImode, low_off); + operands[3] = simplify_gen_subreg (HImode, operands[0], SImode, high_off); + ") -(define_insn "zero_extendhisi2" - [(set (match_operand:SI 0 "register_operand" "=r,&r") - (zero_extend:SI (match_operand:HI 1 "register_operand" "0,*r")))] +(define_insn_and_split "zero_extendhisi2" + [(set (match_operand:SI 0 "register_operand" "=r") + (zero_extend:SI (match_operand:HI 1 "register_operand" "r")))] "" - "@ - clr %C0\;clr %D0 - {mov %A0,%A1\;mov %B0,%B1|movw %A0,%A1}\;clr %C0\;clr %D0" - [(set_attr_alternative "length" - [(const_int 2) - (if_then_else (eq_attr "mcu_have_movw" "yes") - (const_int 3) - (const_int 4))]) - (set_attr "cc" "set_n,set_n")]) + "#" + "reload_completed" + [(set (match_dup 2) (match_dup 1)) + (set (match_dup 3) (const_int 0))] + "unsigned int low_off = subreg_lowpart_offset (HImode, SImode); + unsigned int high_off = subreg_highpart_offset (HImode, SImode); + + operands[2] = simplify_gen_subreg (HImode, operands[0], SImode, low_off); + operands[3] = simplify_gen_subreg (HImode, operands[0], SImode, high_off); + ") + +(define_insn_and_split "zero_extendqidi2" + [(set (match_operand:DI 0 "register_operand" "=r") + (zero_extend:DI (match_operand:QI 1 "register_operand" "r")))] + "" + "#" + "reload_completed" + [(set (match_dup 2) (zero_extend:SI (match_dup 1))) + (set (match_dup 3) (const_int 0))] + "unsigned int low_off = subreg_lowpart_offset (SImode, DImode); + unsigned int high_off = subreg_highpart_offset (SImode, DImode); + + operands[2] = simplify_gen_subreg (SImode, operands[0], DImode, low_off); + operands[3] = simplify_gen_subreg (SImode, operands[0], DImode, high_off); + ") + +(define_insn_and_split "zero_extendhidi2" + [(set (match_operand:DI 0 "register_operand" "=r") + (zero_extend:DI (match_operand:HI 1 "register_operand" "r")))] + "" + "#" + "reload_completed" + [(set (match_dup 2) (zero_extend:SI (match_dup 1))) + (set (match_dup 3) (const_int 0))] + "unsigned int low_off = subreg_lowpart_offset (SImode, DImode); + unsigned int high_off = subreg_highpart_offset (SImode, DImode); + + operands[2] = simplify_gen_subreg (SImode, operands[0], DImode, low_off); + operands[3] = simplify_gen_subreg (SImode, operands[0], DImode, high_off); + ") + +(define_insn_and_split "zero_extendsidi2" + [(set (match_operand:DI 0 "register_operand" "=r") + (zero_extend:DI (match_operand:SI 1 "register_operand" "r")))] + "" + "#" + "reload_completed" + [(set (match_dup 2) (match_dup 1)) + (set (match_dup 3) (const_int 0))] + "unsigned int low_off = subreg_lowpart_offset (SImode, DImode); + unsigned int high_off = subreg_highpart_offset (SImode, DImode); + + operands[2] = simplify_gen_subreg (SImode, operands[0], DImode, low_off); + operands[3] = simplify_gen_subreg (SImode, operands[0], DImode, high_off); + ") ;;<=><=><=><=><=><=><=><=><=><=><=><=><=><=><=><=><=><=><=><=><=><=><=><=><=> ;; compare |