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2024-05-30Support vcond_mask_qiqi and friends.liuhongt1-0/+20
2024-05-30MIPS16: Mark $2/$3 as clobbered if GP is usedYunQiang Su1-1/+10
2024-05-29aarch64: Split aarch64_combinev16qi before RA [PR115258]Richard Sandiford2-16/+15
2024-05-29[to-be-committed] [RISC-V] Use pack to handle repeating constantsJeff Law2-1/+24
2024-05-29libgomp: Enable USM for AMD APUs and MI200 devicesTobias Burnus1-1/+1
2024-05-29i386: Fix ix86_option override after change [PR 113719]Hongyu Wang1-5/+5
2024-05-29Align tight&hot loop without considering max skipping bytes.liuhongt2-5/+153
2024-05-29Adjust generic loop alignment from 16:11:8 to 16 for Intel processorsHaochen Jiang1-1/+1
2024-05-28rs6000: Don't clobber return value when eh_return called [PR114846]Kewen Lin2-4/+18
2024-05-29Reduce cost of MEM (A + imm).liuhongt1-1/+17
2024-05-28i386: Improve access to _Atomic DImode location via XMM regs for SSE4.1 x86_3...Uros Bizjak1-8/+28
2024-05-28regenerate-opt-urls.py: fix transposed values for "vax" and "v850"David Malcolm2-31/+71
2024-05-28[to-be-committed] [RISC-V] Some basic patterns for zbkb code generationLyut Nersisyan3-3/+72
2024-05-28Fix predicate mismatch between vfcmaddcph's define_insn and define_expand.liuhongt1-5/+5
2024-05-28LoongArch: Guard REGNO with REG_P in loongarch_expand_conditional_move [PR115...Xi Ruoyao1-5/+12
2024-05-27Define which threading model is in use on WindowsTheShermanTanker1-5/+8
2024-05-27RISC-V: Fix missing boolean_expression in zmmul extensionLiao Shihua1-1/+1
2024-05-27vax: Fix descriptions of the FP format options [PR79646]Abe Skolnik1-4/+4
2024-05-26[to-be-committed][RISC-V] Reassociate constants in logical opsLyut Nersisyan1-0/+28
2024-05-27x86: Fix Logical Shift Issue in expand_vec_perm_psrlw_psllw_por [PR115146]Levy Hsu1-3/+3
2024-05-26[to-be-committed] [RISC-V] Try inverting for constant synthesisJeff Law1-1/+26
2024-05-26[to-be-committed][RISC-V] Generate nearby constant, then adjust to our final ...Jeff Law1-0/+20
2024-05-24[to-be-committed,v2,RISC-V] Use bclri in constant synthesisJeff Law3-7/+43
2024-05-23s390: Implement TARGET_NOCE_CONVERSION_PROFITABLE_P [PR109549]Stefan Schulze Frielinghaus1-0/+32
2024-05-22AARCH64: Add Qualcomnm oryon-1 coreAndrew Pinski2-1/+6
2024-05-22aarch64: Fold vget_high_* intrinsics to BIT_FIELD_REF [PR102171]Pengxuan Zheng4-149/+43
2024-05-22i386: Correct insn_cost of movabsq.Roger Sayle1-1/+2
2024-05-22i386: Disable ix86_expand_vecop_qihi2 when !TARGET_AVX512BWHaochen Jiang1-0/+7
2024-05-21RISC-V: avoid LUI based const mat in alloca epilogue expansionVineet Gupta1-7/+26
2024-05-21RISC-V: avoid LUI based const mat in prologue/epilogue expansion [PR/105733]Vineet Gupta3-3/+60
2024-05-21Use pblendw instead of pand to clear upper 16 bits.liuhongt1-4/+30
2024-05-20rs6000: Remove useless operands[3]Kewen Lin1-3/+0
2024-05-20rs6000: Remove useless entries in rregKewen Lin1-5/+1
2024-05-20rs6000: Drop useless vector_{load,store}_<mode> definesKewen Lin1-14/+0
2024-05-20rs6000: Clean up TF and TD check with FLOAT128_2REG_PKewen Lin1-1/+1
2024-05-20rs6000: Add assert !TARGET_VSX if !TARGET_ALTIVEC and strip a useless checkKewen Lin1-2/+3
2024-05-20rs6000: Fix ICE on IEEE128 long double without vsx [PR114402]Kewen Lin1-2/+2
2024-05-20aarch64: Fold vget_low_* intrinsics to BIT_FIELD_REF [PR102171]Pengxuan Zheng4-131/+62
2024-05-20AArch64: Improve costing of ctzWilco Dijkstra1-4/+18
2024-05-20AArch64: Fix printing of 2-instruction alternativesWilco Dijkstra1-2/+2
2024-05-20aarch64: Further renaming of generic codeAjit Kumar Agarwal1-35/+36
2024-05-20Regenerate riscv.opt.urls and i386.opt.urlsMark Wielaard2-15/+3
2024-05-20aarch64: Preparatory patch to place target independent and dependent changed ...Ajit Kumar Agarwal1-182/+373
2024-05-20MIPS: Remove -m(no-)lra optionYunQiang Su4-39/+3
2024-05-20i386: Remove Xeon Phi ISA supportHaochen Jiang23-2250/+63
2024-05-19[to-be-committed][RISC-V][PR target/115142] Do not create invalidate shift-ad...Jeff Law1-0/+1
2024-05-19nvptx: Correct pattern for popcountdi2 insn in nvptx.md.Roger Sayle1-3/+10
2024-05-18RISC-V: Implement -m{,no}fence-tsoPalmer Dabbelt2-1/+5
2024-05-18[to-be-committed,RISC-V] Improve some shift-add sequencesJeff Law1-0/+56
2024-05-18RISC-V: Fix "Nan-box the result of movbf on soft-bf16"Xiao Zeng2-23/+11
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