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| author | Levy Hsu <admin@levyhsu.com> | 2024-05-21 12:47:21 +0930 |
|---|---|---|
| committer | Levy Hsu <admin@levyhsu.com> | 2024-05-27 10:40:57 +0800 |
| commit | 0022064649d0ec40e97df24279c48842e278fedc (patch) | |
| tree | 22e368805b2ebeec45642be6ec593429a73ecb76 /gcc/config | |
| parent | 5d99cf74c9f748c93ea218eca9bd2f08edfb2a88 (diff) | |
| download | gcc-0022064649d0ec40e97df24279c48842e278fedc.zip gcc-0022064649d0ec40e97df24279c48842e278fedc.tar.gz gcc-0022064649d0ec40e97df24279c48842e278fedc.tar.bz2 | |
x86: Fix Logical Shift Issue in expand_vec_perm_psrlw_psllw_por [PR115146]
Replaced arithmetic shifts with logical shifts in expand_vec_perm_psrlw_psllw_por to avoid sign bit extension issues. Also corrected gen_vlshrv8hi3 to gen_lshrv8hi3 and gen_vashlv8hi3 to gen_ashlv8hi3.
Co-authored-by: H.J. Lu <hjl.tools@gmail.com>
gcc/ChangeLog:
PR target/115146
* config/i386/i386-expand.cc (expand_vec_perm_psrlw_psllw_por): Replace arithmatic shift
gen_ashrv4hi3 with logic shift gen_lshrv4hi3.
Replace gen_vlshrv8hi3 with gen_lshrv8hi3 and gen_vashlv8hi3 with gen_ashlv8hi3.
gcc/testsuite/ChangeLog:
PR target/115146
* g++.target/i386/pr107563-a.C: Append '-mno-sse3' to compile option
to avoid test failure on hosts with SSE3 support.
* g++.target/i386/pr107563-b.C: Append '-mno-sse3' to compile option
to avoid test failure on hosts with SSE3 support.
* gcc.target/i386/pr115146.c: New test.
Diffstat (limited to 'gcc/config')
| -rw-r--r-- | gcc/config/i386/i386-expand.cc | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/gcc/config/i386/i386-expand.cc b/gcc/config/i386/i386-expand.cc index ec402a7..215a998 100644 --- a/gcc/config/i386/i386-expand.cc +++ b/gcc/config/i386/i386-expand.cc @@ -22055,14 +22055,14 @@ expand_vec_perm_psrlw_psllw_por (struct expand_vec_perm_d *d) if (!TARGET_MMX_WITH_SSE) return false; mode = V4HImode; - gen_shr = gen_ashrv4hi3; + gen_shr = gen_lshrv4hi3; gen_shl = gen_ashlv4hi3; gen_or = gen_iorv4hi3; break; case E_V16QImode: mode = V8HImode; - gen_shr = gen_vlshrv8hi3; - gen_shl = gen_vashlv8hi3; + gen_shr = gen_lshrv8hi3; + gen_shl = gen_ashlv8hi3; gen_or = gen_iorv8hi3; break; default: return false; |