riscv-gnu-toolchain/gcc.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2022-01-07	RISC-V: Minimal support of vector extensions	Kito Cheng	2	-0/+39
2022-01-03	Update copyright years.	Jakub Jelinek	28	-28/+28
2021-12-04	RISC-V: Add implied defines of Zk, Zkn and Zks	SiYu Wu	1	-1/+15
2021-12-04	RISC-V: Add option defines for Scalar Cryptography	SiYu Wu	2	-0/+25
2021-11-03	RISC-V: Fix register class subset checks for CLASS_MAX_NREGS	Maciej W. Rozycki	1	-2/+2
2021-11-02	RISC-V: Fix build errors with shNadd/shNadd.uw patterns in zba cost model	Maciej W. Rozycki	1	-3/+2
2021-10-28	RISC-V: Fix wrong predicator for zero_extendsidi2_internal pattern	Kito Cheng	1	-1/+1
2021-10-28	RISC-V: Handle zi* extension correctly for arch-canonicalize script	Kito Cheng	1	-1/+1
2021-10-25	RISC-V: Cost model for ZBS extension.	Kito Cheng	1	-0/+47
2021-10-25	RISC-V: Implement instruction patterns for ZBS extension.	Jim Wilson	4	-2/+165
2021-10-25	RISC-V: Use li and rori to load constants.	Jim Wilson	1	-0/+41
2021-10-25	RISC-V: Cost model for zbb extension.	Kito Cheng	1	-0/+17
2021-10-25	RISC-V: Implement instruction patterns for ZBB extension.	Jim Wilson	2	-5/+180
2021-10-25	RISC-V: Cost model for zba extension.	Kito Cheng	1	-0/+81
2021-10-25	RISC-V: Implement instruction patterns for ZBA extension.	Jim Wilson	2	-4/+86
2021-10-25	RISC-V: Minimal support of bitmanip extension	Kito Cheng	2	-0/+13
2021-10-08	Come up with OPTION_SET_P macro.	Martin Liska	1	-5/+6
2021-09-28	RISC-V: Pattern name fix mul3_highpart -> smul3_highpart.	Geng Qi	1	-5/+5
2021-08-16	RISC-V: Allow multi-lib build with different code model	Kito Cheng	1	-30/+56
2021-07-13	docs: Add 'S' to Machine Constraints for RISC-V	Kito Cheng	1	-2/+1
2021-06-22	RISC-V: Add tune info for T-HEAD C906.	Jojo R	1	-0/+14
2021-05-25	RISC-V: Pass -mno-relax to assembler	Kito Cheng	1	-0/+1
2021-05-18	Use startswith in targets.	Martin Liska	1	-1/+1
2021-05-05	RISC-V: Generate helpers for cbranch4.	Christoph Muellner	2	-12/+5
2021-04-29	RISC-V: For '-march' and '-mabi' options, add 'Negative' property mentions it...	Geng Qi	1	-2/+2
2021-04-29	RISC-V: Add patterns for builtin overflow.	LevyHsu	3	-0/+257
2021-04-14	d: Add TARGET_D_REGISTER_CPU_TARGET_INFO	Iain Buclaw	3	-1/+49
2021-03-26	d: Define IN_TARGET_CODE in all machine-specific D language files.	Iain Buclaw	1	-0/+2
2021-03-23	RISC-V: Fix riscv_subword() for big endian	Marcus Comstedt	1	-1/+1
2021-03-23	RISC-V: Fix matches against subreg with a bytenum of 0 in riscv.md	Marcus Comstedt	2	-35/+40
2021-03-23	RISC-V: Fix trampoline generation on big endian	Marcus Comstedt	1	-4/+15
2021-03-23	RISC-V: Add riscv{32,64}be with big endian as default	Marcus Comstedt	5	-3/+14
2021-03-23	RISC-V: Support -mlittle-endian and -mbig-endian	Marcus Comstedt	5	-2/+18
2021-03-22	PR target/99702: Check RTL type before get value	Kito Cheng	1	-1/+1
2021-03-19	PR target/99314: Fix integer signedness issue for cpymem pattern expansion.	Sinan Lin	1	-11/+13
2021-02-13	RISC-V: Avoid zero/sign extend for volatile loads. Fix for 97417.	Levy Hsu	2	-7/+49
2021-02-13	RISC-V: Shorten memrefs improvement, partial fix 97417.	Jim Wilson	1	-8/+11
2021-01-19	RISC-V: The 'multilib-generator' enhancement.	Geng Qi	2	-6/+20
2021-01-08	RISC-V: Implement new style of architecture extension test macros.	Kito Cheng	2	-0/+37
2021-01-08	RISC-V: Move class riscv_subset_list and riscv_subset_t to riscv-protos.h	Kito Cheng	2	-1/+93
2021-01-04	Update copyright years.	Jakub Jelinek	26	-26/+26
2020-12-24	RISC-V: Fix python3 compatibility for multilib-generator	Kito Cheng	1	-1/+1
2020-12-16	opts: Remove all usages of Report keyword.	Martin Liska	1	-11/+11
2020-12-10	RISC-V: Explicitly call python when using multilib generator	Simon Cook	1	-1/+2
2020-12-03	RISC-V: Canonicalize --with-arch	Kito Cheng	2	-75/+110
2020-11-30	RISC-V: Always define MULTILIB_DEFAULTS	Kito Cheng	2	-51/+9
2020-11-18	RISC-V: Support version controling for ISA standard extensions	Kito Cheng	3	-1/+35
2020-11-18	RISC-V: Support zicsr and zifencei extension for -march.	Kito Cheng	3	-2/+12
2020-11-13	PR target/97682 - Fix to reuse t1 register between call address and epilogue.	Monk Chiang	2	-12/+17
2020-11-13	Asan changes for RISC-V.	Jim Wilson	1	-0/+16