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| author | SiYu Wu <siyu@isrc.iscas.ac.cn> | 2021-11-22 16:19:09 +0800 |
|---|---|---|
| committer | Kito Cheng <kito.cheng@sifive.com> | 2021-12-04 00:10:26 +0800 |
| commit | add31efdc7b0aa869cb9d83f40e274e864072b25 (patch) | |
| tree | 714eaf82d8558b44bc014670d6ede53deebeb8bd /gcc/config/riscv | |
| parent | 06f2e7d49fc6341ea0128ccd83fd13705dd2c523 (diff) | |
| download | gcc-add31efdc7b0aa869cb9d83f40e274e864072b25.zip gcc-add31efdc7b0aa869cb9d83f40e274e864072b25.tar.gz gcc-add31efdc7b0aa869cb9d83f40e274e864072b25.tar.bz2 | |
RISC-V: Add option defines for Scalar Cryptography
gcc/ChangeLog:
2021-11-21 SiYu Wu <siyu@isrc.iscas.ac.cn>
* common/config/riscv/riscv-common.c (riscv_ext_version_table):
Add zbk* and zk*.
* config/riscv/riscv-opts.h (MASK_ZBKB): New.
(MASK_ZBKC): Ditto.
(MASK_ZBKX): Ditto.
(MASK_ZKNE): Ditto.
(MASK_ZKND): Ditto.
(MASK_ZKNH): Ditto.
(MASK_ZKR): Ditto.
(MASK_ZKSED): Ditto.
(MASK_ZKSH): Ditto.
(MASK_ZKT): Ditto.
(TARGET_ZBKB): Ditto.
(TARGET_ZBKC): Ditto.
(TARGET_ZBKX): Ditto.
(TARGET_ZKNE): Ditto.
(TARGET_ZKND): Ditto.
(TARGET_ZKNH): Ditto.
(TARGET_ZKR): Ditto.
(TARGET_ZKSED): Ditto.
(TARGET_ZKSH): Ditto.
(TARGET_ZKT): Ditto.
* config/riscv/riscv.opt (riscv_zk_subext): New.
Diffstat (limited to 'gcc/config/riscv')
| -rw-r--r-- | gcc/config/riscv/riscv-opts.h | 22 | ||||
| -rw-r--r-- | gcc/config/riscv/riscv.opt | 3 |
2 files changed, 25 insertions, 0 deletions
diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h index 2efc4b8..f65ff67 100644 --- a/gcc/config/riscv/riscv-opts.h +++ b/gcc/config/riscv/riscv-opts.h @@ -83,4 +83,26 @@ enum stack_protector_guard { #define TARGET_ZBC ((riscv_zb_subext & MASK_ZBC) != 0) #define TARGET_ZBS ((riscv_zb_subext & MASK_ZBS) != 0) +#define MASK_ZBKB (1 << 0) +#define MASK_ZBKC (1 << 1) +#define MASK_ZBKX (1 << 2) +#define MASK_ZKNE (1 << 3) +#define MASK_ZKND (1 << 4) +#define MASK_ZKNH (1 << 5) +#define MASK_ZKR (1 << 6) +#define MASK_ZKSED (1 << 7) +#define MASK_ZKSH (1 << 8) +#define MASK_ZKT (1 << 9) + +#define TARGET_ZBKB ((riscv_zk_subext & MASK_ZBKB) != 0) +#define TARGET_ZBKC ((riscv_zk_subext & MASK_ZBKC) != 0) +#define TARGET_ZBKX ((riscv_zk_subext & MASK_ZBKX) != 0) +#define TARGET_ZKNE ((riscv_zk_subext & MASK_ZKNE) != 0) +#define TARGET_ZKND ((riscv_zk_subext & MASK_ZKND) != 0) +#define TARGET_ZKNH ((riscv_zk_subext & MASK_ZKNH) != 0) +#define TARGET_ZKR ((riscv_zk_subext & MASK_ZKR) != 0) +#define TARGET_ZKSED ((riscv_zk_subext & MASK_ZKSED) != 0) +#define TARGET_ZKSH ((riscv_zk_subext & MASK_ZKSH) != 0) +#define TARGET_ZKT ((riscv_zk_subext & MASK_ZKT) != 0) + #endif /* ! GCC_RISCV_OPTS_H */ diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt index 15bf89e..6170009 100644 --- a/gcc/config/riscv/riscv.opt +++ b/gcc/config/riscv/riscv.opt @@ -198,6 +198,9 @@ int riscv_zi_subext TargetVariable int riscv_zb_subext +TargetVariable +int riscv_zk_subext + Enum Name(isa_spec_class) Type(enum riscv_isa_spec_class) Supported ISA specs (for use with the -misa-spec= option): |