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path: root/gcc/config/riscv/riscv.c
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2022-01-17Rename .c files to .cc files.Martin Liska1-5783/+0
2022-01-03Update copyright years.Jakub Jelinek1-1/+1
2021-11-03RISC-V: Fix register class subset checks for CLASS_MAX_NREGSMaciej W. Rozycki1-2/+2
2021-11-02RISC-V: Fix build errors with shNadd/shNadd.uw patterns in zba cost modelMaciej W. Rozycki1-3/+2
2021-10-25RISC-V: Cost model for ZBS extension.Kito Cheng1-0/+47
2021-10-25RISC-V: Implement instruction patterns for ZBS extension.Jim Wilson1-2/+33
2021-10-25RISC-V: Use li and rori to load constants.Jim Wilson1-0/+41
2021-10-25RISC-V: Cost model for zbb extension.Kito Cheng1-0/+17
2021-10-25RISC-V: Cost model for zba extension.Kito Cheng1-0/+81
2021-10-08Come up with OPTION_SET_P macro.Martin Liska1-5/+6
2021-06-22RISC-V: Add tune info for T-HEAD C906.Jojo R1-0/+14
2021-05-18Use startswith in targets.Martin Liska1-1/+1
2021-05-05RISC-V: Generate helpers for cbranch4.Christoph Muellner1-4/+1
2021-04-29RISC-V: Add patterns for builtin overflow.LevyHsu1-0/+8
2021-03-23RISC-V: Fix riscv_subword() for big endianMarcus Comstedt1-1/+1
2021-03-23RISC-V: Fix trampoline generation on big endianMarcus Comstedt1-4/+15
2021-03-23RISC-V: Add riscv{32,64}be with big endian as defaultMarcus Comstedt1-0/+5
2021-03-22PR target/99702: Check RTL type before get valueKito Cheng1-1/+1
2021-03-19PR target/99314: Fix integer signedness issue for cpymem pattern expansion.Sinan Lin1-11/+13
2021-02-13RISC-V: Avoid zero/sign extend for volatile loads. Fix for 97417.Levy Hsu1-0/+22
2021-02-13RISC-V: Shorten memrefs improvement, partial fix 97417.Jim Wilson1-8/+11
2021-01-04Update copyright years.Jakub Jelinek1-1/+1
2020-11-13PR target/97682 - Fix to reuse t1 register between call address and epilogue.Monk Chiang1-11/+12
2020-11-13Asan changes for RISC-V.Jim Wilson1-0/+16
2020-10-15RISC-V: Add support for -mcpu option.Kito Cheng1-45/+52
2020-07-31RISC-V: Add support for TLS stack protector canary accessCooper Qu1-0/+47
2020-06-16RISC-V: Fix ICE on riscv_gpr_save_operation_p [PR95683]Kito Cheng1-1/+4
2020-06-15RISC-V: Suppress warning for signed and unsigned integer comparison.Kito Cheng1-3/+3
2020-06-10RISC-V: Unify the output asm pattern between gpr_save and gpr_restore pattern.Kito Cheng1-15/+1
2020-06-10RISC-V: Describe correct USEs for gpr_save pattern [PR95252]Kito Cheng1-2/+81
2020-05-12RISC-V: Make unique SECCAT_SRODATA names start with .srodata (not .sdata2)Keith Packard1-0/+40
2020-05-12RISC-V: Add shorten_memrefs pass.Craig Blackmore1-5/+99
2020-03-04PR target/93995 ICE in patch_jump_insn, at cfgrtl.c:1290 on riscv64-linux-gnuKito Cheng1-3/+4
2020-02-24RISC-V: Adjust floating point code gen for LTGT compareKito Cheng1-3/+14
2020-02-19RISC-V: Using fmv.x.w/fmv.w.x rather than fmv.x.s/fmv.s.xKito Cheng1-2/+2
2020-01-21riscv: Fix up riscv_rtx_costs for RTL checking (PR target/93333)Jakub Jelinek1-1/+4
2020-01-21RISC-V: Disallow regrenme if the TO register never used before for interrupt ...Kito Cheng1-0/+13
2020-01-09re PR inline-asm/93202 ([RISCV] ICE when using inline asm 'h' operand modifier)Jakub Jelinek1-1/+2
2020-01-08RISC-V: Disable use of TLS copy relocs.Jim Wilson1-0/+3
2020-01-01Update copyright years.Jakub Jelinek1-1/+1
2019-11-19Initialize a variable due to -Wmaybe-uninitialized.Martin Liska1-1/+1
2019-10-28gcc/riscv: Add a mechanism to remove some calls to _riscv_save_0Andrew Burgess1-0/+13
2019-10-16RISC-V: Include more registers in SIBCALL_REGS.Andrew Burgess1-3/+3
2019-09-18RISC-V: Fix more splitters accidentally calling gen_reg_rtx.Jim Wilson1-18/+28
2019-09-10Add call_used_or_fixed_reg_pRichard Sandiford1-5/+6
2019-09-06RISC-V: Re-enable -msave-restore for shared libraries.Jim Wilson1-10/+0
2019-08-30RISC-V: Disable -msave-restore for shared libraries.Jim Wilson1-0/+10
2019-08-20Use function_arg_info for TARGET_FUNCTION_ARG_ADVANCERichard Sandiford1-5/+4
2019-08-20Use function_arg_info for TARGET_FUNCTION_(INCOMING_)ARGRichard Sandiford1-4/+3
2019-08-20Use function_arg_info for TARGET_SETUP_INCOMING_ARGSRichard Sandiford1-4/+5