riscv-gnu-toolchain/gcc.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2024-12-07	Revert "RISC-V: Add const to function_shape::get_name [NFC]"	Kito Cheng	1	-2/+2
2024-12-05	RISC-V: Add const to function_shape::get_name [NFC]	Kito Cheng	1	-2/+2
2024-12-02	RISC-V: Add intrinsics support for SiFive Xsfvfnrclipxfqf extensions.	yulong	1	-0/+7
2024-11-29	RISC-V: Add intrinsics support for SiFive Xsfvqmaccqoq/dod extensions.	yulong	1	-0/+14
2024-08-06	RISC-V: Fix typos in code	Patrick O'Neill	1	-2/+2
2024-08-06	RISC-V: Fix comment typos	Patrick O'Neill	1	-3/+3
2024-07-15	RISC-V: Add Zvfbfmin and Zvfbfwma intrinsic	Feng Wang	1	-10/+24
2024-07-15	RISC-V: Add vector type of BFloat16 format	Feng Wang	1	-0/+1
2024-04-08	RISC-V: Refine the error msg for RVV intrinisc required ext	Pan Li	1	-3/+72
2024-01-18	RISC-V: Add support for xtheadvector-specific intrinsics.	Jun Sha (Joshua)	1	-0/+3
2024-01-03	Update copyright years.	Jakub Jelinek	1	-1/+1
2023-12-19	RISC-V: Add required_extensions in function_group	Feng Wang	1	-0/+46
2023-12-14	Revert "RISC-V: Add avail interface into function_group_info"	Feng Wang	1	-10/+0
2023-12-12	RISC-V: Add avail interface into function_group_info	Feng Wang	1	-0/+10
2023-11-06	RISC-V: Implement RESOLVE_OVERLOADED_BUILTIN for RVV intrinsic	xuli	1	-1/+26
2023-06-29	RISC-V: Allow rounding mode control for RVV floating-point add	Pan Li	1	-0/+4
2023-06-01	RISC-V: Introduce vfloat16m{f}*_t and their machine mode.	Pan Li	1	-0/+1
2023-05-17	RISC-V: Introduce rounding mode operand into fixed-point intrinsics	Juzhe-Zhong	1	-0/+18
2023-05-08	RISC-V: Fix ugly && incorrect codes of RVV auto-vectorization	Juzhe-Zhong	1	-3/+0
2023-05-06	RISC-V: autovec: Export policy functions to global scope	Michael Collison	1	-0/+3
2023-05-03	RISC-V: Support segment intrinsics	Ju-Zhe Zhong	1	-0/+1
2023-05-03	RISC-V: Add tuple type vget/vset intrinsics	Ju-Zhe Zhong	1	-0/+11
2023-05-03	RISC-V: Add tuple types support	Ju-Zhe Zhong	1	-0/+1
2023-04-12	RISC-V: Fix supporting data type according to RVV ISA. [PR109479]	Ju-Zhe Zhong	1	-1/+2
2023-03-10	RISC-V: Add fault first load C/C++ support	Ju-Zhe Zhong	1	-0/+25
2023-03-05	RISC-V: Add RVV misc intrinsic support	Ju-Zhe Zhong	1	-32/+87
2023-03-05	RISC-V: Add scalar move support and fix VSETVL bugs	Ju-Zhe Zhong	1	-0/+10
2023-02-22	RISC-V: Add RVV reduction C/C++ intrinsics support	Ju-Zhe Zhong	1	-1/+3
2023-02-22	RISC-V: Add floating-point RVV C/C++ api	Ju-Zhe Zhong	1	-0/+12
2023-02-15	RISC-V: Finish all integer C/C++ intrinsics	Ju-Zhe Zhong	1	-0/+2
2023-02-15	RISC-V: Add integer compare C/C++ intrinsic support	Ju-Zhe Zhong	1	-0/+9
2023-02-12	RISC-V: Add vmadc/vmsbc C/C++ API support	Ju-Zhe Zhong	1	-0/+11
2023-02-12	RISC-V: Add vadc/vsbc C/C++ API support	Ju-Zhe Zhong	1	-0/+12
2023-02-12	RISC-V: Add integer widening instructions	Ju-Zhe Zhong	1	-0/+3
2023-02-12	RISC-V: Add vmulh C/C++ support	Ju-Zhe Zhong	1	-0/+3
2023-02-12	RISC-V: Add vsext/vzext C/C++ intrinsic support	Ju-Zhe Zhong	1	-0/+3
2023-02-01	RISC-V: Add integer binary vv C/C++ API support	Ju-Zhe Zhong	1	-0/+1
2023-01-31	RISC-V: Add indexed loads/stores C/C++ intrinsic support	Ju-Zhe Zhong	1	-0/+36
2023-01-27	RISC-V: Fix inferior codegen for vse intrinsics.	Ju-Zhe Zhong	1	-4/+4
2023-01-16	Update copyright years.	Jakub Jelinek	1	-1/+1
2022-12-23	RISC-V: Support vle.v/vse.v intrinsics	Ju-Zhe Zhong	1	-0/+65
2022-10-31	RISC-V: Change constexpr back to CONSTEXPR	Ju-Zhe Zhong	1	-1/+1
2022-10-24	RISC-V: Replace CONSTEXPR with constexpr	Ju-Zhe Zhong	1	-1/+1
2022-10-21	RISC-V: Add RVV intrinsic basic framework.	Ju-Zhe Zhong	1	-0/+363
2022-10-12	RISC-V: Remove TUPLE size macro define. [NFC]	Ju-Zhe Zhong	1	-3/+0
2022-10-12	RISC-V: Apply clang-format for riscv-vector-builtins.* [NFC]	Ju-Zhe Zhong	1	-2/+1
2022-10-12	RISC-V: Refine register_builtin_types function. [NFC]	Ju-Zhe Zhong	1	-0/+10
2022-10-12	RISC-V: Move function place to make it looks better. [NFC]	Ju-Zhe Zhong	1	-19/+0
2022-10-11	RISC-V: move struct vector_type_info from .h to .cc and change "user_name" ...	Ju-Zhe Zhong	1	-18/+2
2022-10-05	RISC-V: Introduce RVV header to enable builtin types	Ju-Zhe Zhong	1	-8/+5