riscv-gnu-toolchain/gcc.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
4 days	RISC-V: fix const interleaved stepped vector with a scalar pattern	Vineet Gupta	1	-3/+3
6 days	RISC-V: Implement the MASK_LEN_STRIDED_LOAD{STORE}	Pan Li	1	-0/+52
2024-10-21	RISC-V: Implement vector SAT_TRUNC for signed integer	Pan Li	1	-0/+46
2024-10-19	[PATCH 4/7] RISC-V: Honour -mrvv-max-lmul in riscv_vector::expand_block_move	Craig Blackmore	1	-0/+12
2024-10-12	RISC-V: Implement vector SAT_SUB for signed integer	Pan Li	1	-0/+9
2024-09-18	RISC-V: Implement SAT_ADD for signed integer vector	Pan Li	1	-0/+9
2024-08-27	RISC-V: Move helper functions above expand_const_vector	Patrick O'Neill	1	-66/+66
2024-08-27	RISC-V: Allow non-duplicate bool patterns in expand_const_vector	Patrick O'Neill	1	-15/+8
2024-08-27	RISC-V: Handle 0.0 floating point pattern costing to match const_vector expander	Patrick O'Neill	1	-1/+10
2024-08-27	RISC-V: Emit costs for bool and stepped const vectors	Patrick O'Neill	1	-52/+1
2024-08-27	RISC-V: Handle case when constant vector construction target rtx is not a reg...	Patrick O'Neill	1	-32/+41
2024-08-27	RISC-V: Fix vid const vector expander for non-npatterns size steps	Patrick O'Neill	1	-6/+42
2024-08-23	RISC-V: Use encoded nelts when calling repeating_sequence_p	Patrick O'Neill	1	-7/+3
2024-08-13	RISC-V: Fix non-obvious comment typos	Patrick O'Neill	1	-3/+3
2024-08-06	RISC-V: Fix typos in code	Patrick O'Neill	1	-5/+5
2024-08-06	RISC-V: Fix comment typos	Patrick O'Neill	1	-12/+12
2024-07-08	RISC-V: Implement .SAT_TRUNC for vector unsigned int	Pan Li	1	-0/+46
2024-06-18	RISC-V: Move mode assertion out of conditional branch in emit_insn	Edwin Lu	1	-6/+19
2024-06-11	RISC-V: Implement .SAT_SUB for unsigned vector int	Pan Li	1	-5/+14
2024-05-31	RISC-V: Remove dead perm series code and document.	Robin Dapp	1	-22/+4
2024-05-31	RISC-V: Use widening shift for scatter/gather if applicable.	Robin Dapp	1	-13/+29
2024-05-18	RISC-V: Implement IFN SAT_ADD for both the scalar and vector	Pan Li	1	-0/+19
2024-04-30	This is almost exclusively Jivan's work. His original post:	Jivan Hakobyan	1	-1/+1
2024-03-20	RISC-V: Introduce option -mrvv-max-lmul for RVV autovec	demin.han	1	-1/+1
2024-03-07	RISC-V: Refactor expand_vec_cmp [NFC]	demin.han	1	-30/+14
2024-03-01	RISC-V: Introduce gcc option mrvv-vector-bits for RVV	Pan Li	1	-8/+8
2024-02-23	RISC-V: Fix vec_init for simple sequences [PR114028].	Robin Dapp	1	-1/+24
2024-02-03	RISC-V: Expand VLMAX scalar move in reduction	Juzhe-Zhong	1	-5/+7
2024-01-22	RISC-V: Lower vmv.v.x (avl = 1) into vmv.s.x	Juzhe-Zhong	1	-0/+12
2024-01-18	RISC-V: Handle differences between XTheadvector and Vector	Jun Sha (Joshua)	1	-1/+1
2024-01-10	RISC-V: Refine unsigned avg_floor/avg_ceil	Juzhe-Zhong	1	-0/+11
2024-01-06	RISC-V: Allow simplification non-vlmax with len = NUNITS reg to reg move	Juzhe-Zhong	1	-0/+23
2024-01-05	RISC-V: Clean up unused variable [NFC]	Kito Cheng	1	-5/+0
2024-01-03	Update copyright years.	Jakub Jelinek	1	-1/+1
2024-01-02	RISC-V: Add simplification of dummy len and dummy mask COND_LEN_xxx pattern	Juzhe-Zhong	1	-3/+8
2023-12-29	RISC-V: Disallow transformation into VLMAX AVL for cond_len_xxx when length i...	Juzhe-Zhong	1	-6/+15
2023-12-21	RISC-V: Optimize SELECT_VL codegen when length is known as smaller than VF	Juzhe-Zhong	1	-0/+10
2023-12-20	RISC-V: Bugfix for the const vector in single steps	Pan Li	1	-16/+95
2023-12-19	RISC-V: Refine some codes of expand_const_vector [NFC]	Juzhe-Zhong	1	-3/+3
2023-12-18	RISC-V: Bugfix for the RVV const vector	Pan Li	1	-1/+1
2023-12-15	RISC-V: Fix vmerge optimization bug in vec_perm vectorization	Juzhe-Zhong	1	-8/+51
2023-12-14	expmed: Use GET_MODE_PRECISION and expander's output mode.	Robin Dapp	1	-6/+8
2023-12-12	RISC-V: Move RVV POLY VALUE estimation from riscv.cc to riscv-v.cc[NFC]	Juzhe-Zhong	1	-0/+47
2023-12-11	RISC-V: Robostify shuffle index used by vrgather and fix regression	Juzhe-Zhong	1	-32/+48
2023-12-11	RISC-V: Recognize stepped series in expand_vec_perm_const.	Robin Dapp	1	-2/+64
2023-12-08	RISC-V: Support interleave vector with different step sequence	Juzhe-Zhong	1	-11/+137
2023-12-06	RISC-V: Block VLSmodes according to TARGET_MAX_LMUL and BITS_PER_RISCV_VECTOR	Juzhe-Zhong	1	-1/+15
2023-12-05	RISC-V: FAIL:g++.dg/torture/vshuf-v[2\|4]di.C -Os (execution test) on RV32	xuli	1	-1/+6
2023-12-05	RISC-V: Add blocker for gather/scatter auto-vectorization	Juzhe-Zhong	1	-0/+18
2023-11-28	RISC-V: Disallow poly (1,1) VLA SLP interleave vectorization	Juzhe-Zhong	1	-0/+9