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path: root/gcc/config/riscv/riscv-protos.h
AgeCommit message (Expand)AuthorFilesLines
2023-10-27RISC-V: Add rawmemchr expander.Robin Dapp1-0/+2
2023-10-27RISC-V: Add AVL propagation PASS for RVV auto-vectorizationJuzhe-Zhong1-0/+1
2023-10-25RISC-V: Export some functions from riscv-vsetvl to riscv-v[NFC]Juzhe-Zhong1-0/+8
2023-10-25RISC-V: Change MD attribute avl_type into avl_type_idx[NFC]Juzhe-Zhong1-0/+1
2023-10-23RISC-V: Add popcount fallback expander.Robin Dapp1-0/+1
2023-10-23RISC-V: Bugfix for merging undefined tmp register in mathPan Li1-0/+5
2023-10-21RISC-V: Support partial VLS mode when preference fixed-vlmax [PR111857]Pan Li1-0/+1
2023-10-16RISC-V: NFC: Move scalar block move expansion code into riscv-string.ccChristoph Müllner1-2/+3
2023-10-13RISC-V: Support FP lfloor/lfloorf auto vectorizationPan Li1-0/+2
2023-10-13RISC-V: Support FP lceil/lceilf auto vectorizationPan Li1-0/+2
2023-10-12RISC-V: Support FP lround/lroundf auto vectorizationPan Li1-0/+2
2023-10-11RISC-V: Fix incorrect index(offset) of gather/scatterJuzhe-Zhong1-0/+1
2023-10-11RISC-V: Support FP lrint/lrintf auto vectorizationPan Li1-0/+1
2023-10-02cpymem for RISC-V with v extensionJoern Rennecke1-0/+1
2023-10-01Make riscv_vector::legitimize_move adjust SRC in the caller.Joern Rennecke1-1/+1
2023-09-27RISC-V: Support FP roundeven auto-vectorizationPan Li1-0/+5
2023-09-27RISC-V: Support FP trunc auto-vectorizationPan Li1-0/+1
2023-09-26RISC-V: Support FP round auto-vectorizationPan Li1-0/+5
2023-09-26RISC-V: Support FP rint auto-vectorizationPan Li1-0/+1
2023-09-26RISC-V: Support FP nearbyint auto-vectorizationPan Li1-0/+2
2023-09-23RISC-V: Suport FP floor auto-vectorizationPan Li1-0/+5
2023-09-22RISC-V: Add VLS conditional patterns supportJuzhe-Zhong1-0/+3
2023-09-22RISC-V: Support combine cond extend and reduce sum to widen reduce sumLehua Ding1-0/+1
2023-09-22RISC-V: Split VLS avl_type from NONVLMAX avl_typeLehua Ding1-2/+19
2023-09-22RISC-V: Support ceil and ceilf auto-vectorizationPan Li1-0/+5
2023-09-19RISC-V: Refactor and cleanup fma patternsLehua Ding1-1/+1
2023-09-19RISC-V: Bugfix for scalar move with merged operandPan Li1-0/+4
2023-09-15RISC-V: Fix using wrong mode to get reduction insn vlmaxLehua Ding1-6/+6
2023-09-15RISC-V: Refactor expand_reduction and cleanup enum reduction_typeLehua Ding1-8/+1
2023-09-14RISC-V: Refactor vector reduction patternsLehua Ding1-1/+1
2023-09-12riscv: Add support for str(n)cmp inline expansionChristoph Müllner1-0/+1
2023-09-12riscv: Add support for strlen inline expansionChristoph Müllner1-0/+3
2023-09-11RISC-V: Remove redundant functionsJuzhe-Zhong1-2/+0
2023-09-11RISC-V: Add VLS modes VEC_PERM support[PR111311]Juzhe-Zhong1-0/+2
2023-09-06RISC-V: Part-3: Output .variant_cc directive for vector functionLehua Ding1-0/+3
2023-09-06RISC-V: Part-1: Select suitable vector registers for vector type args and ret...Lehua Ding1-0/+1
2023-09-05RISC-V: Export functions as global extern preparing for dynamic LMUL patch useJuzhe-Zhong1-0/+3
2023-09-01RISC-V: Adjust expand_cond_len_{unary,binop,op} apiLehua Ding1-2/+2
2023-08-31RISC-V: Change vsetvl tail and mask policy to default policyLehua Ding1-0/+3
2023-08-31RISC-V: Refactor and clean emit_{vlmax,nonvlmax}_xxx functionsLehua Ding1-34/+161
2023-08-30RISC-V: support cm.push cm.pop cm.popret in zcmpFei Gao1-0/+2
2023-08-29RISC-V: Refactor and clean expand_cond_len_{unop,binop,ternop}Lehua Ding1-10/+6
2023-08-26RISC-V: Support LEN_FOLD_EXTRACT_LAST auto-vectorizationJuzhe-Zhong1-0/+2
2023-08-25[PATCH v10] RISC-V: Add support for the Zfa extensionJin Ma1-0/+1
2023-08-23RISC-V: Add conditional unary neg/abs/not autovec patternsLehua Ding1-2/+5
2023-08-16RISC-V: Support MASK_LEN_{LOAD_LANES,STORE_LANES}Juzhe-Zhong1-0/+1
2023-08-10RISC-V: Refactor RVV frm_mode attr for rounding mode intrinsicPan Li1-0/+4
2023-08-08RISC-V: Support CALL conditional autovec patternsJuzhe-Zhong1-0/+5
2023-08-07[committed] [RISC-V] Handle more cases in riscv_expand_conditional_moveRaphael Zinsly1-1/+1
2023-07-31RISC-V: Return machine_mode rather than opt_machine_mode for get_mask_mode, NFCKito Cheng1-1/+1