diff options
| author | Lehua Ding <lehua.ding@rivai.ai> | 2023-08-25 15:50:15 +0800 |
|---|---|---|
| committer | Lehua Ding <lehua.ding@rivai.ai> | 2023-08-29 21:20:30 +0800 |
| commit | b3176bdc86c04da6545a4bd8e2fb7f38d3f2db8d (patch) | |
| tree | 915a2afe567f68b3163f497c63a22fe75371269b /gcc/config/riscv/riscv-protos.h | |
| parent | f2242694d4f868ec04c9766878762c5b466b0670 (diff) | |
| download | gcc-b3176bdc86c04da6545a4bd8e2fb7f38d3f2db8d.zip gcc-b3176bdc86c04da6545a4bd8e2fb7f38d3f2db8d.tar.gz gcc-b3176bdc86c04da6545a4bd8e2fb7f38d3f2db8d.tar.bz2 | |
RISC-V: Refactor and clean expand_cond_len_{unop,binop,ternop}
This patch refactors the codes of expand_cond_len_{unop,binop,ternop}.
Introduces a new unified function expand_cond_len_op to do the main thing.
The expand_cond_len_{unop,binop,ternop} functions only care about how
to pass the operands to the intrinsic patterns.
gcc/ChangeLog:
* config/riscv/autovec.md: Adjust
* config/riscv/riscv-protos.h (RVV_VUNDEF): Clean.
(get_vlmax_rtx): Exported.
* config/riscv/riscv-v.cc (emit_nonvlmax_fp_ternary_tu_insn): Deleted.
(emit_vlmax_masked_gather_mu_insn): Adjust.
(get_vlmax_rtx): New func.
(expand_load_store): Adjust.
(expand_cond_len_unop): Call expand_cond_len_op.
(expand_cond_len_op): New subroutine.
(expand_cond_len_binop): Call expand_cond_len_op.
(expand_cond_len_ternop): Call expand_cond_len_op.
(expand_lanes_load_store): Adjust.
Diffstat (limited to 'gcc/config/riscv/riscv-protos.h')
| -rw-r--r-- | gcc/config/riscv/riscv-protos.h | 16 |
1 files changed, 6 insertions, 10 deletions
diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h index 0e04702..4137bb1 100644 --- a/gcc/config/riscv/riscv-protos.h +++ b/gcc/config/riscv/riscv-protos.h @@ -181,25 +181,20 @@ namespace riscv_vector { #define RVV_VUNDEF(MODE) \ gen_rtx_UNSPEC (MODE, gen_rtvec (1, gen_rtx_REG (SImode, X0_REGNUM)), \ UNSPEC_VUNDEF) + +/* The value means the number of operands for insn_expander. */ enum insn_type { RVV_MISC_OP = 1, RVV_UNOP = 2, - RVV_UNOP_M = RVV_UNOP + 2, - RVV_UNOP_MU = RVV_UNOP + 2, - RVV_UNOP_TU = RVV_UNOP + 2, - RVV_UNOP_TUMU = RVV_UNOP + 2, + RVV_UNOP_MASK = RVV_UNOP + 2, RVV_BINOP = 3, - RVV_BINOP_MU = RVV_BINOP + 2, - RVV_BINOP_TU = RVV_BINOP + 2, - RVV_BINOP_TUMU = RVV_BINOP + 2, + RVV_BINOP_MASK = RVV_BINOP + 2, RVV_MERGE_OP = 4, RVV_CMP_OP = 4, RVV_CMP_MU_OP = RVV_CMP_OP + 2, /* +2 means mask and maskoff operand. */ RVV_TERNOP = 5, - RVV_TERNOP_MU = RVV_TERNOP + 1, - RVV_TERNOP_TU = RVV_TERNOP + 1, - RVV_TERNOP_TUMU = RVV_TERNOP + 1, + RVV_TERNOP_MASK = RVV_TERNOP + 1, RVV_WIDEN_TERNOP = 4, RVV_SCALAR_MOV_OP = 4, /* +1 for VUNDEF according to vector.md. */ RVV_SLIDE_OP = 4, /* Dest, VUNDEF, source and offset. */ @@ -260,6 +255,7 @@ void emit_vlmax_masked_mu_insn (unsigned, int, rtx *); void emit_scalar_move_insn (unsigned, rtx *, rtx = 0); void emit_nonvlmax_integer_move_insn (unsigned, rtx *, rtx); enum vlmul_type get_vlmul (machine_mode); +rtx get_vlmax_rtx (machine_mode); unsigned int get_ratio (machine_mode); unsigned int get_nf (machine_mode); machine_mode get_subpart_mode (machine_mode); |