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authorJuzhe-Zhong <juzhe.zhong@rivai.ai>2023-09-11 11:25:02 +0800
committerLehua Ding <lehua.ding@rivai.ai>2023-09-11 11:31:37 +0800
commitd05aac047e0643d5c32b706c4c3b12e13f35e19a (patch)
tree5d2518b44f50b0066b1090fa65dad86cbd616c3e /gcc/config/riscv/riscv-protos.h
parent4ab2520ec424fa097ec839f2cde33522b220e93a (diff)
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RISC-V: Add VLS modes VEC_PERM support[PR111311]
This patch add VLS modes VEC_PERM support which fix these following FAILs in https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111311: FAIL: gcc.dg/tree-ssa/forwprop-40.c scan-tree-dump-times optimized "BIT_FIELD_REF" 0 FAIL: gcc.dg/tree-ssa/forwprop-40.c scan-tree-dump-times optimized "BIT_INSERT_EXPR" 0 FAIL: gcc.dg/tree-ssa/forwprop-41.c scan-tree-dump-times optimized "BIT_FIELD_REF" 0 FAIL: gcc.dg/tree-ssa/forwprop-41.c scan-tree-dump-times optimized "BIT_INSERT_EXPR" 1 These FAILs are fixed after this patch. PR target/111311 gcc/ChangeLog: * config/riscv/autovec.md: Add VLS modes. * config/riscv/riscv-protos.h (cmp_lmul_le_one): New function. (cmp_lmul_gt_one): Ditto. * config/riscv/riscv-v.cc (cmp_lmul_le_one): Ditto. (cmp_lmul_gt_one): Ditto. * config/riscv/riscv.cc (riscv_print_operand): Add VLS modes. (riscv_vectorize_vec_perm_const): Ditto. * config/riscv/vector-iterators.md: Ditto. * config/riscv/vector.md: Ditto. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/partial/slp-1.c: Adapt test. * gcc.target/riscv/rvv/autovec/partial/slp-16.c: Ditto. * gcc.target/riscv/rvv/autovec/partial/slp-17.c: Ditto. * gcc.target/riscv/rvv/autovec/partial/slp-3.c: Ditto. * gcc.target/riscv/rvv/autovec/partial/slp-5.c: Ditto. * gcc.target/riscv/rvv/autovec/vls/compress-1.c: New test. * gcc.target/riscv/rvv/autovec/vls/compress-2.c: New test. * gcc.target/riscv/rvv/autovec/vls/compress-3.c: New test. * gcc.target/riscv/rvv/autovec/vls/compress-4.c: New test. * gcc.target/riscv/rvv/autovec/vls/compress-5.c: New test. * gcc.target/riscv/rvv/autovec/vls/compress-6.c: New test. * gcc.target/riscv/rvv/autovec/vls/merge-1.c: New test. * gcc.target/riscv/rvv/autovec/vls/merge-2.c: New test. * gcc.target/riscv/rvv/autovec/vls/merge-3.c: New test. * gcc.target/riscv/rvv/autovec/vls/merge-4.c: New test. * gcc.target/riscv/rvv/autovec/vls/merge-5.c: New test. * gcc.target/riscv/rvv/autovec/vls/merge-6.c: New test. * gcc.target/riscv/rvv/autovec/vls/merge-7.c: New test. * gcc.target/riscv/rvv/autovec/vls/perm-1.c: New test. * gcc.target/riscv/rvv/autovec/vls/perm-2.c: New test. * gcc.target/riscv/rvv/autovec/vls/perm-3.c: New test. * gcc.target/riscv/rvv/autovec/vls/perm-4.c: New test. * gcc.target/riscv/rvv/autovec/vls/perm-5.c: New test. * gcc.target/riscv/rvv/autovec/vls/perm-6.c: New test. * gcc.target/riscv/rvv/autovec/vls/perm-7.c: New test.
Diffstat (limited to 'gcc/config/riscv/riscv-protos.h')
-rw-r--r--gcc/config/riscv/riscv-protos.h2
1 files changed, 2 insertions, 0 deletions
diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h
index 6dbf6b9..46d77ef 100644
--- a/gcc/config/riscv/riscv-protos.h
+++ b/gcc/config/riscv/riscv-protos.h
@@ -500,6 +500,8 @@ opt_machine_mode vectorize_related_mode (machine_mode, scalar_mode,
unsigned int autovectorize_vector_modes (vec<machine_mode> *, bool);
hash_set<basic_block> get_all_predecessors (basic_block);
hash_set<basic_block> get_all_successors (basic_block);
+bool cmp_lmul_le_one (machine_mode);
+bool cmp_lmul_gt_one (machine_mode);
}
/* We classify builtin types into two classes: