riscv-gnu-toolchain/gcc.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2024-10-19	[PATCH][v5] RISC-V: add option -m(no-)autovec-segment	Greg McGary	1	-0/+5
2024-08-06	RISC-V: Fix comment typos	Patrick O'Neill	1	-3/+3
2024-06-05	RISC-V: Introduce -mvector-strict-align.	Robin Dapp	1	-3/+0
2024-04-08	RISC-V: Implement TLS Descriptors.	Tatsuyuki Ishi	1	-0/+6
2024-03-20	RISC-V: Introduce option -mrvv-max-lmul for RVV autovec	demin.han	1	-2/+2
2024-03-18	[PATCH] RISC-V: Add XiangShan Nanhu microarchitecture.	Chen Jiawei	1	-0/+1
2024-03-01	RISC-V: Introduce gcc option mrvv-vector-bits for RVV	Pan Li	1	-7/+8
2024-02-04	RISC-V: Support scheduling for sifive p400 series	Monk Chiang	1	-0/+1
2024-02-01	RISC-V: Support scheduling for sifive p600 series	Monk Chiang	1	-0/+1
2024-01-25	RISC-V: Add optim-no-fusion compile option [VSETVL PASS]	Juzhe-Zhong	1	-3/+5
2024-01-17	RISC-V: RVV: add toggle to control vsetvl pass behavior	Vineet Gupta	1	-0/+9
2024-01-03	Update copyright years.	Jakub Jelinek	1	-1/+1
2023-12-20	RISC-V: Support -mcmodel=large.	Kuan-Lin Chen	1	-0/+1
2023-12-04	RISC-V: Rename and unify stringop strategy handling.	Robin Dapp	1	-9/+9
2023-11-27	RISC-V: Initial RV64E and LP64E support	Tsukasa OI	1	-0/+1
2023-11-20	RISC-V: Implement -mmemcpy-strategy= options[PR112537]	xuli	1	-0/+12
2023-10-27	RISC-V: Move lmul calculation into macro	Juzhe-Zhong	1	-0/+4
2023-10-21	RISC-V: Support partial VLS mode when preference fixed-vlmax [PR111857]	Pan Li	1	-5/+0
2023-10-11	RISC-V: Add TARGET_MIN_VLEN_OPTS to fix the build	Kito Cheng	1	-0/+6
2023-10-09	RISC-V: Add initial pipeline description for an out-of-order core.	Robin Dapp	1	-1/+2
2023-10-09	RISC-V: Support movmisalign of RVV VLA modes	Juzhe-Zhong	1	-0/+3
2023-10-01	RISC-V:Optimize the MASK opt generation	Feng Wang	1	-217/+1
2023-09-07	RISC-V: Add support for 'XVentanaCondOps' reusing 'Zicond' support	Tsukasa OI	1	-0/+6
2023-09-05	RISC-V: Fix Dynamic LMUL compile option	Juzhe-Zhong	1	-1/+1
2023-09-01	RISC-V: Add dynamic LMUL compile option	Juzhe-Zhong	1	-1/+3
2023-08-28	RISC-V: __builtin_riscv_pause for all environment	Tsukasa OI	1	-0/+2
2023-08-25	[PATCH v10] RISC-V: Add support for the Zfa extension	Jin Ma	1	-0/+3
2023-08-14	RISC-V: Minimal support for ZC* extensions.	Jiawei	1	-0/+16
2023-08-12	RISC-V: Add TAREGT_VECTOR check into VLS modes	Juzhe-Zhong	1	-1/+2
2023-08-10	RISC-V: Add Ztso atomic mappings	Patrick O'Neill	1	-0/+4
2023-07-27	RISC-V: Enable basic VLS modes support	Juzhe-Zhong	1	-0/+4
2023-07-26	[PATCH 1/5] [RISC-V] Recognize Zicond extension	Xiao Zeng	1	-0/+3
2023-07-14	RISC-V: Recognized zihintntl extensions	Monk Chiang	1	-0/+2
2023-07-04	RISC-V: Add support for vector crypto extensions	Christoph Müllner	1	-0/+34
2023-06-01	RISC-V: Introduce vfloat16m{f}*_t and their machine mode.	Pan Li	1	-0/+4
2023-05-31	RISC-V: Add ZVFH extension to the -march= option	Pan Li	1	-0/+2
2023-05-29	RISC-V: Add ZVFHMIN extension to the -march= option	Pan Li	1	-2/+4
2023-05-17	RISC-V: Add mode switching target hook to insert rounding mode config for fix...	Juzhe-Zhong	1	-0/+8
2023-05-08	RISC-V: Handle multi-lib path correclty for linux	Kito Cheng	1	-0/+9
2023-04-25	RISC-V: Add auto-vectorization compile option for RVV	Ju-Zhe Zhong	1	-0/+15
2023-03-15	riscv: Add basic XThead* vendor extension support	Christoph Müllner	1	-0/+26
2023-01-16	Update copyright years.	Jakub Jelinek	1	-1/+1
2022-11-15	Revert "RISC-V: Add basic support for the Ventana-VT1 core"	Philipp Tomsich	1	-1/+1
2022-11-14	RISC-V: Add basic support for the Ventana-VT1 core	Philipp Tomsich	1	-1/+1
2022-11-02	RISC-V: Add Zawrs ISA extension support	Christoph Müllner	1	-0/+3
2022-10-27	RISC-V: Minimal support of z*inx extension.	Jiawei	1	-0/+10
2022-10-26	RISC-V: Recognized Svinval and Svnapot extensions	Monk Chiang	1	-0/+6
2022-09-05	RISC-V: Support Zmmul extension	LiaoShihua	1	-0/+3
2022-08-16	RISC-V: Support zfh and zfhmin extension	Kito Cheng	1	-0/+6
2022-05-24	RISC-V: Add mininal support for Zicbo[mzp]	ShiYulong	1	-0/+8