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authorRobin Dapp <rdapp.gcc@gmail.com>2024-05-28 21:19:26 +0200
committerRobin Dapp <rdapp@ventanamicro.com>2024-06-05 21:32:45 +0200
commit68b0742a49de7122d5023f0bf46460ff2fb3e3dd (patch)
treec8fcee27ef184ce63dbb27d1e42c45a3c1a37c00 /gcc/config/riscv/riscv-opts.h
parent3eb9f6eab9802d5ae65ead6b1f2ae6fe0833e06e (diff)
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RISC-V: Introduce -mvector-strict-align.
this patch disables movmisalign by default and introduces the -mno-vector-strict-align option to override it and re-enable movmisalign. For now, generic-ooo is the only uarch that supports misaligned vector access. The patch also adds a check_effective_target_riscv_v_misalign_ok to the testsuite which enables or disables the vector misalignment tests depending on whether the target under test can execute a misaligned vle32. Changes from v3: - Adressed Kito's comments. - Made -mscalar-strict-align a real alias. gcc/ChangeLog: * config/riscv/riscv-opts.h (TARGET_VECTOR_MISALIGN_SUPPORTED): Move from here... * config/riscv/riscv.h (TARGET_VECTOR_MISALIGN_SUPPORTED): ...to here and map to riscv_vector_unaligned_access_p. * config/riscv/riscv.opt: Add -mvector-strict-align. * config/riscv/riscv.cc (struct riscv_tune_param): Add vector_unaligned_access. (riscv_override_options_internal): Set riscv_vector_unaligned_access_p. * doc/invoke.texi: Document -mvector-strict-align. gcc/testsuite/ChangeLog: * lib/target-supports.exp: Add check_effective_target_riscv_v_misalign_ok. * gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul2-7.c: Add -mno-vector-strict-align. * gcc.dg/vect/costmodel/riscv/rvv/vla_vs_vls-10.c: Ditto. * gcc.dg/vect/costmodel/riscv/rvv/vla_vs_vls-11.c: Ditto. * gcc.dg/vect/costmodel/riscv/rvv/vla_vs_vls-12.c: Ditto. * gcc.dg/vect/costmodel/riscv/rvv/vla_vs_vls-8.c: Ditto. * gcc.dg/vect/costmodel/riscv/rvv/vla_vs_vls-9.c: Ditto. * gcc.target/riscv/rvv/autovec/vls/misalign-1.c: Ditto.
Diffstat (limited to 'gcc/config/riscv/riscv-opts.h')
-rw-r--r--gcc/config/riscv/riscv-opts.h3
1 files changed, 0 insertions, 3 deletions
diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h
index 1b2dd57..f58a07a 100644
--- a/gcc/config/riscv/riscv-opts.h
+++ b/gcc/config/riscv/riscv-opts.h
@@ -147,9 +147,6 @@ enum rvv_vector_bits_enum {
? 0 \
: 32 << (__builtin_popcount (opts->x_riscv_zvl_flags) - 1))
-/* TODO: Enable RVV movmisalign by default for now. */
-#define TARGET_VECTOR_MISALIGN_SUPPORTED 1
-
/* The maximmum LMUL according to user configuration. */
#define TARGET_MAX_LMUL \
(int) (rvv_max_lmul == RVV_DYNAMIC ? RVV_M8 : rvv_max_lmul)