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2024-11-19[RISC-V][PR target/117649] Fix branch on masked values splitterJeff Law1-1/+1
2024-11-19RISC-V: Tie MUL and DIV masks to the M extensionDimitar Dimitrov1-1/+5
2024-11-19RISC-V: Load VLS perm indices directly from memory.Robin Dapp1-2/+20
2024-11-18[committed][RISC-V][PR target/117595] Fix bogus use of simplify_gen_subregJeff Law2-2/+2
2024-11-18RISC-V: Add VLS modes to strided loads.Robin Dapp3-13/+256
2024-11-18RISC-V: Add else operand to masked loads [PR115336].Robin Dapp3-30/+53
2024-11-14[RISC-V][V2] Fix type on vector move patternsJeff Law1-2/+8
2024-11-13[PATCH] RISC-V: Bugfix for unrecognizable insn for XTheadVectorJin Ma1-2/+2
2024-11-13RISC-V: Implement TARGET_GENERATE_VERSION_DISPATCHER_BODY and TARGET_GET_FUNC...Yangyu Chen1-0/+587
2024-11-13RISC-V: Implement TARGET_MANGLE_DECL_ASSEMBLER_NAMEYangyu Chen1-0/+39
2024-11-13RISC-V: Implement TARGET_COMPARE_VERSION_PRIORITY and TARGET_OPTION_FUNCTION_...Yangyu Chen1-0/+127
2024-11-13RISC-V: Implement TARGET_OPTION_VALID_VERSION_ATTRIBUTE_PYangyu Chen4-13/+115
2024-11-13RISC-V: Implement riscv_minimal_hwprobe_feature_bitsYangyu Chen2-0/+49
2024-11-13RISC-V: Implement Priority syntax parser for Function Multi-VersioningYangyu Chen2-0/+27
2024-11-13Introduce TARGET_CLONES_ATTR_SEPARATOR for RISC-VYangyu Chen1-0/+5
2024-11-13RISC-V: Bugfix for max_sew_overlap_and_next_ratio_valid_for_prev_sew_p[pr117483]xuli1-2/+9
2024-11-12[RISC-V] Fix costing of LO_SUM expressionsXianmiao Qu1-1/+2
2024-11-12RISC-V: Add norelax function attributeyulong1-16/+28
2024-11-12[RISC-V] Drop undesirable two instruction macc alternativesJeff Law1-170/+140
2024-11-11RISC-V: Fix one nit indent issue of ustrunc pattern [NFC]Pan Li1-1/+1
2024-11-04[PATCH v2 2/2] RISC-V: Disable by pieces for vector setmem length > UNITS_PER...Craig Blackmore1-0/+19
2024-11-04[PATCH v2 1/2] RISC-V: Make vectorized memset handle more casesCraig Blackmore1-18/+19
2024-10-31RISC-V: fix const interleaved stepped vector with a scalar patternVineet Gupta1-3/+3
2024-10-31RISC-V: Do not inline when callee is versioned but caller is notYangyu Chen1-0/+4
2024-10-31RISC-V: Split riscv_process_target_attr with const char *args argumentYangyu Chen2-28/+39
2024-10-31RISC-V: allow -fno-plt to disable PLTYangyu Chen2-3/+3
2024-10-30[RISC-V] Aggressively hoist VXRM assignmentsJeff Law1-0/+69
2024-10-29[PATCH 1/2] RISC-V:Add intrinsic support for the CMOs extensionsyulong1-0/+84
2024-10-29RISC-V: Implement the MASK_LEN_STRIDED_LOAD{STORE}Pan Li3-0/+83
2024-10-28[target/117316] Fix initializer for riscv code alignment handlingJeff Law1-3/+27
2024-10-28RISC-V:Bugfix for vlmul_ext and vlmul_trunc with NULL return value[pr117286]xuli1-0/+4
2024-10-25gcc: Remove trailing whitespaceJakub Jelinek2-2/+2
2024-10-24Use unique_ptr in more places in pretty_printer/diagnostics [PR116613]David Malcolm3-0/+3
2024-10-23[PATCH] RISC-V: override alignment of function/jump/loopWang Pengcheng1-0/+15
2024-10-21RISC-V: Implement vector SAT_TRUNC for signed integerPan Li3-0/+84
2024-10-20Revert "[PATCH 7/7] RISC-V: Disable by pieces for vector setmem length > UNIT...Jeff Law1-19/+0
2024-10-19[PATCH][v5] RISC-V: add option -m(no-)autovec-segmentGreg McGary3-2/+11
2024-10-19[PATCH 7/7] RISC-V: Disable by pieces for vector setmem length > UNITS_PER_WORDCraig Blackmore1-0/+19
2024-10-19[PATCH 5/7] RISC-V: Move vector memcpy decision making to separate function [...Craig Blackmore1-56/+87
2024-10-19[PATCH 4/7] RISC-V: Honour -mrvv-max-lmul in riscv_vector::expand_block_moveCraig Blackmore4-38/+54
2024-10-18[PATCH 3/7] RISC-V: Fix vector memcpy smaller LMUL generationCraig Blackmore1-3/+5
2024-10-18[PATCH 2/7] RISC-V: Fix uninitialized reg in memcpyCraig Blackmore1-2/+1
2024-10-18[PATCH 1/7] RISC-V: Fix indentation in riscv_vector::expand_block_move [NFC]Craig Blackmore1-16/+16
2024-10-16Ternary operator formatting fixesJakub Jelinek2-4/+4
2024-10-16RISC-V: Use biggest_mode as mode for constants.Robin Dapp1-4/+10
2024-10-12[RISC-V] Avoid unnecessary extensions when value is already extendedJivan Hakobyan1-2/+18
2024-10-12RISC-V] Slightly improve broadcasting small constants into vectorsJeff Law2-6/+21
2024-10-12RISC-V: Implement vector SAT_SUB for signed integerPan Li3-0/+21
2024-10-10RISC-V:Bugfix for C++ code compilation failure with rv32imafc_zve32f[pr116883]Li Xu1-1/+6
2024-10-09RISC-V: Optimize branches with shifted immediate operandsJovan Vukic3-0/+48