riscv-gnu-toolchain/gcc.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2024-08-17	RISC-V: Bugfix incorrect operand for vwsll auto-vect	Pan Li	1	-0/+4
2024-06-18	RISC-V: Fix vwsll combine on rv32 targets	Edwin Lu	1	-4/+2
2024-05-31	RISC-V: Add vandn combine helper.	Robin Dapp	1	-0/+18
2024-05-31	RISC-V: Add vwsll combine helpers.	Robin Dapp	1	-2/+124
2024-05-16	RISC-V: Implement vectorizable early exit with vcond_mask_len	Pan Li	1	-0/+33
2024-01-03	Update copyright years.	Jakub Jelinek	1	-1/+1
2023-11-10	RISC-V: Move cond_copysign from combine pattern to autovec pattern	Juzhe-Zhong	1	-22/+0
2023-11-07	RISC-V: Fixed failed rvv combine testcases	Lehua Ding	1	-0/+214
2023-09-24	RISC-V: Support full coverage VLS combine support	Juzhe-Zhong	1	-19/+19
2023-09-23	RISC-V: Add VLS unary combine patterns	Juzhe-Zhong	1	-17/+13
2023-09-22	RISC-V: Support combine cond extend and reduce sum to widen reduce sum	Lehua Ding	1	-0/+72
2023-09-20	RISC-V: Reorganize and rename combine patterns in autovec-opt.md	Lehua Ding	1	-112/+91
2023-09-20	RISC-V: Fixed ICE caused by missing operand	Lehua Ding	1	-5/+10
2023-09-19	RISC-V: Refactor and cleanup fma patterns	Lehua Ding	1	-425/+311
2023-09-15	RISC-V: Refactor expand_reduction and cleanup enum reduction_type	Lehua Ding	1	-8/+14
2023-09-15	RISC-V: Support combine extend and reduce sum to widen reduce sum	Lehua Ding	1	-0/+82
2023-09-14	RISC-V: Support VLS modes mask operations	Juzhe-Zhong	1	-9/+9
2023-09-13	RISC-V: Support cond vmulh.vv and vmulu.vv autovec patterns	Lehua Ding	1	-1/+22
2023-09-13	RISC-V: Support cond vnsrl/vnsra autovec patterns	Lehua Ding	1	-0/+46
2023-09-13	RISC-V: Support cond vfsgnj.vv autovec patterns	Lehua Ding	1	-19/+50
2023-09-12	RISC-V: Finish Typing Un-Typed Instructions and Turn on Assert	Edwin Lu	1	-1/+2
2023-09-11	RISC-V: Update Types for Vector Instructions	Edwin Lu	1	-24/+48
2023-09-06	RISC-V: Keep vlmax vector operators in simple form until split1 pass	Lehua Ding	1	-101/+193
2023-09-06	RISC-V: Add conditional sqrt autovec pattern	Lehua Ding	1	-0/+20
2023-09-01	RISC-V: Add conditional autovec convert(INT<->FP) patterns	Lehua Ding	1	-0/+120
2023-09-01	RISC-V: Add conditional autovec convert(FP<->FP) patterns	Lehua Ding	1	-0/+39
2023-09-01	RISC-V: Add conditional autovec convert(INT<->INT) patterns	Lehua Ding	1	-0/+77
2023-08-31	RISC-V: Support rounding mode for VFNMADD/VFNMACC autovec	Pan Li	1	-16/+22
2023-08-31	RISC-V: Support rounding mode for VFNMSAC/VFNMSUB autovec	Pan Li	1	-14/+20
2023-08-31	RISC-V: Support rounding mode for VFMSAC/VFMSUB autovec	Pan Li	1	-15/+21
2023-08-31	RISC-V: Support rounding mode for VFMADD/VFMACC autovec	Pan Li	1	-13/+19
2023-08-31	RISC-V: Refactor and clean emit_{vlmax,nonvlmax}_xxx functions	Lehua Ding	1	-26/+26
2023-08-23	RISC-V: Add conditional unary neg/abs/not autovec patterns	Lehua Ding	1	-0/+39
2023-07-03	RISC-V: Support vfwnmacc/vfwmsac/vfwnmsac combine lowering	Juzhe-Zhong	1	-0/+182
2023-07-03	RISC-V: Support vfwmul.vv combine lowering	Juzhe-Zhong	1	-0/+39
2023-07-03	Revert "RISC-V: Support vfwnmacc/vfwmsac/vfwnmsac combine lowering"	Lehua Ding	1	-182/+0
2023-07-03	RISC-V: Support vfwnmacc/vfwmsac/vfwnmsac combine lowering	Juzhe-Zhong	1	-0/+182
2023-06-28	RISC-V: Support vfwmacc combine lowering	Juzhe-Zhong	1	-0/+58
2023-06-19	RISC-V: Add sign-extending variants for vmv.x.s.	Robin Dapp	1	-0/+29
2023-06-15	RISC-V: Align the predictor style for define_insn_and_split	Pan Li	1	-10/+10
2023-06-12	RISC-V: Add RVV narrow shift right lowering auto-vectorization	Juzhe-Zhong	1	-0/+46
2023-06-06	RISC-V: Add RVV vwmacc/vwmaccu/vwmaccsu combine lowering optmization	Juzhe-Zhong	1	-0/+160
2023-06-04	RISC-V: Move optimization patterns into autovec-opt.md	Juzhe-Zhong	1	-0/+92
2023-06-03	RISC-V: Add pseudo vwmul.wv pattern to enhance vwmul.vv instruction optimizat...	Juzhe-Zhong	1	-0/+80