RISC-V: Add conditional sqrt autovec pattern

This patch adds a combined pattern for combining vfsqrt.v and vcond_mask.

gcc/ChangeLog:

	* config/riscv/autovec-opt.md (*cond_<optab><mode>):
	Add sqrt + vcond_mask combine pattern.
	* config/riscv/autovec.md (<optab><mode>2):
	Change define_expand to define_insn_and_split.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/autovec/cond/cond_sqrt-1.c: New test.
	* gcc.target/riscv/rvv/autovec/cond/cond_sqrt-2.c: New test.
	* gcc.target/riscv/rvv/autovec/cond/cond_sqrt_run-1.c: New test.
	* gcc.target/riscv/rvv/autovec/cond/cond_sqrt_run-2.c: New test.

1 files changed, 20 insertions, 0 deletions

diff --git a/gcc/config/riscv/autovec-opt.md b/gcc/config/riscv/autovec-opt.md
index 1ca5ce9..d9863c7 100644
--- a/gcc/config/riscv/autovec-opt.md
+++ b/gcc/config/riscv/autovec-opt.md
@@ -730,6 +730,26 @@
   DONE;
 })
 
+;; Combine vfsqrt.v and cond_mask
+(define_insn_and_split "*cond_<optab><mode>"
+  [(set (match_operand:VF 0 "register_operand")
+     (if_then_else:VF
+       (match_operand:<VM> 1 "register_operand")
+       (any_float_unop:VF
+         (match_operand:VF 2 "register_operand"))
+       (match_operand:VF 3 "register_operand")))]
+  "TARGET_VECTOR && can_create_pseudo_p ()"
+  "#"
+  "&& 1"
+  [(const_int 0)]
+{
+  insn_code icode = code_for_pred (<CODE>, <MODE>mode);
+  rtx ops[] = {operands[0], operands[1], operands[2], operands[3],
+               gen_int_mode (GET_MODE_NUNITS (<MODE>mode), Pmode)};
+  riscv_vector::expand_cond_len_unop (icode, ops);
+  DONE;
+})
+
 ;; Combine vlmax neg and UNSPEC_VCOPYSIGN
 (define_insn_and_split "*copysign<mode>_neg"
   [(set (match_operand:VF 0 "register_operand")