RISC-V: Add conditional autovec convert(INT<->INT) patterns

gcc/ChangeLog:

	* config/riscv/autovec-opt.md (*cond_<optab><v_double_trunc><mode>):
	New combine pattern.
	(*cond_<optab><v_quad_trunc><mode>): Ditto.
	(*cond_<optab><v_oct_trunc><mode>): Ditto.
	(*cond_trunc<mode><v_double_trunc>): Ditto.
	* config/riscv/autovec.md (<optab><v_quad_trunc><mode>2): Adjust.
	(<optab><v_oct_trunc><mode>2): Ditto.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/autovec/binop/narrow-3.c: Adjust.
	* gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-1.h: New test.
	* gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-2.h: New test.
	* gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv32-1.c: New test.
	* gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv32-2.c: New test.
	* gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv64-1.c: New test.
	* gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv64-2.c: New test.
	* gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int_run-1.c: New test.
	* gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int_run-2.c: New test.

1 files changed, 77 insertions, 0 deletions

diff --git a/gcc/config/riscv/autovec-opt.md b/gcc/config/riscv/autovec-opt.md
index 9259077..6796239 100644
--- a/gcc/config/riscv/autovec-opt.md
+++ b/gcc/config/riscv/autovec-opt.md
@@ -747,3 +747,80 @@
                                   riscv_vector::BINARY_OP, operands);
   DONE;
 })
+
+;; Combine sign_extend/zero_extend(vf2) and vcond_mask
+(define_insn_and_split "*cond_<optab><v_double_trunc><mode>"
+  [(set (match_operand:VWEXTI 0 "register_operand")
+        (if_then_else:VWEXTI
+          (match_operand:<VM> 1 "register_operand")
+          (any_extend:VWEXTI (match_operand:<V_DOUBLE_TRUNC> 2 "register_operand"))
+          (match_operand:VWEXTI 3 "register_operand")))]
+  "TARGET_VECTOR && can_create_pseudo_p ()"
+  "#"
+  "&& 1"
+  [(const_int 0)]
+{
+  insn_code icode = code_for_pred_vf2 (<CODE>, <MODE>mode);
+  rtx ops[] = {operands[0], operands[1], operands[2], operands[3],
+               gen_int_mode (GET_MODE_NUNITS (<MODE>mode), Pmode)};
+  riscv_vector::expand_cond_len_unop (icode, ops);
+  DONE;
+})
+
+;; Combine sign_extend/zero_extend(vf4) and vcond_mask
+(define_insn_and_split "*cond_<optab><v_quad_trunc><mode>"
+  [(set (match_operand:VQEXTI 0 "register_operand")
+        (if_then_else:VQEXTI
+          (match_operand:<VM> 1 "register_operand")
+          (any_extend:VQEXTI (match_operand:<V_QUAD_TRUNC> 2 "register_operand"))
+          (match_operand:VQEXTI 3 "register_operand")))]
+  "TARGET_VECTOR && can_create_pseudo_p ()"
+  "#"
+  "&& 1"
+  [(const_int 0)]
+{
+  insn_code icode = code_for_pred_vf4 (<CODE>, <MODE>mode);
+  rtx ops[] = {operands[0], operands[1], operands[2], operands[3],
+               gen_int_mode (GET_MODE_NUNITS (<MODE>mode), Pmode)};
+  riscv_vector::expand_cond_len_unop (icode, ops);
+  DONE;
+})
+
+;; Combine sign_extend/zero_extend(vf8) and vcond_mask
+(define_insn_and_split "*cond_<optab><v_oct_trunc><mode>"
+  [(set (match_operand:VOEXTI 0 "register_operand")
+        (if_then_else:VOEXTI
+          (match_operand:<VM> 1 "register_operand")
+          (any_extend:VOEXTI (match_operand:<V_OCT_TRUNC> 2 "register_operand"))
+          (match_operand:VOEXTI 3 "register_operand")))]
+  "TARGET_VECTOR && can_create_pseudo_p ()"
+  "#"
+  "&& 1"
+  [(const_int 0)]
+{
+  insn_code icode = code_for_pred_vf8 (<CODE>, <MODE>mode);
+  rtx ops[] = {operands[0], operands[1], operands[2], operands[3],
+               gen_int_mode (GET_MODE_NUNITS (<MODE>mode), Pmode)};
+  riscv_vector::expand_cond_len_unop (icode, ops);
+  DONE;
+})
+
+;; Combine trunc(vf2) + vcond_mask
+(define_insn_and_split "*cond_trunc<mode><v_double_trunc>"
+  [(set (match_operand:<V_DOUBLE_TRUNC> 0 "register_operand")
+    (if_then_else:<V_DOUBLE_TRUNC>
+          (match_operand:<VM> 1 "register_operand")
+          (truncate:<V_DOUBLE_TRUNC>
+            (match_operand:VWEXTI 2 "register_operand"))
+          (match_operand:<V_DOUBLE_TRUNC> 3 "register_operand")))]
+  "TARGET_VECTOR && can_create_pseudo_p ()"
+  "#"
+  "&& 1"
+  [(const_int 0)]
+{
+  insn_code icode = code_for_pred_trunc (<MODE>mode);
+  rtx ops[] = {operands[0], operands[1], operands[2], operands[3],
+               gen_int_mode (GET_MODE_NUNITS (<MODE>mode), Pmode)};
+  riscv_vector::expand_cond_len_unop (icode, ops);
+  DONE;
+})