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2022-10-19i386: Fix up __bf16 handling on ia32Jakub Jelinek2-10/+9
2022-10-19Canonicalize vec_perm index to make the first index come from the first vector.liuhongt1-0/+17
2022-10-17Remove accidential commitsJeff Law12-31671/+0
2022-10-17Enable REE for H8Jeff Law12-0/+31671
2022-10-14middle-end, c++, i386, libgcc: std::bfloat16_t and __bf16 arithmetic supportJakub Jelinek4-69/+94
2022-10-13machmode: Introduce GET_MODE_NEXT_MODE with previous GET_MODE_WIDER_MODE mean...Jakub Jelinek1-1/+1
2022-10-12Remove AVX512_VP2INTERSECT from PTA_SAPPHIRERAPIDSCui,Lili2-12/+8
2022-10-11i386: Fix up RTL checking ICE [PR107185]Jakub Jelinek1-1/+1
2022-10-11Add define_insn_and_split to support general version of "kxnor".liuhongt1-0/+71
2022-10-10Fix unrecognizable insn of cvtss2si.liuhongt1-2/+2
2022-10-07fix clang warningsMartin Liska1-2/+2
2022-10-03gcc/config/t-i386: add build dependencies on i386-builtin-types.incSergei Trofimovich1-0/+5
2022-09-30i386, rs6000, ia64, s390: Fix C++ ICEs with _Float64x or _Float128 [PR107080]Jakub Jelinek1-4/+4
2022-09-28i386: Mark XMM4-XMM6 as clobbered by encodekey128/encodekey256H.J. Lu2-12/+12
2022-09-27c++: Implement P1467R9 - Extended floating-point types and standard names com...Jakub Jelinek3-9/+22
2022-09-26Support 2-instruction vector shuffle for V4SI/V4SF in ix86_expand_vec_perm_co...liuhongt1-0/+116
2022-09-23i386: Optimize code generation of __mm256_zextsi128_si256(__mm_set1_epi8(-1))Hu, Lin14-5/+86
2022-09-22Fix typo in floorv2sf2, should be register_operand for op1, not vector_operand.liuhongt1-1/+1
2022-09-20Support 64-bit vectorization for single-precision floating rounding operation.liuhongt1-0/+154
2022-09-20Adjust issue_rate for latest Intel processors.liuhongt1-0/+14
2022-09-20i386: Fixed vec_init_dup_v16bf [PR106887]konglin11-7/+36
2022-09-16Modernize ix86_builtin_vectorized_function with corresponding expanders.liuhongt2-181/+84
2022-09-06Fix _mm512_cvt_roundps_ph to generate sae instruction.liuhongt2-3/+29
2022-09-05i386: avoid zero extension for crc32qAlexander Monakov1-4/+5
2022-09-05rename DBX_REGISTER_NUMBER to DEBUGGER_REGNOMartin Liska19-58/+58
2022-09-05x86: Handle V8BF in expand_vec_perm_broadcast_1konglin13-9/+14
2022-09-02d: Fix #error You must define PREFERRED_DEBUGGING_TYPE if DWARF is not supportedIain Buclaw5-11/+28
2022-09-02STABS: remove -gstabs and -gxcoff functionalityMartin Liska2-10/+0
2022-09-02ipa: Fix throw in multi-versioned functions [PR106627]Simon Rainer1-0/+1
2022-09-01i386: Fix conversion of move to/from AX_REG into xchg [PR106707]Uros Bizjak1-2/+2
2022-08-29x86: Handle V16BF in ix86_avx256_split_vector_move_misalignH.J. Lu2-2/+6
2022-08-27contrib: modernize gen_autofdo_event.pyXi Ruoyao1-14/+17
2022-08-26Implement __builtin_issignalingJakub Jelinek1-0/+52
2022-08-26Don't gimple fold ymm-version vblendvpd/vblendvps/vpblendvb w/o TARGET_AVX2liuhongt2-5/+11
2022-08-24i386: Fix up mode iterators that weren't expanded [PR106721]Jakub Jelinek1-7/+8
2022-08-23x86: Cast stride to __PTRDIFF_TYPE__ in AMX intrinsicsH.J. Lu1-3/+3
2022-08-19mkoffload: Cleanup temporary omp_requires_fileTobias Burnus1-0/+1
2022-08-18x86: Support vector __bf16 typekonglin15-119/+258
2022-08-17[Committed] PR target/106640: Fix use of XINT in TImode compute_convert_gain.Roger Sayle1-3/+3
2022-08-16i386: add 'final' and 'override' to scalar_chainMartin Liska1-2/+2
2022-08-15Support shifts and rotates by integer constants in TImode STV on x86_64.Roger Sayle1-6/+144
2022-08-15Improved gain calculation for COMPARE to 0 or -1 in TImode STV on x86_64.Roger Sayle1-0/+17
2022-08-15x86: Enable __bf16 type for TARGET_SSE2 and abovekonglin16-24/+129
2022-08-13Move V1TI shift/rotate lowering from expand to pre-reload split on x86_64.Roger Sayle2-2/+101
2022-08-09Use PTEST to perform AND in TImode STV of (A & B) != 0 on x86_64.Roger Sayle4-27/+118
2022-08-07Allow any immediate constant in *cmp<dwi>_doubleword splitter on x86_64.Roger Sayle1-3/+13
2022-08-03PR target/47949: Use xchg to move from/to AX_REG with -Oz on x86.Roger Sayle1-0/+12
2022-08-03Improved pre-reload split of double word comparison against -1 on x86.Roger Sayle1-0/+9
2022-08-03Support logical shifts by (some) integer constants in TImode STV on x86_64.Roger Sayle1-0/+21
2022-08-01PR target/106481: Handle CONST_WIDE_INT in REG_EQUAL during STV on x86_64.Roger Sayle1-2/+9