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| author | liuhongt <hongtao.liu@intel.com> | 2022-08-30 17:32:47 +0800 |
|---|---|---|
| committer | liuhongt <hongtao.liu@intel.com> | 2022-09-06 13:40:57 +0800 |
| commit | 20288a0c89906ec21b90a3008a5bc98df1e69375 (patch) | |
| tree | d18e5d2a157bbf2e614fa6122b2edf4e5971c7e2 /gcc/config/i386 | |
| parent | 47d2dcd1397bf02b79515c39438e0ea9898f9056 (diff) | |
| download | gcc-20288a0c89906ec21b90a3008a5bc98df1e69375.zip gcc-20288a0c89906ec21b90a3008a5bc98df1e69375.tar.gz gcc-20288a0c89906ec21b90a3008a5bc98df1e69375.tar.bz2 | |
Fix _mm512_cvt_roundps_ph to generate sae instruction.
zmm-version vcvtps2ph is special, it encodes {sae} in evex, but put
round control in the imm. For intrinsic _mm512_cvt_roundps_ph (a,
imm), imm contains both {sae} and round control, we need to separate
it in the assembly output since vcvtps2ph will ignore imm[3:7].
gcc/ChangeLog:
* config/i386/i386-builtin.def (IX86_BUILTIN_CVTPS2PH512):
Map to CODE_FOR_avx512f_vcvtps2ph512_mask_sae.
* config/i386/sse.md (<mask_codefor>avx512f_vcvtps2ph512<mask_name>): Extend to ..
(<mask_codefor>avx512f_vcvtps2ph512<mask_name><round_saeonly_name>): .. this.
(avx512f_vcvtps2ph512_mask_sae): New expander
gcc/testsuite/ChangeLog:
* gcc.target/i386/avx512f-vcvtps2ph-sae.c: New test.
Diffstat (limited to 'gcc/config/i386')
| -rw-r--r-- | gcc/config/i386/i386-builtin.def | 2 | ||||
| -rw-r--r-- | gcc/config/i386/sse.md | 30 |
2 files changed, 29 insertions, 3 deletions
diff --git a/gcc/config/i386/i386-builtin.def b/gcc/config/i386/i386-builtin.def index f9c7abd..dea52a2 100644 --- a/gcc/config/i386/i386-builtin.def +++ b/gcc/config/i386/i386-builtin.def @@ -1351,7 +1351,7 @@ BDESC (OPTION_MASK_ISA_AVX512F, 0, CODE_FOR_avx512f_cmpv8di3_mask, "__builtin_ia BDESC (OPTION_MASK_ISA_AVX512F, 0, CODE_FOR_avx512f_compressv8df_mask, "__builtin_ia32_compressdf512_mask", IX86_BUILTIN_COMPRESSPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_UQI) BDESC (OPTION_MASK_ISA_AVX512F, 0, CODE_FOR_avx512f_compressv16sf_mask, "__builtin_ia32_compresssf512_mask", IX86_BUILTIN_COMPRESSPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_UHI) BDESC (OPTION_MASK_ISA_AVX512F, 0, CODE_FOR_floatv8siv8df2_mask, "__builtin_ia32_cvtdq2pd512_mask", IX86_BUILTIN_CVTDQ2PD512, UNKNOWN, (int) V8DF_FTYPE_V8SI_V8DF_UQI) -BDESC (OPTION_MASK_ISA_AVX512F, 0, CODE_FOR_avx512f_vcvtps2ph512_mask, "__builtin_ia32_vcvtps2ph512_mask", IX86_BUILTIN_CVTPS2PH512, UNKNOWN, (int) V16HI_FTYPE_V16SF_INT_V16HI_UHI) +BDESC (OPTION_MASK_ISA_AVX512F, 0, CODE_FOR_avx512f_vcvtps2ph512_mask_sae, "__builtin_ia32_vcvtps2ph512_mask", IX86_BUILTIN_CVTPS2PH512, UNKNOWN, (int) V16HI_FTYPE_V16SF_INT_V16HI_UHI) BDESC (OPTION_MASK_ISA_AVX512F, 0, CODE_FOR_ufloatv8siv8df2_mask, "__builtin_ia32_cvtudq2pd512_mask", IX86_BUILTIN_CVTUDQ2PD512, UNKNOWN, (int) V8DF_FTYPE_V8SI_V8DF_UQI) BDESC (OPTION_MASK_ISA_AVX512F, 0, CODE_FOR_cvtusi2sd32, "__builtin_ia32_cvtusi2sd32", IX86_BUILTIN_CVTUSI2SD32, UNKNOWN, (int) V2DF_FTYPE_V2DF_UINT) BDESC (OPTION_MASK_ISA_AVX512F, 0, CODE_FOR_expandv8df_mask, "__builtin_ia32_expanddf512_mask", IX86_BUILTIN_EXPANDPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_UQI) diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index 72acf0b..d535c0a 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -26903,14 +26903,40 @@ (set_attr "btver2_decode" "vector") (set_attr "mode" "V8SF")]) -(define_insn "<mask_codefor>avx512f_vcvtps2ph512<mask_name>" +;; vcvtps2ph is special, it encodes {sae} in evex, but round control in the imm +;; For intrinsic _mm512_cvt_roundps_ph (a, imm), imm contains both {sae} +;; and round control, we need to separate it in the assembly output. +;; op2 in avx512f_vcvtps2ph512_mask_sae contains both sae and round control. +(define_expand "avx512f_vcvtps2ph512_mask_sae" + [(set (match_operand:V16HI 0 "register_operand" "=v") + (vec_merge:V16HI + (unspec:V16HI + [(match_operand:V16SF 1 "register_operand" "v") + (match_operand:SI 2 "const_0_to_255_operand")] + UNSPEC_VCVTPS2PH) + (match_operand:V16HI 3 "nonimm_or_0_operand") + (match_operand:HI 4 "register_operand")))] + "TARGET_AVX512F" +{ + int round = INTVAL (operands[2]); + /* Separate {sae} from rounding control imm, + imm[3:7] will be ignored by the instruction. */ + if (round & 8) + { + emit_insn (gen_avx512f_vcvtps2ph512_mask_round (operands[0], operands[1], + operands[2], operands[3], operands[4], GEN_INT (8))); + DONE; + } +}) + +(define_insn "<mask_codefor>avx512f_vcvtps2ph512<mask_name><round_saeonly_name>" [(set (match_operand:V16HI 0 "register_operand" "=v") (unspec:V16HI [(match_operand:V16SF 1 "register_operand" "v") (match_operand:SI 2 "const_0_to_255_operand")] UNSPEC_VCVTPS2PH))] "TARGET_AVX512F" - "vcvtps2ph\t{%2, %1, %0<mask_operand3>|%0<mask_operand3>, %1, %2}" + "vcvtps2ph\t{%2, <round_saeonly_mask_op3>%1, %0<mask_operand3>|%0<mask_operand3>, %1<round_saeonly_mask_op3>, %2}" [(set_attr "type" "ssecvt") (set_attr "prefix" "evex") (set_attr "mode" "V16SF")]) |