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| author | Alexander Monakov <amonakov@ispras.ru> | 2022-08-23 18:42:24 +0300 |
|---|---|---|
| committer | Alexander Monakov <amonakov@ispras.ru> | 2022-09-05 21:01:35 +0300 |
| commit | 810d9815249451f477d4cbc67b8e4a0819c37faa (patch) | |
| tree | bab7793a187d199024f39a50d47ad4ca07e23b5a /gcc/config/i386 | |
| parent | 8492f7dd51aff17fd755c9f9dd4dc5874ddd6dec (diff) | |
| download | gcc-810d9815249451f477d4cbc67b8e4a0819c37faa.zip gcc-810d9815249451f477d4cbc67b8e4a0819c37faa.tar.gz gcc-810d9815249451f477d4cbc67b8e4a0819c37faa.tar.bz2 | |
i386: avoid zero extension for crc32q
The crc32q instruction takes 64-bit operands, but ignores high 32 bits
of the destination operand, and zero-extends the result from 32 bits.
Let's model this in the RTL pattern to avoid zero-extension when the
_mm_crc32_u64 intrinsic is used with a 32-bit type.
PR target/106453
gcc/ChangeLog:
* config/i386/i386.md (sse4_2_crc32di): Model that only low 32
bits of operand 0 are consumed, and the result is zero-extended
to 64 bits.
gcc/testsuite/ChangeLog:
* gcc.target/i386/pr106453.c: New test.
Diffstat (limited to 'gcc/config/i386')
| -rw-r--r-- | gcc/config/i386/i386.md | 9 |
1 files changed, 5 insertions, 4 deletions
diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md index 1aef1af..1be9b66 100644 --- a/gcc/config/i386/i386.md +++ b/gcc/config/i386/i386.md @@ -23823,10 +23823,11 @@ (define_insn "sse4_2_crc32di" [(set (match_operand:DI 0 "register_operand" "=r") - (unspec:DI - [(match_operand:DI 1 "register_operand" "0") - (match_operand:DI 2 "nonimmediate_operand" "rm")] - UNSPEC_CRC32))] + (zero_extend:DI + (unspec:SI + [(match_operand:SI 1 "register_operand" "0") + (match_operand:DI 2 "nonimmediate_operand" "rm")] + UNSPEC_CRC32)))] "TARGET_64BIT && TARGET_CRC32" "crc32{q}\t{%2, %0|%0, %2}" [(set_attr "type" "sselog1") |