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2015-11-22re PR target/68390 (Incorrect code due to indirect tail call of varargs funct...Kugan Vivekanandarajah1-1/+6
2015-11-20[AArch64] Add attribute for compatibility with ARM pipeline modelsEvandro Menezes1-0/+3
2015-11-20[ARM] Do not expand movmisalign pattern if not in 32-bit modeKyrylo Tkachov2-7/+8
2015-11-20[ARM] PR 68149 Fix ICE in unaligned_loaddi splitKyrylo Tkachov2-57/+24
2015-11-18Finalize func_options in arm target inMartin Liska1-0/+2
2015-11-17Make builtin_vectorized_function take a combined_fnRichard Sandiford2-56/+53
2015-11-17[ARM] PR 68143 Properly update memory offsets when expanding setmemKyrylo Tkachov1-13/+24
2015-11-16[Patch ARM] Add support for Cortex-A35James Greenhalgh6-3/+33
2015-11-16Add missing v8a cpus to the t-aprofile file.Jim Wilson1-0/+3
2015-11-16arm_neon.h: Remove #ifndef check on __ARM_NEON.Christian Bruel1-257/+219
2015-11-16re PR target/65837 ([arm-linux-gnueabihf] lto1 target specific builtin not av...Christian Bruel1-2/+6
2015-11-16re PR target/65837 ([arm-linux-gnueabihf] lto1 target specific builtin not av...Christian Bruel2-32/+70
2015-11-16coding nitChristian Bruel1-1/+1
2015-11-16re PR target/65837 ([arm-linux-gnueabihf] lto1 target specific builtin not av...Christian Bruel3-73/+95
2015-11-16re PR target/65837 ([arm-linux-gnueabihf] lto1 target specific builtin not av...Christian Bruel2-36/+31
2015-11-13re PR target/65837 ([arm-linux-gnueabihf] lto1 target specific builtin not av...Christian Bruel2-20/+18
2015-11-13Revert [ARM] Remove neon-testgen.ml and generated tests.Christophe Lyon1-0/+324
2015-11-12[ARM] Remove neon-testgen.ml and generated tests.Christophe Lyon1-324/+0
2015-11-12Add initial qualcomm support.Jim Wilson4-2/+8
2015-11-12[PATCH][ARM]Fix addsi3_compare_op2 pattern.Renlin Li1-2/+2
2015-11-12[ARM] remove unused variableCharles Baylis1-6/+0
2015-11-11[ARM] PR67305, tighten neon_vector_mem_operand on eliminable registersJiong Wang1-3/+3
2015-11-11[ARM] PR63870 Remove error for invalid lane numbersCharles Baylis1-40/+8
2015-11-11[ARM] PR63870 Mark lane indices of vldN/vstN with appropriate qualifierCharles Baylis2-25/+61
2015-11-11[ARM] PR63870 Add qualifiers for NEON builtinsCharles Baylis3-18/+37
2015-11-10[ARM] Fix costing of vmul+vcvt combine patternKyrylo Tkachov1-0/+17
2015-11-10[ARM][cleanup] Remove uses of CONST_DOUBLE_HIGH/LOWKyrylo Tkachov1-24/+7
2015-11-09Machine modes for address printing.Julian Brown1-13/+5
2015-11-06revert: arm.md (*arm_smin_cmp): New pattern.Michael Collison1-38/+0
2015-11-06[Patch ARM] Unified assembler in ARM state.Ramana Radhakrishnan8-274/+231
2015-11-06[ARM/AArch64] PR 68088: Fix RTL checking ICE due to subregs inside accumulato...Kyrylo Tkachov1-0/+6
2015-11-03remove unused config/arm/coff.hTrevor Saunders1-82/+0
2015-11-02[ARM] neon-testgen.ml typoJulian Brown1-7/+7
2015-10-30Fix comment typo.Jim Wilson1-1/+1
2015-10-30[ARM] Fix checking RTL error in cortex_a9_sched_adjust_costKyrylo Tkachov1-3/+1
2015-10-29[PATCH 8/9] ENABLE_CHECKING refactoring: target-specific partsMikhail Maltsev1-14/+15
2015-10-27[ARM] PR target/67929 Tighten vfp3_const_double_for_bits checksKyrylo Tkachov3-15/+28
2015-10-21Improve --help output to generate references to option aliases.Martin Sebor1-30/+30
2015-10-16gen-mul-tables.cc: Adjust include files.Andrew MacLeod4-53/+21
2015-10-16re PR target/67745 ([ARM] wrong alignments when __attribute__ ((optimize,targ...Christian Bruel2-1/+23
2015-10-16re PR target/67745 ([ARM] wrong alignments when __attribute__ ((optimize,targ...Christian Bruel2-1/+23
2015-10-09[PATCH][ARM]Add earlyclobber modifier for neon_(vtrn, vuzp, vzip)<mode>_insn rtxRenlin Li1-6/+6
2015-10-09[Patch PR target/67366 1/2] [ARM] - Add movmisalignhi / si patternsRamana Radhakrishnan2-0/+38
2015-10-07Fix PR c/65345 for armRamana Radhakrishnan1-2/+2
2015-10-06arm.c (arm_emit_probe_stack_range): Adjust comment.Eric Botcazou2-15/+14
2015-10-05Remove REAL_VALUE_FROM_CONST_DOUBLERichard Sandiford3-57/+34
2015-10-05Replace REAL_VALUES_EQUAL with real_equalRichard Sandiford1-3/+3
2015-10-01[Patch 2/2 ARM/AArch64] Add a new Cortex-A53 scheduling modelJames Greenhalgh3-201/+664
2015-09-29add separate insn sched class for vector LDP & STPEvandro Menezes3-5/+17
2015-09-28[Patch 1/2 AArch64/ARM] Give AArch64 ROR (Immediate) a new type attributeJames Greenhalgh3-2/+4
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