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| author | Kyrylo Tkachov <kyrylo.tkachov@arm.com> | 2015-11-20 15:19:09 +0000 |
|---|---|---|
| committer | Kyrylo Tkachov <ktkachov@gcc.gnu.org> | 2015-11-20 15:19:09 +0000 |
| commit | 8e92560a9c9c57dfed3283c48ef5e46a7e0204b1 (patch) | |
| tree | 7537684c2270e6e521ed169b8b6a13da9a61f96a /gcc/config/arm | |
| parent | 88fdc9a66e4b14aef5aa4b873223e4d081a8824c (diff) | |
| download | gcc-8e92560a9c9c57dfed3283c48ef5e46a7e0204b1.zip gcc-8e92560a9c9c57dfed3283c48ef5e46a7e0204b1.tar.gz gcc-8e92560a9c9c57dfed3283c48ef5e46a7e0204b1.tar.bz2 | |
[ARM] Do not expand movmisalign pattern if not in 32-bit mode
* config/arm/arm.c (arm_option_override): Require TARGET_32BIT
for unaligned_access.
* config/arm/arm.md (unaligned_loadsi): Remove redundant TARGET_32BIT
from matching condition.
(unaligned_loadhis): Likewise.
(unaligned_loadhiu): Likewise.
(unaligned_storesi): Likewise.
(unaligned_storehi): Likewise.
* gcc.target/arm/armv6-unaligned-load-ice.c: New test.
From-SVN: r230664
Diffstat (limited to 'gcc/config/arm')
| -rw-r--r-- | gcc/config/arm/arm.c | 5 | ||||
| -rw-r--r-- | gcc/config/arm/arm.md | 10 |
2 files changed, 8 insertions, 7 deletions
diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c index 805335c..290b537 100644 --- a/gcc/config/arm/arm.c +++ b/gcc/config/arm/arm.c @@ -3282,7 +3282,8 @@ arm_option_override (void) } /* Enable -munaligned-access by default for - - all ARMv6 architecture-based processors + - all ARMv6 architecture-based processors when compiling for a 32-bit ISA + i.e. Thumb2 and ARM state only. - ARMv7-A, ARMv7-R, and ARMv7-M architecture-based processors. - ARMv8 architecture-base processors. @@ -3292,7 +3293,7 @@ arm_option_override (void) if (unaligned_access == 2) { - if (arm_arch6 && (arm_arch_notm || arm_arch7)) + if (TARGET_32BIT && arm_arch6 && (arm_arch_notm || arm_arch7)) unaligned_access = 1; else unaligned_access = 0; diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md index 227a9bd..effe7eb 100644 --- a/gcc/config/arm/arm.md +++ b/gcc/config/arm/arm.md @@ -4219,7 +4219,7 @@ [(set (match_operand:SI 0 "s_register_operand" "=l,r") (unspec:SI [(match_operand:SI 1 "memory_operand" "Uw,m")] UNSPEC_UNALIGNED_LOAD))] - "unaligned_access && TARGET_32BIT" + "unaligned_access" "ldr%?\t%0, %1\t@ unaligned" [(set_attr "arch" "t2,any") (set_attr "length" "2,4") @@ -4232,7 +4232,7 @@ (sign_extend:SI (unspec:HI [(match_operand:HI 1 "memory_operand" "Uw,Uh")] UNSPEC_UNALIGNED_LOAD)))] - "unaligned_access && TARGET_32BIT" + "unaligned_access" "ldrsh%?\t%0, %1\t@ unaligned" [(set_attr "arch" "t2,any") (set_attr "length" "2,4") @@ -4245,7 +4245,7 @@ (zero_extend:SI (unspec:HI [(match_operand:HI 1 "memory_operand" "Uw,m")] UNSPEC_UNALIGNED_LOAD)))] - "unaligned_access && TARGET_32BIT" + "unaligned_access" "ldrh%?\t%0, %1\t@ unaligned" [(set_attr "arch" "t2,any") (set_attr "length" "2,4") @@ -4257,7 +4257,7 @@ [(set (match_operand:SI 0 "memory_operand" "=Uw,m") (unspec:SI [(match_operand:SI 1 "s_register_operand" "l,r")] UNSPEC_UNALIGNED_STORE))] - "unaligned_access && TARGET_32BIT" + "unaligned_access" "str%?\t%1, %0\t@ unaligned" [(set_attr "arch" "t2,any") (set_attr "length" "2,4") @@ -4269,7 +4269,7 @@ [(set (match_operand:HI 0 "memory_operand" "=Uw,m") (unspec:HI [(match_operand:HI 1 "s_register_operand" "l,r")] UNSPEC_UNALIGNED_STORE))] - "unaligned_access && TARGET_32BIT" + "unaligned_access" "strh%?\t%1, %0\t@ unaligned" [(set_attr "arch" "t2,any") (set_attr "length" "2,4") |