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2024-11-29__builtin_prefetch fixes [PR117608]Jakub Jelinek1-7/+7
2024-01-03Update copyright years.Jakub Jelinek1-1/+1
2023-12-13ARC: Add *extvsi_n_0 define_insn_and_split for PR 110717.Roger Sayle1-0/+20
2023-11-28ARC: Consistent use of whitespace in assembler templates.Roger Sayle1-177/+176
2023-11-13ARC: Improved DImode rotates and right shifts by one bit.Roger Sayle1-0/+219
2023-11-13ARC: Provide a TARGET_FOLD_BUILTIN target hook.Roger Sayle1-15/+2
2023-11-03ARC: Improve DImode left shift by a single bit.Roger Sayle1-9/+46
2023-10-30ARC: Convert (signed<<31)>>31 to -(signed&1) without barrel shifter.Roger Sayle1-0/+14
2023-10-30ARC: Improved SImode shifts and rotates with -mswap.Roger Sayle1-11/+32
2023-10-24ARC: Improved SImode shifts and rotates on !TARGET_BARREL_SHIFTER.Roger Sayle1-169/+61
2023-10-24arc: Remove mpy_dest_reg_operand predicateClaudiu Zissulescu1-3/+3
2023-10-16ARC: Split asl dst,1,src into bset dst,0,src to implement 1<<x.Roger Sayle1-0/+16
2023-10-10arc: Refurbish add.f combiner patternsClaudiu Zissulescu1-13/+12
2023-10-05arc: Remove obsolete ccfsm instruction predication mechanismClaudiu Zissulescu1-93/+25
2023-10-05arc: Remove '^' print punct characterClaudiu Zissulescu1-9/+9
2023-10-05arc: Remove unused/incomplete alignment assembly annotation.Claudiu Zissulescu1-63/+62
2023-10-04ARC: Split SImode shifts pre-reload on !TARGET_BARREL_SHIFTER.Roger Sayle1-56/+182
2023-10-04ARC: Correct instruction length attributes.Roger Sayle1-7/+7
2023-10-03ARC: Use rlc r0,0 to implement scc_ltu (i.e. carry_flag ? 1 : 0)Roger Sayle1-1/+13
2023-09-05arc: Cleanup addsi3 instruction patternClaudiu Zissulescu1-42/+39
2023-09-05arc: Remove obsolete mbbit-peephole option and unused patterns.Claudiu Zissulescu1-31/+0
2023-08-31arc: Honor SWAP option for lsl16 instructionClaudiu Zissulescu1-1/+1
2023-06-18Fix arc assumption that insns are not re-recognizedJeff Law1-1/+7
2023-01-02Update copyright years.Jakub Jelinek1-1/+1
2022-10-10arc: Remove Rcq constraint.Claudiu Zissulescu1-79/+73
2022-10-10arc: Remove Rcw constraintClaudiu Zissulescu1-110/+110
2022-10-10arc: Remove Rcr constraintClaudiu Zissulescu1-18/+18
2022-07-18arc: Add ARCHS release 310a tune variant.Claudiu Zissulescu1-12/+20
2022-02-25arc: Fail conditional move expand patternsClaudiu Zissulescu1-5/+20
2022-01-18Fix -Wformat-diag in various targets.Martin Liska1-1/+1
2022-01-17Change references of .c files to .cc filesMartin Liska1-4/+4
2022-01-03Update copyright years.Jakub Jelinek1-1/+1
2021-11-16arc: Update (u)maddhisi4 patternsClaudiu Zissulescu1-17/+17
2021-09-14arc: Update ZOL pattern.Claudiu Zissulescu1-4/+4
2021-06-09arc: Update doloop_end patternsClaudiu Zissulescu1-26/+20
2021-06-09arc: Fix (u)maddhisi patternsClaudiu Zissulescu1-25/+41
2021-06-09arc: Update 64bit move split patterns.Claudiu Zissulescu1-73/+18
2021-06-03arc: Remove obsolete optionsClaudiu Zissulescu1-8/+0
2021-06-02arc: Remove define_insn_and_split *bbit_diKewen Lin1-28/+0
2021-05-10arc: Improve vector support for ARCv2.Claudiu Zissulescu1-0/+1
2021-05-10arc: Update ctz/clz patternsClaudiu Zissulescu1-23/+30
2021-01-05arc: fix accumulator first register.Claudiu Zissulescu1-4/+4
2021-01-04Update copyright years.Jakub Jelinek1-1/+1
2020-12-29arc: generate mac(u) insn instead of macd(u) when destination is acclClaudiu Zissulescu1-10/+14
2020-12-29arc: Don't use predicated vadd2 instructions in mov patterns.Claudiu Zissulescu1-3/+3
2020-12-11arc: Refurbish adc/sbc patternsClaudiu Zissulescu1-66/+29
2020-12-11arc: Use separate predicated patterns for mpyd(u)Claudiu Zissulescu1-50/+51
2020-11-09arc: Improve/add instruction patterns to better use MAC instructions.Claudiu Zissulescu1-6/+65
2020-03-03arc: Improve code gen for 64bit add/sub operations.Claudiu Zissulescu1-75/+41
2020-03-03arc: Add length attribute to eh_return pattern.Claudiu Zissulescu1-1/+3
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