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author | Jakub Jelinek <jakub@redhat.com> | 2024-11-29 10:17:07 +0100 |
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committer | Jakub Jelinek <jakub@gcc.gnu.org> | 2024-11-29 10:18:32 +0100 |
commit | f7bbdf7e4acf9c90f51d24db9a3c911c49169ab6 (patch) | |
tree | e3fcf8d20d639da2f16b93d0305752860d7c09a4 /gcc/config/arc/arc.md | |
parent | 48b72743b0e29871171593fe34856da62d954750 (diff) | |
download | gcc-f7bbdf7e4acf9c90f51d24db9a3c911c49169ab6.zip gcc-f7bbdf7e4acf9c90f51d24db9a3c911c49169ab6.tar.gz gcc-f7bbdf7e4acf9c90f51d24db9a3c911c49169ab6.tar.bz2 |
__builtin_prefetch fixes [PR117608]
The r15-4833-ge9ab41b79933 patch had among tons of config/i386
specific changes also important change to the generic code, allowing
also 2 as valid value of the second argument of __builtin_prefetch:
- /* Argument 1 must be either zero or one. */
- if (INTVAL (op1) != 0 && INTVAL (op1) != 1)
+ /* Argument 1 must be 0, 1 or 2. */
+ if (INTVAL (op1) < 0 || INTVAL (op1) > 2)
But the patch failed to document that change in __builtin_prefetch
documentation, and more importantly didn't adjust any of the other
backends to deal with it (my understanding is the expected behavior
is that 2 will be silently handled as 0 unless backends have some
more specific way). Some of the backends would ICE on it, in some
cases gcc_assert failures/gcc_unreachable, in other cases crash later
(e.g. accessing arrays with that value as index and due to accessing
garbage after the array crashing at final.cc time), others treated 2
silently as 0, others treated 2 silently as 1.
And even in the i386 backend there were bugs which caused ICEs.
The patch added some if (write == 0) and write 2 handling into
a (badly indented, maybe that is the reason, if (write == 1) body),
rather than into the else side, so it would be always false.
The new *prefetch_rst2 define_insn only accepts parameters 2 1
(i.e. read-shared with moderate degree of locality), so in order
not to ICE the patch uses it only for __builtin_prefetch (ptr, 2, 1);
or __builtin_ia32_prefetch (ptr, 2, 1, 0); and not for other values
of the parameter. If that isn't what we want and we want it to be used
also for all or some of __builtin_prefetch (ptr, 2, {0,2,3}); and
corresponding __builtin_ia32_prefetch, maybe the define_insn could match
other values.
And there was another problem that -mno-mmx -mno-sse -mmovrs compilation
would ICE on most of the prefetches, so I had to add the FAIL; cases.
2024-11-29 Jakub Jelinek <jakub@redhat.com>
PR target/117608
* doc/extend.texi (__builtin_prefetch): Document that second
argument may be also 2 and its meaning.
* config/i386/i386.md (prefetch): Remove unreachable code.
Clear write set operands[1] to const0_rtx if !TARGET_MOVRS or
of locality is not 1. Formatting fixes.
* config/i386/i386-expand.cc (ix86_expand_builtin): Use IN_RANGE.
Call gen_prefetch even for TARGET_MOVRS.
* config/alpha/alpha.md (prefetch): Treat read_or_write 2 like 0.
* config/mips/mips.md (prefetch): Likewise.
* config/arc/arc.md (prefetch_1, prefetch_2, prefetch_3): Likewise.
* config/riscv/riscv.md (prefetch): Likewise.
* config/loongarch/loongarch.md (prefetch): Likewise.
* config/sparc/sparc.md (prefetch): Likewise. Use IN_RANGE.
* config/ia64/ia64.md (prefetch): Likewise.
* config/pa/pa.md (prefetch): Likewise.
* config/aarch64/aarch64.md (prefetch): Likewise.
* config/rs6000/rs6000.md (prefetch): Likewise.
* gcc.dg/builtin-prefetch-1.c (good): Add tests with second argument
2.
* gcc.target/i386/pr117608-1.c: New test.
* gcc.target/i386/pr117608-2.c: New test.
Diffstat (limited to 'gcc/config/arc/arc.md')
-rw-r--r-- | gcc/config/arc/arc.md | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/gcc/config/arc/arc.md b/gcc/config/arc/arc.md index 9004b60..1fb7cf5 100644 --- a/gcc/config/arc/arc.md +++ b/gcc/config/arc/arc.md @@ -5439,9 +5439,9 @@ archs4x, archs4xd" (match_operand:SI 2 "const_int_operand" "n"))] "TARGET_HS" { - if (INTVAL (operands[1])) + if ((INTVAL (operands[1]) & 1) != 0) return "prefetchw [%0]"; - else + else return "prefetch [%0]"; } [(set_attr "type" "load") @@ -5454,9 +5454,9 @@ archs4x, archs4xd" (match_operand:SI 3 "const_int_operand" "n,n,n"))] "TARGET_HS" { - if (INTVAL (operands[2])) + if ((INTVAL (operands[2]) & 1) != 0) return "prefetchw\\t[%0, %1]"; - else + else return "prefetch\\t[%0, %1]"; } [(set_attr "type" "load") @@ -5468,10 +5468,10 @@ archs4x, archs4xd" (match_operand:SI 2 "const_int_operand" "n"))] "TARGET_HS" { - operands[0] = gen_rtx_MEM (SImode, operands[0]); - if (INTVAL (operands[1])) + operands[0] = gen_rtx_MEM (SImode, operands[0]); + if ((INTVAL (operands[1]) & 1) != 0) return "prefetchw%U0\\t%0"; - else + else return "prefetch%U0\\t%0"; } [(set_attr "type" "load") |