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authorClaudiu Zissulescu <claziss@gmail.com>2023-10-17 12:23:19 +0300
committerClaudiu Zissulescu <claziss@gmail.com>2023-10-24 15:47:31 +0300
commit2287fa29fd28ae39963de80d5f845be2c6ab8675 (patch)
tree87813950b2d4744f695e68410fdf86a27ab85a5e /gcc/config/arc/arc.md
parent0fc13e8c0e39c51e82deb93f324d9d86ad8d7460 (diff)
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arc: Remove mpy_dest_reg_operand predicate
The mpy_dest_reg_operand is just a wrapper for register_operand. Remove it. gcc/ * config/arc/arc.md (mulsi3_700): Update pattern. (mulsi3_v2): Likewise. * config/arc/predicates.md (mpy_dest_reg_operand): Remove it. Signed-off-by: Claudiu Zissulescu <claziss@gmail.com>
Diffstat (limited to 'gcc/config/arc/arc.md')
-rw-r--r--gcc/config/arc/arc.md6
1 files changed, 3 insertions, 3 deletions
diff --git a/gcc/config/arc/arc.md b/gcc/config/arc/arc.md
index 22af0bf..325e4f5 100644
--- a/gcc/config/arc/arc.md
+++ b/gcc/config/arc/arc.md
@@ -2293,7 +2293,7 @@ archs4x, archs4xd"
; registers, since it cannot be the destination of a multi-cycle insn
; like MPY or MPYU.
(define_insn "mulsi3_700"
- [(set (match_operand:SI 0 "mpy_dest_reg_operand" "=r, r,r, r,r")
+ [(set (match_operand:SI 0 "register_operand" "=r, r,r, r,r")
(mult:SI (match_operand:SI 1 "register_operand" "%0, r,0, 0,r")
(match_operand:SI 2 "nonmemory_operand" "rL,rL,I,Cal,Cal")))]
"TARGET_ARC700_MPY"
@@ -2306,8 +2306,8 @@ archs4x, archs4xd"
; ARCv2 has no penalties between mpy and mpyu. So, we use mpy because of its
; short variant. LP_COUNT constraints are still valid.
(define_insn "mulsi3_v2"
- [(set (match_operand:SI 0 "mpy_dest_reg_operand" "=q,q, r, r,r, r, r")
- (mult:SI (match_operand:SI 1 "register_operand" "%0,q, 0, r,0, 0, c")
+ [(set (match_operand:SI 0 "register_operand" "=q,q, r, r,r, r, r")
+ (mult:SI (match_operand:SI 1 "register_operand" "%0,q, 0, r,0, 0, r")
(match_operand:SI 2 "nonmemory_operand" "q,0,rL,rL,I,Cal,Cal")))]
"TARGET_MULTI"
"@