| Age | Commit message (Expand) | Author | Files | Lines |
|---|
| 2016-01-28 | re PR target/69305 (wrong code with -O and int128 @ aarch64) | Richard Henderson | 1 | -0/+3 |
| 2016-01-11 | [AArch64] PR rtl-optimization/68796: Add patterns for QImode and HImode compa... | Kyrylo Tkachov | 1 | -0/+2 |
| 2016-01-04 | Update copyright years. | Jakub Jelinek | 1 | -1/+1 |
| 2015-12-02 | aarch64.md: New pattern. | David Sherwood | 1 | -0/+10 |
| 2015-11-26 | [AArch64] Add sqrdmah, sqrdmsh instructions. | Matthew Wahab | 1 | -0/+6 |
| 2015-11-25 | 2015-11-24 Michael Collison <michael.collison@linaro.org> | Michael Collison | 1 | -0/+12 |
| 2015-11-24 | [AArch64][v2] Improve comparison with complex immediates followed by branch/cset | Kyrylo Tkachov | 1 | -1/+2 |
| 2015-11-10 | [AArch64] Move iterators from atomics.md to iterators.md | Matthew Wahab | 1 | -0/+33 |
| 2015-11-10 | [AArch64][2/3] Implement negcc, notcc optabs | Kyrylo Tkachov | 1 | -0/+6 |
| 2015-11-03 | [AARCH64][PATCH 1/3] Implementing the variants of the vmulx_ NEON intrinsic | Bilyan Borisov | 1 | -0/+1 |
| 2015-10-12 | [AArch64_be] Fix vtbl[34] and vtbx4 | Christophe Lyon | 1 | -0/+1 |
| 2015-10-06 | iterators.md (vwcore): Add missing cases for V4HF/V8HF modes. | Kugan Vivekanandarajah | 1 | -0/+1 |
| 2015-09-15 | [AArch64 array_mode 7/8] Combine the expanders using VSTRUCT:nregs | Alan Lawrence | 1 | -0/+3 |
| 2015-09-15 | [AArch64 array_mode 6/8] Remove V_TWO_ELEM, again using BLKmode + set_mem_size. | Alan Lawrence | 1 | -10/+0 |
| 2015-09-15 | [AArch64 array_mode 5/8] Remove V_FOUR_ELEM, again using BLKmode + set_mem_size. | Alan Lawrence | 1 | -10/+0 |
| 2015-09-15 | [AArch64 array_mode 3/8] Stop using EImode in aarch64-simd.md and iterators.md | Alan Lawrence | 1 | -9/+0 |
| 2015-09-15 | [AArch64 array_mode 2/8] Remove VSTRUCT_DREG, use BLKmode for d-reg aarch64_s... | Alan Lawrence | 1 | -2/+0 |
| 2015-09-14 | [AArch64] Handle literal pools for functions > 1 MiB in size. | Ramana Radhakrishnan | 1 | -0/+3 |
| 2015-09-11 | Remove separate movtf pattern - Use an iterator for all FP modes. | Ramana Radhakrishnan | 1 | -2/+2 |
| 2015-09-08 | [AArch64] Add vcvt(_high)?_f32_f16 intrinsics, with BE RTL fix | Alan Lawrence | 1 | -5/+13 |
| 2015-09-08 | [AArch64] Improve code generation for float16 vector code | Alan Lawrence | 1 | -1/+6 |
| 2015-09-08 | [AArch64] Implement vcvt_{,high_}f16_f32 | Alan Lawrence | 1 | -1/+9 |
| 2015-09-08 | [AArch64] vld{2,3,4}{,_lane,_dup}, vcombine, vcreate | Alan Lawrence | 1 | -6/+12 |
| 2015-09-08 | [AArch64] Add support for float16x{4,8}_t vectors/builtins | Alan Lawrence | 1 | -8/+28 |
| 2015-08-27 | aarch64.md (*condjump): Handle functions > 1 MiB. | Thomas Preud'homme | 1 | -0/+6 |
| 2015-08-14 | re PR target/67143 (ICE (could not split insn) on aarch64-linux-gnu) | Matthew Wahab | 1 | -3/+10 |
| 2015-07-30 | [AArch64] Removed unused VRL2/3/4 iterator values | Alan Lawrence | 1 | -12/+3 |
| 2015-07-29 | [AArch64] Add basic FP16 support | Alan Lawrence | 1 | -0/+3 |
| 2015-06-26 | [AArch64][2/2] Implement -fpic for -mcmodel=small | Jiong Wang | 1 | -0/+4 |
| 2015-04-30 | [PATCH][AARCH64]Define vec_shr as an unspec, use shl for big-endian. | Renlin Li | 1 | -0/+1 |
| 2015-01-28 | [Patch AArch64] Make integer vabs intrinsics UNSPECs | James Greenhalgh | 1 | -0/+1 |
| 2015-01-27 | [AArch64] Improve bit-test-branch pattern to avoid unnecessary register clobber | Jiong Wang | 1 | -0/+3 |
| 2015-01-21 | gcc/ | David Sherwood | 1 | -0/+3 |
| 2015-01-05 | Update copyright years. | Jakub Jelinek | 1 | -1/+1 |
| 2014-12-19 | [AArch64 3/3] Fix XOR_one_cmpl pattern; add SIMD-reg variants for BIC,ORN,EON | Alan Lawrence | 1 | -0/+3 |
| 2014-12-19 | [AArch64 2/3] Add SIMD-reg variants of logical operators and/ior/xor/not | Alan Lawrence | 1 | -1/+2 |
| 2014-12-08 | arm_neon.h (vrecpe_u32, [...]): Rewrite using builtin functions. | Felix Yang | 1 | -0/+3 |
| 2014-12-03 | [AArch64] Remove/merge redundant iterators | Alan Lawrence | 1 | -26/+1 |
| 2014-11-21 | [AArch64] Add vector pattern for __builtin_ctz | Jiong Wang | 1 | -0/+6 |
| 2014-11-17 | aarch64-builtins.c (TYPES_CREATE): Remove. | Alan Lawrence | 1 | -3/+0 |
| 2014-11-04 | [AArch64] Fix predicate and constraint mismatch in logical atomic operations | Michael Collison | 1 | -0/+3 |
| 2014-10-27 | [AArch64] Use new reduc_plus_scal optabs, inc. for __builtins | Alan Lawrence | 1 | -5/+1 |
| 2014-09-25 | [AArch64] Tighten predicates on SIMD shift intrinsics | James Greenhalgh | 1 | -2/+11 |
| 2014-09-22 | [AArch64] Auto-generate the "BUILTIN_" macros for aarch64-builtins.c | James Greenhalgh | 1 | -0/+3 |
| 2014-09-11 | [AArch64] Simplify vreinterpret for float64x1_t using casts. | Alan Lawrence | 1 | -3/+0 |
| 2014-09-04 | re PR target/62040 (internal compiler error: in simplify_const_unary_operatio... | Guozhi Wei | 1 | -0/+6 |
| 2014-06-23 | PR/60825 Make float64x1_t in arm_neon.h a proper vector type | Alan Lawrence | 1 | -2/+5 |
| 2014-06-20 | [AArch64] Fix some saturating math NEON intrinsics types. | Kyrylo Tkachov | 1 | -12/+4 |
| 2014-06-11 | [AArch64] Implement CRC32 ACLE intrinsics. | Kyrylo Tkachov | 1 | -0/+14 |
| 2014-06-03 | Recognize shuffle patterns for REV instructions on AArch64, rewrite intrinsics. | Alan Lawrence | 1 | -0/+9 |
